drivers/pci/fsl_pci_init.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /*
  24  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  25  *
  26  * Initialize controller and call the common driver/pci pci_hose_scan to
  27  * scan for bridges and devices.
  28  *
  29  * Hose fields which need to be pre-initialized by board specific code:
  30  *   regions[]
  31  *   first_busno
  32  *
  33  * Fields updated:
  34  *   last_busno
  35  */
  36
  37 #include <pci.h>
  38 #include <asm/io.h>
  39 #include <asm/fsl_pci.h>
  40
  41 /* Freescale-specific PCI config registers */
  42 #define FSL_PCI_PBFR            0x44
  43 #define FSL_PCIE_CAP_ID         0x4c
  44 #define FSL_PCIE_CFG_RDY        0x4b0
  45 #define FSL_PROG_IF_AGENT       0x1
  46
  47 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  48                                 pci_dev_t dev, int sub_bus);
  49 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  50                                 pci_dev_t dev, int sub_bus);
  51 void pciauto_config_init(struct pci_controller *hose);
  52
  53 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  54 #define CONFIG_SYS_PCI_MEMORY_BUS 0
  55 #endif
  56
  57 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  58 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  59 #endif
  60
  61 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  62 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  63 #endif
  64
  65 /* Setup one inbound ATMU window.
  66  *
  67  * We let the caller decide what the window size should be
  68  */
  69 static void set_inbound_window(volatile pit_t *pi,
  70                                 struct pci_region *r,
  71                                 u64 size)
  72 {
  73         u32 sz = (__ilog2_u64(size) - 1);
  74         u32 flag = PIWAR_EN | PIWAR_LOCAL |
  75                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  76
  77         out_be32(&pi->pitar, r->phys_start >> 12);
  78         out_be32(&pi->piwbar, r->bus_start >> 12);
  79 #ifdef CONFIG_SYS_PCI_64BIT
  80         out_be32(&pi->piwbear, r->bus_start >> 44);
  81 #else
  82         out_be32(&pi->piwbear, 0);
  83 #endif
  84         if (r->flags & PCI_REGION_PREFETCH)
  85                 flag |= PIWAR_PF;
  86         out_be32(&pi->piwar, flag | sz);
  87 }
  88
  89 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
  90                                          u64 out_lo, u8 pcie_cap,
  91                                          volatile pit_t *pi)
  92 {
  93         struct pci_region *r = hose->regions + hose->region_count;
  94         u64 sz = min((u64)gd->ram_size, (1ull << 32));
  95
  96         phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  97         pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  98         pci_size_t pci_sz;
  99
 100         /* we have no space available for inbound memory mapping */
 101         if (bus_start > out_lo) {
 102                 printf ("no space for inbound mapping of memory\n");
 103                 return 0;
 104         }
 105
 106         /* limit size */
 107         if ((bus_start + sz) > out_lo) {
 108                 sz = out_lo - bus_start;
 109                 debug ("limiting size to %llx\n", sz);
 110         }
 111
 112         pci_sz = 1ull << __ilog2_u64(sz);
 113         /*
 114          * we can overlap inbound/outbound windows on PCI-E since RX & TX
 115          * links a separate
 116          */
 117         if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
 118                 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
 119                         (u64)bus_start, (u64)phys_start, (u64)sz);
 120                 pci_set_region(r, bus_start, phys_start, sz,
 121                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 122                                 PCI_REGION_PREFETCH);
 123
 124                 /* if we aren't an exact power of two match, pci_sz is smaller
 125                  * round it up to the next power of two.  We report the actual
 126                  * size to pci region tracking.
 127                  */
 128                 if (pci_sz != sz)
 129                         sz = 2ull << __ilog2_u64(sz);
 130
 131                 set_inbound_window(pi--, r++, sz);
 132                 sz = 0; /* make sure we dont set the R2 window */
 133         } else {
 134                 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
 135                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 136                 pci_set_region(r, bus_start, phys_start, pci_sz,
 137                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 138                                 PCI_REGION_PREFETCH);
 139                 set_inbound_window(pi--, r++, pci_sz);
 140
 141                 sz -= pci_sz;
 142                 bus_start += pci_sz;
 143                 phys_start += pci_sz;
 144
 145                 pci_sz = 1ull << __ilog2_u64(sz);
 146                 if (sz) {
 147                         debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
 148                                 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 149                         pci_set_region(r, bus_start, phys_start, pci_sz,
 150                                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 151                                         PCI_REGION_PREFETCH);
 152                         set_inbound_window(pi--, r++, pci_sz);
 153                         sz -= pci_sz;
 154                         bus_start += pci_sz;
 155                         phys_start += pci_sz;
 156                 }
 157         }
 158
 159 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
 160         /*
 161          * On 64-bit capable systems, set up a mapping for all of DRAM
 162          * in high pci address space.
 163          */
 164         pci_sz = 1ull << __ilog2_u64(gd->ram_size);
 165         /* round up to the next largest power of two */
 166         if (gd->ram_size > pci_sz)
 167                 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
 168         debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
 169                 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
 170                 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
 171                 (u64)pci_sz);
 172         pci_set_region(r,
 173                         CONFIG_SYS_PCI64_MEMORY_BUS,
 174                         CONFIG_SYS_PCI_MEMORY_PHYS,
 175                         pci_sz,
 176                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 177                         PCI_REGION_PREFETCH);
 178         set_inbound_window(pi--, r++, pci_sz);
 179 #else
 180         pci_sz = 1ull << __ilog2_u64(sz);
 181         if (sz) {
 182                 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
 183                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 184                 pci_set_region(r, bus_start, phys_start, pci_sz,
 185                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 186                                 PCI_REGION_PREFETCH);
 187                 sz -= pci_sz;
 188                 bus_start += pci_sz;
 189                 phys_start += pci_sz;
 190                 set_inbound_window(pi--, r++, pci_sz);
 191         }
 192 #endif
 193
 194 #ifdef CONFIG_PHYS_64BIT
 195         if (sz && (((u64)gd->ram_size) < (1ull << 32)))
 196                 printf("Was not able to map all of memory via "
 197                         "inbound windows -- %lld remaining\n", sz);
 198 #endif
 199
 200         hose->region_count = r - hose->regions;
 201
 202         return 1;
 203 }
 204
 205 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 206 {
 207         u16 temp16;
 208         u32 temp32;
 209         int enabled, r, inbound = 0;
 210         u16 ltssm;
 211         u8 temp8, pcie_cap;
 212         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
 213         struct pci_region *reg = hose->regions + hose->region_count;
 214         pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 215
 216         /* Initialize ATMU registers based on hose regions and flags */
 217         volatile pot_t *po = &pci->pot[1];      /* skip 0 */
 218         volatile pit_t *pi = &pci->pit[2];      /* ranges from: 3 to 1 */
 219
 220         u64 out_hi = 0, out_lo = -1ULL;
 221         u32 pcicsrbar, pcicsrbar_sz;
 222
 223 #ifdef DEBUG
 224         int neg_link_w;
 225 #endif
 226
 227         pci_setup_indirect(hose, cfg_addr, cfg_data);
 228
 229         /* Handle setup of outbound windows first */
 230         for (r = 0; r < hose->region_count; r++) {
 231                 unsigned long flags = hose->regions[r].flags;
 232                 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
 233
 234                 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
 235                 if (flags != PCI_REGION_SYS_MEMORY) {
 236                         u64 start = hose->regions[r].bus_start;
 237                         u64 end = start + hose->regions[r].size;
 238
 239                         out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
 240                         out_be32(&po->potar, start >> 12);
 241 #ifdef CONFIG_SYS_PCI_64BIT
 242                         out_be32(&po->potear, start >> 44);
 243 #else
 244                         out_be32(&po->potear, 0);
 245 #endif
 246                         if (hose->regions[r].flags & PCI_REGION_IO) {
 247                                 out_be32(&po->powar, POWAR_EN | sz |
 248                                         POWAR_IO_READ | POWAR_IO_WRITE);
 249                         } else {
 250                                 out_be32(&po->powar, POWAR_EN | sz |
 251                                         POWAR_MEM_READ | POWAR_MEM_WRITE);
 252                                 out_lo = min(start, out_lo);
 253                                 out_hi = max(end, out_hi);
 254                         }
 255                         po++;
 256                 }
 257         }
 258         debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
 259
 260         /* setup PCSRBAR/PEXCSRBAR */
 261         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 262         pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
 263         pcicsrbar_sz = ~pcicsrbar_sz + 1;
 264
 265         if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
 266                 (out_lo > 0x100000000ull))
 267                 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
 268         else
 269                 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
 270         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
 271
 272         out_lo = min(out_lo, (u64)pcicsrbar);
 273
 274         debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
 275
 276         pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
 277                         pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
 278         hose->region_count++;
 279
 280         /* see if we are a PCIe or PCI controller */
 281         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 282
 283         /* inbound */
 284         inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
 285
 286         for (r = 0; r < hose->region_count; r++)
 287                 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
 288                         (u64)hose->regions[r].phys_start,
 289                         hose->regions[r].bus_start,
 290                         hose->regions[r].size,
 291                         hose->regions[r].flags);
 292
 293         pci_register_hose(hose);
 294         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
 295         hose->current_busno = hose->first_busno;
 296
 297         out_be32(&pci->pedr, 0xffffffff);       /* Clear any errors */
 298         out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
 299                                          * - Master abort (pci)
 300                                          * - Master PERR (pci)
 301                                          * - ICCA (PCIe)
 302                                          */
 303         pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
 304         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
 305         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 306
 307         if (pcie_cap == PCI_CAP_ID_EXP) {
 308                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 309                 enabled = ltssm >= PCI_LTSSM_L0;
 310
 311 #ifdef CONFIG_FSL_PCIE_RESET
 312                 if (ltssm == 1) {
 313                         int i;
 314                         debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
 315                         /* assert PCIe reset */
 316                         setbits_be32(&pci->pdb_stat, 0x08000000);
 317                         (void) in_be32(&pci->pdb_stat);
 318                         udelay(100);
 319                         debug("  Asserting PCIe reset @%x = %x\n",
 320                               &pci->pdb_stat, in_be32(&pci->pdb_stat));
 321                         /* clear PCIe reset */
 322                         clrbits_be32(&pci->pdb_stat, 0x08000000);
 323                         asm("sync;isync");
 324                         for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
 325                                 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
 326                                                         &ltssm);
 327                                 udelay(1000);
 328                                 debug("....PCIe link error. "
 329                                       "LTSSM=0x%02x.\n", ltssm);
 330                         }
 331                         enabled = ltssm >= PCI_LTSSM_L0;
 332
 333                         /* we need to re-write the bar0 since a reset will
 334                          * clear it
 335                          */
 336                         pci_hose_write_config_dword(hose, dev,
 337                                         PCI_BASE_ADDRESS_0, pcicsrbar);
 338                 }
 339 #endif
 340
 341                 if (!enabled) {
 342                         debug("....PCIE link error.  Skipping scan."
 343                               "LTSSM=0x%02x\n", ltssm);
 344                         hose->last_busno = hose->first_busno;
 345                         return;
 346                 }
 347
 348                 out_be32(&pci->pme_msg_det, 0xffffffff);
 349                 out_be32(&pci->pme_msg_int_en, 0xffffffff);
 350 #ifdef DEBUG
 351                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 352                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 353                 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 354                       ltssm, neg_link_w);
 355 #endif
 356                 hose->current_busno++; /* Start scan with secondary */
 357                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 358         }
 359
 360         /* Use generic setup_device to initialize standard pci regs,
 361          * but do not allocate any windows since any BAR found (such
 362          * as PCSRBAR) is not in this cpu's memory space.
 363          */
 364         pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 365                              hose->pci_prefetch, hose->pci_io);
 366
 367         if (inbound) {
 368                 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
 369                 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 370                                            temp16 | PCI_COMMAND_MEMORY);
 371         }
 372
 373 #ifndef CONFIG_PCI_NOSCAN
 374         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
 375
 376         /* Programming Interface (PCI_CLASS_PROG)
 377          * 0 == pci host or pcie root-complex,
 378          * 1 == pci agent or pcie end-point
 379          */
 380         if (!temp8) {
 381                 printf("               Scanning PCI bus %02x\n",
 382                         hose->current_busno);
 383                 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
 384         } else {
 385                 debug("               Not scanning PCI bus %02x. PI=%x\n",
 386                         hose->current_busno, temp8);
 387                 hose->last_busno = hose->current_busno;
 388         }
 389
 390         /* if we are PCIe - update limit regs and subordinate busno
 391          * for the virtual P2P bridge
 392          */
 393         if (pcie_cap == PCI_CAP_ID_EXP) {
 394                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 395         }
 396 #else
 397         hose->last_busno = hose->current_busno;
 398 #endif
 399
 400         /* Clear all error indications */
 401         if (pcie_cap == PCI_CAP_ID_EXP)
 402                 out_be32(&pci->pme_msg_det, 0xffffffff);
 403         out_be32(&pci->pedr, 0xffffffff);
 404
 405         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 406         if (temp16) {
 407                 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
 408         }
 409
 410         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 411         if (temp16) {
 412                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 413         }
 414 }
 415
 416 int fsl_is_pci_agent(struct pci_controller *hose)
 417 {
 418         u8 prog_if;
 419         pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 420
 421         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
 422
 423         return (prog_if == FSL_PROG_IF_AGENT);
 424 }
 425
 426 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 427                         struct pci_controller *hose, int busno)
 428 {
 429         volatile ccsr_fsl_pci_t *pci;
 430         struct pci_region *r;
 431
 432         pci = (ccsr_fsl_pci_t *) pci_info->regs;
 433
 434         /* on non-PCIe controllers we don't have pme_msg_det so this code
 435          * should do nothing since the read will return 0
 436          */
 437         if (in_be32(&pci->pme_msg_det)) {
 438                 out_be32(&pci->pme_msg_det, 0xffffffff);
 439                 debug (" with errors.  Clearing.  Now 0x%08x",
 440                         pci->pme_msg_det);
 441         }
 442
 443         r = hose->regions + hose->region_count;
 444
 445         /* outbound memory */
 446         pci_set_region(r++,
 447                         pci_info->mem_bus,
 448                         pci_info->mem_phys,
 449                         pci_info->mem_size,
 450                         PCI_REGION_MEM);
 451
 452         /* outbound io */
 453         pci_set_region(r++,
 454                         pci_info->io_bus,
 455                         pci_info->io_phys,
 456                         pci_info->io_size,
 457                         PCI_REGION_IO);
 458
 459         hose->region_count = r - hose->regions;
 460         hose->first_busno = busno;
 461
 462         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 463
 464         if (fsl_is_pci_agent(hose)) {
 465                 fsl_pci_config_unlock(hose);
 466                 hose->last_busno = hose->first_busno;
 467         }
 468
 469         printf("    PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
 470                         hose->first_busno, hose->last_busno);
 471
 472         return(hose->last_busno + 1);
 473 }
 474
 475 /* Enable inbound PCI config cycles for agent/endpoint interface */
 476 void fsl_pci_config_unlock(struct pci_controller *hose)
 477 {
 478         pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
 479         u8 agent;
 480         u8 pcie_cap;
 481         u16 pbfr;
 482
 483         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
 484         if (!agent)
 485                 return;
 486
 487         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 488         if (pcie_cap != 0x0) {
 489                 /* PCIe - set CFG_READY bit of Configuration Ready Register */
 490                 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
 491         } else {
 492                 /* PCI - clear ACL bit of PBFR */
 493                 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
 494                 pbfr &= ~0x20;
 495                 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
 496         }
 497 }
 498
 499 #ifdef CONFIG_OF_BOARD_SETUP
 500 #include <libfdt.h>
 501 #include <fdt_support.h>
 502
 503 void ft_fsl_pci_setup(void *blob, const char *pci_alias,
 504                         struct pci_controller *hose)
 505 {
 506         int off = fdt_path_offset(blob, pci_alias);
 507
 508         if (off >= 0) {
 509                 u32 bus_range[2];
 510
 511                 bus_range[0] = 0;
 512                 bus_range[1] = hose->last_busno - hose->first_busno;
 513                 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
 514                 fdt_pci_dma_ranges(blob, off, hose);
 515         }
 516 }
 517 #endif