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git.ipfire.org Git - people/ms/u-boot.git/blob - drivers/pci/fsl_pci_init.c
2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifdef CONFIG_FSL_PCI_INIT
24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
26 * Initialize controller and call the common driver/pci pci_hose_scan to
27 * scan for bridges and devices.
29 * Hose fields which need to be pre-initialized by board specific code:
38 #include <asm/immap_fsl_pci.h>
40 void pciauto_prescan_setup_bridge(struct pci_controller
*hose
,
41 pci_dev_t dev
, int sub_bus
);
42 void pciauto_postscan_setup_bridge(struct pci_controller
*hose
,
43 pci_dev_t dev
, int sub_bus
);
45 void pciauto_config_init(struct pci_controller
*hose
);
47 fsl_pci_init(struct pci_controller
*hose
)
51 int busno
= hose
->first_busno
;
58 volatile ccsr_fsl_pci_t
*pci
= (ccsr_fsl_pci_t
*) hose
->cfg_addr
;
59 pci_dev_t dev
= PCI_BDF(busno
,0,0);
61 /* Initialize ATMU registers based on hose regions and flags */
62 volatile pot_t
*po
=&pci
->pot
[1]; /* skip 0 */
63 volatile pit_t
*pi
=&pci
->pit
[0]; /* ranges from: 3 to 1 */
69 for (r
=0; r
<hose
->region_count
; r
++) {
70 if (hose
->regions
[r
].flags
& PCI_REGION_MEMORY
) { /* inbound */
71 pi
->pitar
= (hose
->regions
[r
].bus_start
>> 12) & 0x000fffff;
72 pi
->piwbar
= (hose
->regions
[r
].phys_start
>> 12) & 0x000fffff;
74 pi
->piwar
= PIWAR_EN
| PIWAR_PF
| PIWAR_LOCAL
|
75 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
|
76 (__ilog2(hose
->regions
[r
].size
) - 1);
78 inbound
= hose
->regions
[r
].size
> 0;
79 } else { /* Outbound */
80 po
->powbar
= (hose
->regions
[r
].phys_start
>> 12) & 0x000fffff;
81 po
->potar
= (hose
->regions
[r
].bus_start
>> 12) & 0x000fffff;
83 if (hose
->regions
[r
].flags
& PCI_REGION_IO
)
84 po
->powar
= POWAR_EN
| POWAR_IO_READ
| POWAR_IO_WRITE
|
85 (__ilog2(hose
->regions
[r
].size
) - 1);
87 po
->powar
= POWAR_EN
| POWAR_MEM_READ
| POWAR_MEM_WRITE
|
88 (__ilog2(hose
->regions
[r
].size
) - 1);
93 pci_register_hose(hose
);
94 pciauto_config_init(hose
); /* grab pci_{mem,prefetch,io} */
95 hose
->current_busno
= hose
->first_busno
;
97 pci
->pedr
= 0xffffffff; /* Clear any errors */
98 pci
->peer
= ~0x20140; /* Enable All Error Interupts except
99 * - Master abort (pci)
100 * - Master PERR (pci)
103 pci_hose_read_config_dword (hose
, dev
, PCI_DCR
, &temp32
);
104 temp32
|= 0xf000e; /* set URR, FER, NFER (but not CER) */
105 pci_hose_write_config_dword(hose
, dev
, PCI_DCR
, temp32
);
107 pci_hose_read_config_byte (hose
, dev
, PCI_HEADER_TYPE
, &temp8
);
108 bridge
= temp8
& PCI_HEADER_TYPE_BRIDGE
; /* Bridge, such as pcie */
112 pci_hose_read_config_word(hose
, dev
, PCI_LTSSM
, <ssm
);
113 enabled
= ltssm
>= PCI_LTSSM_L0
;
115 #ifdef CONFIG_FSL_PCIE_RESET
118 debug("....PCIe link error. "
119 "LTSSM=0x%02x.", ltssm
);
120 pci
->pdb_stat
|= 0x08000000; /* assert PCIe reset */
121 temp32
= pci
->pdb_stat
;
123 debug(" Asserting PCIe reset @%x = %x\n",
124 &pci
->pdb_stat
, pci
->pdb_stat
);
125 pci
->pdb_stat
&= ~0x08000000; /* clear reset */
127 for (i
=0; i
<100 && ltssm
< PCI_LTSSM_L0
; i
++) {
128 pci_hose_read_config_word(hose
, dev
, PCI_LTSSM
,
131 debug("....PCIe link error. "
132 "LTSSM=0x%02x.\n", ltssm
);
134 enabled
= ltssm
>= PCI_LTSSM_L0
;
139 debug("....PCIE link error. Skipping scan."
140 "LTSSM=0x%02x\n", ltssm
);
141 hose
->last_busno
= hose
->first_busno
;
145 pci
->pme_msg_det
= 0xffffffff;
146 pci
->pme_msg_int_en
= 0xffffffff;
148 pci_hose_read_config_word(hose
, dev
, PCI_LSR
, &temp16
);
149 neg_link_w
= (temp16
& 0x3f0 ) >> 4;
150 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
153 hose
->current_busno
++; /* Start scan with secondary */
154 pciauto_prescan_setup_bridge(hose
, dev
, hose
->current_busno
);
158 /* Use generic setup_device to initialize standard pci regs,
159 * but do not allocate any windows since any BAR found (such
160 * as PCSRBAR) is not in this cpu's memory space.
163 pciauto_setup_device(hose
, dev
, 0, hose
->pci_mem
,
164 hose
->pci_prefetch
, hose
->pci_io
);
167 pci_hose_read_config_word(hose
, dev
, PCI_COMMAND
, &temp16
);
168 pci_hose_write_config_word(hose
, dev
, PCI_COMMAND
,
169 temp16
| PCI_COMMAND_MEMORY
);
172 #ifndef CONFIG_PCI_NOSCAN
173 printf (" Scanning PCI bus %02x\n", hose
->current_busno
);
174 hose
->last_busno
= pci_hose_scan_bus(hose
,hose
->current_busno
);
176 if ( bridge
) { /* update limit regs and subordinate busno */
177 pciauto_postscan_setup_bridge(hose
, dev
, hose
->last_busno
);
180 hose
->last_busno
= hose
->current_busno
;
183 /* Clear all error indications */
185 pci
->pme_msg_det
= 0xffffffff;
186 pci
->pedr
= 0xffffffff;
188 pci_hose_read_config_word (hose
, dev
, PCI_DSR
, &temp16
);
190 pci_hose_write_config_word(hose
, dev
,
194 pci_hose_read_config_word (hose
, dev
, PCI_SEC_STATUS
, &temp16
);
196 pci_hose_write_config_word(hose
, dev
, PCI_SEC_STATUS
, 0xffff);
200 #endif /* CONFIG_FSL_PCI */