drivers/pci/fsl_pci_init.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  17  * MA 02111-1307 USA
  18  */
  19
  20 #include <common.h>
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 /*
  25  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  26  *
  27  * Initialize controller and call the common driver/pci pci_hose_scan to
  28  * scan for bridges and devices.
  29  *
  30  * Hose fields which need to be pre-initialized by board specific code:
  31  *   regions[]
  32  *   first_busno
  33  *
  34  * Fields updated:
  35  *   last_busno
  36  */
  37
  38 #include <pci.h>
  39 #include <asm/io.h>
  40 #include <asm/fsl_pci.h>
  41
  42 /* Freescale-specific PCI config registers */
  43 #define FSL_PCI_PBFR            0x44
  44 #define FSL_PCIE_CAP_ID         0x4c
  45 #define FSL_PCIE_CFG_RDY        0x4b0
  46 #define FSL_PROG_IF_AGENT       0x1
  47
  48 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  49                                 pci_dev_t dev, int sub_bus);
  50 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  51                                 pci_dev_t dev, int sub_bus);
  52 void pciauto_config_init(struct pci_controller *hose);
  53
  54 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  55 #define CONFIG_SYS_PCI_MEMORY_BUS 0
  56 #endif
  57
  58 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  59 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
  60 #endif
  61
  62 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
  63 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
  64 #endif
  65
  66 /* Setup one inbound ATMU window.
  67  *
  68  * We let the caller decide what the window size should be
  69  */
  70 static void set_inbound_window(volatile pit_t *pi,
  71                                 struct pci_region *r,
  72                                 u64 size)
  73 {
  74         u32 sz = (__ilog2_u64(size) - 1);
  75         u32 flag = PIWAR_EN | PIWAR_LOCAL |
  76                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  77
  78         out_be32(&pi->pitar, r->phys_start >> 12);
  79         out_be32(&pi->piwbar, r->bus_start >> 12);
  80 #ifdef CONFIG_SYS_PCI_64BIT
  81         out_be32(&pi->piwbear, r->bus_start >> 44);
  82 #else
  83         out_be32(&pi->piwbear, 0);
  84 #endif
  85         if (r->flags & PCI_REGION_PREFETCH)
  86                 flag |= PIWAR_PF;
  87         out_be32(&pi->piwar, flag | sz);
  88 }
  89
  90 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
  91 {
  92         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
  93
  94         /* Reset hose to make sure its in a clean state */
  95         memset(hose, 0, sizeof(struct pci_controller));
  96
  97         pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
  98
  99         return fsl_is_pci_agent(hose);
 100 }
 101
 102 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
 103                                          u64 out_lo, u8 pcie_cap,
 104                                          volatile pit_t *pi)
 105 {
 106         struct pci_region *r = hose->regions + hose->region_count;
 107         u64 sz = min((u64)gd->ram_size, (1ull << 32));
 108
 109         phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
 110         pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
 111         pci_size_t pci_sz;
 112
 113         /* we have no space available for inbound memory mapping */
 114         if (bus_start > out_lo) {
 115                 printf ("no space for inbound mapping of memory\n");
 116                 return 0;
 117         }
 118
 119         /* limit size */
 120         if ((bus_start + sz) > out_lo) {
 121                 sz = out_lo - bus_start;
 122                 debug ("limiting size to %llx\n", sz);
 123         }
 124
 125         pci_sz = 1ull << __ilog2_u64(sz);
 126         /*
 127          * we can overlap inbound/outbound windows on PCI-E since RX & TX
 128          * links a separate
 129          */
 130         if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
 131                 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
 132                         (u64)bus_start, (u64)phys_start, (u64)sz);
 133                 pci_set_region(r, bus_start, phys_start, sz,
 134                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 135                                 PCI_REGION_PREFETCH);
 136
 137                 /* if we aren't an exact power of two match, pci_sz is smaller
 138                  * round it up to the next power of two.  We report the actual
 139                  * size to pci region tracking.
 140                  */
 141                 if (pci_sz != sz)
 142                         sz = 2ull << __ilog2_u64(sz);
 143
 144                 set_inbound_window(pi--, r++, sz);
 145                 sz = 0; /* make sure we dont set the R2 window */
 146         } else {
 147                 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
 148                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 149                 pci_set_region(r, bus_start, phys_start, pci_sz,
 150                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 151                                 PCI_REGION_PREFETCH);
 152                 set_inbound_window(pi--, r++, pci_sz);
 153
 154                 sz -= pci_sz;
 155                 bus_start += pci_sz;
 156                 phys_start += pci_sz;
 157
 158                 pci_sz = 1ull << __ilog2_u64(sz);
 159                 if (sz) {
 160                         debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
 161                                 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 162                         pci_set_region(r, bus_start, phys_start, pci_sz,
 163                                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 164                                         PCI_REGION_PREFETCH);
 165                         set_inbound_window(pi--, r++, pci_sz);
 166                         sz -= pci_sz;
 167                         bus_start += pci_sz;
 168                         phys_start += pci_sz;
 169                 }
 170         }
 171
 172 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
 173         /*
 174          * On 64-bit capable systems, set up a mapping for all of DRAM
 175          * in high pci address space.
 176          */
 177         pci_sz = 1ull << __ilog2_u64(gd->ram_size);
 178         /* round up to the next largest power of two */
 179         if (gd->ram_size > pci_sz)
 180                 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
 181         debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
 182                 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
 183                 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
 184                 (u64)pci_sz);
 185         pci_set_region(r,
 186                         CONFIG_SYS_PCI64_MEMORY_BUS,
 187                         CONFIG_SYS_PCI_MEMORY_PHYS,
 188                         pci_sz,
 189                         PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 190                         PCI_REGION_PREFETCH);
 191         set_inbound_window(pi--, r++, pci_sz);
 192 #else
 193         pci_sz = 1ull << __ilog2_u64(sz);
 194         if (sz) {
 195                 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
 196                         (u64)bus_start, (u64)phys_start, (u64)pci_sz);
 197                 pci_set_region(r, bus_start, phys_start, pci_sz,
 198                                 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
 199                                 PCI_REGION_PREFETCH);
 200                 sz -= pci_sz;
 201                 bus_start += pci_sz;
 202                 phys_start += pci_sz;
 203                 set_inbound_window(pi--, r++, pci_sz);
 204         }
 205 #endif
 206
 207 #ifdef CONFIG_PHYS_64BIT
 208         if (sz && (((u64)gd->ram_size) < (1ull << 32)))
 209                 printf("Was not able to map all of memory via "
 210                         "inbound windows -- %lld remaining\n", sz);
 211 #endif
 212
 213         hose->region_count = r - hose->regions;
 214
 215         return 1;
 216 }
 217
 218 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
 219 {
 220         u16 temp16;
 221         u32 temp32;
 222         int enabled, r, inbound = 0;
 223         u16 ltssm;
 224         u8 temp8, pcie_cap;
 225         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
 226         struct pci_region *reg = hose->regions + hose->region_count;
 227         pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 228
 229         /* Initialize ATMU registers based on hose regions and flags */
 230         volatile pot_t *po = &pci->pot[1];      /* skip 0 */
 231         volatile pit_t *pi = &pci->pit[2];      /* ranges from: 3 to 1 */
 232
 233         u64 out_hi = 0, out_lo = -1ULL;
 234         u32 pcicsrbar, pcicsrbar_sz;
 235
 236 #ifdef DEBUG
 237         int neg_link_w;
 238 #endif
 239
 240         pci_setup_indirect(hose, cfg_addr, cfg_data);
 241
 242         /* Handle setup of outbound windows first */
 243         for (r = 0; r < hose->region_count; r++) {
 244                 unsigned long flags = hose->regions[r].flags;
 245                 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
 246
 247                 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
 248                 if (flags != PCI_REGION_SYS_MEMORY) {
 249                         u64 start = hose->regions[r].bus_start;
 250                         u64 end = start + hose->regions[r].size;
 251
 252                         out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
 253                         out_be32(&po->potar, start >> 12);
 254 #ifdef CONFIG_SYS_PCI_64BIT
 255                         out_be32(&po->potear, start >> 44);
 256 #else
 257                         out_be32(&po->potear, 0);
 258 #endif
 259                         if (hose->regions[r].flags & PCI_REGION_IO) {
 260                                 out_be32(&po->powar, POWAR_EN | sz |
 261                                         POWAR_IO_READ | POWAR_IO_WRITE);
 262                         } else {
 263                                 out_be32(&po->powar, POWAR_EN | sz |
 264                                         POWAR_MEM_READ | POWAR_MEM_WRITE);
 265                                 out_lo = min(start, out_lo);
 266                                 out_hi = max(end, out_hi);
 267                         }
 268                         po++;
 269                 }
 270         }
 271         debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
 272
 273         /* setup PCSRBAR/PEXCSRBAR */
 274         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 275         pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
 276         pcicsrbar_sz = ~pcicsrbar_sz + 1;
 277
 278         if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
 279                 (out_lo > 0x100000000ull))
 280                 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
 281         else
 282                 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
 283         pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
 284
 285         out_lo = min(out_lo, (u64)pcicsrbar);
 286
 287         debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
 288
 289         pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
 290                         pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
 291         hose->region_count++;
 292
 293         /* see if we are a PCIe or PCI controller */
 294         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 295
 296         /* inbound */
 297         inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
 298
 299         for (r = 0; r < hose->region_count; r++)
 300                 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
 301                         (u64)hose->regions[r].phys_start,
 302                         hose->regions[r].bus_start,
 303                         hose->regions[r].size,
 304                         hose->regions[r].flags);
 305
 306         pci_register_hose(hose);
 307         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
 308         hose->current_busno = hose->first_busno;
 309
 310         out_be32(&pci->pedr, 0xffffffff);       /* Clear any errors */
 311         out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
 312                                          * - Master abort (pci)
 313                                          * - Master PERR (pci)
 314                                          * - ICCA (PCIe)
 315                                          */
 316         pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
 317         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
 318         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 319
 320         if (pcie_cap == PCI_CAP_ID_EXP) {
 321                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 322                 enabled = ltssm >= PCI_LTSSM_L0;
 323
 324 #ifdef CONFIG_FSL_PCIE_RESET
 325                 if (ltssm == 1) {
 326                         int i;
 327                         debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
 328                         /* assert PCIe reset */
 329                         setbits_be32(&pci->pdb_stat, 0x08000000);
 330                         (void) in_be32(&pci->pdb_stat);
 331                         udelay(100);
 332                         debug("  Asserting PCIe reset @%x = %x\n",
 333                               &pci->pdb_stat, in_be32(&pci->pdb_stat));
 334                         /* clear PCIe reset */
 335                         clrbits_be32(&pci->pdb_stat, 0x08000000);
 336                         asm("sync;isync");
 337                         for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
 338                                 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
 339                                                         &ltssm);
 340                                 udelay(1000);
 341                                 debug("....PCIe link error. "
 342                                       "LTSSM=0x%02x.\n", ltssm);
 343                         }
 344                         enabled = ltssm >= PCI_LTSSM_L0;
 345
 346                         /* we need to re-write the bar0 since a reset will
 347                          * clear it
 348                          */
 349                         pci_hose_write_config_dword(hose, dev,
 350                                         PCI_BASE_ADDRESS_0, pcicsrbar);
 351                 }
 352 #endif
 353
 354                 if (!enabled) {
 355                         debug("....PCIE link error.  Skipping scan."
 356                               "LTSSM=0x%02x\n", ltssm);
 357                         hose->last_busno = hose->first_busno;
 358                         return;
 359                 }
 360
 361                 out_be32(&pci->pme_msg_det, 0xffffffff);
 362                 out_be32(&pci->pme_msg_int_en, 0xffffffff);
 363 #ifdef DEBUG
 364                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 365                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 366                 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 367                       ltssm, neg_link_w);
 368 #endif
 369                 hose->current_busno++; /* Start scan with secondary */
 370                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 371         }
 372
 373         /* Use generic setup_device to initialize standard pci regs,
 374          * but do not allocate any windows since any BAR found (such
 375          * as PCSRBAR) is not in this cpu's memory space.
 376          */
 377         pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 378                              hose->pci_prefetch, hose->pci_io);
 379
 380         if (inbound) {
 381                 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
 382                 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
 383                                            temp16 | PCI_COMMAND_MEMORY);
 384         }
 385
 386 #ifndef CONFIG_PCI_NOSCAN
 387         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
 388
 389         /* Programming Interface (PCI_CLASS_PROG)
 390          * 0 == pci host or pcie root-complex,
 391          * 1 == pci agent or pcie end-point
 392          */
 393         if (!temp8) {
 394                 printf("               Scanning PCI bus %02x\n",
 395                         hose->current_busno);
 396                 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
 397         } else {
 398                 debug("               Not scanning PCI bus %02x. PI=%x\n",
 399                         hose->current_busno, temp8);
 400                 hose->last_busno = hose->current_busno;
 401         }
 402
 403         /* if we are PCIe - update limit regs and subordinate busno
 404          * for the virtual P2P bridge
 405          */
 406         if (pcie_cap == PCI_CAP_ID_EXP) {
 407                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 408         }
 409 #else
 410         hose->last_busno = hose->current_busno;
 411 #endif
 412
 413         /* Clear all error indications */
 414         if (pcie_cap == PCI_CAP_ID_EXP)
 415                 out_be32(&pci->pme_msg_det, 0xffffffff);
 416         out_be32(&pci->pedr, 0xffffffff);
 417
 418         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 419         if (temp16) {
 420                 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
 421         }
 422
 423         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 424         if (temp16) {
 425                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 426         }
 427 }
 428
 429 int fsl_is_pci_agent(struct pci_controller *hose)
 430 {
 431         u8 prog_if;
 432         pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
 433
 434         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
 435
 436         return (prog_if == FSL_PROG_IF_AGENT);
 437 }
 438
 439 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 440                         struct pci_controller *hose, int busno)
 441 {
 442         volatile ccsr_fsl_pci_t *pci;
 443         struct pci_region *r;
 444         pci_dev_t dev = PCI_BDF(busno,0,0);
 445         u8 pcie_cap;
 446
 447         pci = (ccsr_fsl_pci_t *) pci_info->regs;
 448
 449         /* on non-PCIe controllers we don't have pme_msg_det so this code
 450          * should do nothing since the read will return 0
 451          */
 452         if (in_be32(&pci->pme_msg_det)) {
 453                 out_be32(&pci->pme_msg_det, 0xffffffff);
 454                 debug (" with errors.  Clearing.  Now 0x%08x",
 455                         pci->pme_msg_det);
 456         }
 457
 458         r = hose->regions + hose->region_count;
 459
 460         /* outbound memory */
 461         pci_set_region(r++,
 462                         pci_info->mem_bus,
 463                         pci_info->mem_phys,
 464                         pci_info->mem_size,
 465                         PCI_REGION_MEM);
 466
 467         /* outbound io */
 468         pci_set_region(r++,
 469                         pci_info->io_bus,
 470                         pci_info->io_phys,
 471                         pci_info->io_size,
 472                         PCI_REGION_IO);
 473
 474         hose->region_count = r - hose->regions;
 475         hose->first_busno = busno;
 476
 477         fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
 478
 479         if (fsl_is_pci_agent(hose)) {
 480                 fsl_pci_config_unlock(hose);
 481                 hose->last_busno = hose->first_busno;
 482         }
 483
 484         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 485         printf("    PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
 486                         "E" : "", pci_info->pci_num,
 487                         hose->first_busno, hose->last_busno);
 488
 489         return(hose->last_busno + 1);
 490 }
 491
 492 /* Enable inbound PCI config cycles for agent/endpoint interface */
 493 void fsl_pci_config_unlock(struct pci_controller *hose)
 494 {
 495         pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
 496         u8 agent;
 497         u8 pcie_cap;
 498         u16 pbfr;
 499
 500         pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
 501         if (!agent)
 502                 return;
 503
 504         pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
 505         if (pcie_cap != 0x0) {
 506                 /* PCIe - set CFG_READY bit of Configuration Ready Register */
 507                 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
 508         } else {
 509                 /* PCI - clear ACL bit of PBFR */
 510                 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
 511                 pbfr &= ~0x20;
 512                 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
 513         }
 514 }
 515
 516 #ifdef CONFIG_OF_BOARD_SETUP
 517 #include <libfdt.h>
 518 #include <fdt_support.h>
 519
 520 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
 521                         struct pci_controller *hose, unsigned long ctrl_addr)
 522 {
 523         int off;
 524         u32 bus_range[2];
 525         phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
 526
 527         /* convert ctrl_addr to true physical address */
 528         p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
 529         p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
 530
 531         off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
 532
 533         if (off < 0)
 534                 return;
 535
 536         /* We assume a cfg_addr not being set means we didn't setup the controller */
 537         if ((hose == NULL) || (hose->cfg_addr == NULL)) {
 538                 fdt_del_node(blob, off);
 539         } else {
 540                 bus_range[0] = 0;
 541                 bus_range[1] = hose->last_busno - hose->first_busno;
 542                 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
 543                 fdt_pci_dma_ranges(blob, off, hose);
 544         }
 545 }
 546 #endif