2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
17 #include <dm/device-internal.h>
18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
19 #include <asm/fsp/fsp_support.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR
;
25 int pci_get_bus(int busnum
, struct udevice
**busp
)
29 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret
= uclass_first_device_err(UCLASS_PCI
, busp
);
36 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
42 struct udevice
*pci_get_controller(struct udevice
*dev
)
44 while (device_is_on_pci_bus(dev
))
50 pci_dev_t
dm_pci_get_bdf(struct udevice
*dev
)
52 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
53 struct udevice
*bus
= dev
->parent
;
55 return PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
59 * pci_get_bus_max() - returns the bus number of the last active bus
61 * @return last bus number, or -1 if no active buses
63 static int pci_get_bus_max(void)
69 ret
= uclass_get(UCLASS_PCI
, &uc
);
70 uclass_foreach_dev(bus
, uc
) {
75 debug("%s: ret=%d\n", __func__
, ret
);
80 int pci_last_busno(void)
82 return pci_get_bus_max();
85 int pci_get_ff(enum pci_size_t size
)
97 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
98 struct udevice
**devp
)
102 for (device_find_first_child(bus
, &dev
);
104 device_find_next_child(&dev
)) {
105 struct pci_child_platdata
*pplat
;
107 pplat
= dev_get_parent_platdata(dev
);
108 if (pplat
&& pplat
->devfn
== find_devfn
) {
117 int dm_pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
122 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
125 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
128 static int pci_device_matches_ids(struct udevice
*dev
,
129 struct pci_device_id
*ids
)
131 struct pci_child_platdata
*pplat
;
134 pplat
= dev_get_parent_platdata(dev
);
137 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
138 if (pplat
->vendor
== ids
[i
].vendor
&&
139 pplat
->device
== ids
[i
].device
)
146 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
147 int *indexp
, struct udevice
**devp
)
151 /* Scan all devices on this bus */
152 for (device_find_first_child(bus
, &dev
);
154 device_find_next_child(&dev
)) {
155 if (pci_device_matches_ids(dev
, ids
) >= 0) {
156 if ((*indexp
)-- <= 0) {
166 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
167 struct udevice
**devp
)
171 /* Scan all known buses */
172 for (uclass_first_device(UCLASS_PCI
, &bus
);
174 uclass_next_device(&bus
)) {
175 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
183 static int dm_pci_bus_find_device(struct udevice
*bus
, unsigned int vendor
,
184 unsigned int device
, int *indexp
,
185 struct udevice
**devp
)
187 struct pci_child_platdata
*pplat
;
190 for (device_find_first_child(bus
, &dev
);
192 device_find_next_child(&dev
)) {
193 pplat
= dev_get_parent_platdata(dev
);
194 if (pplat
->vendor
== vendor
&& pplat
->device
== device
) {
205 int dm_pci_find_device(unsigned int vendor
, unsigned int device
, int index
,
206 struct udevice
**devp
)
210 /* Scan all known buses */
211 for (uclass_first_device(UCLASS_PCI
, &bus
);
213 uclass_next_device(&bus
)) {
214 if (!dm_pci_bus_find_device(bus
, vendor
, device
, &index
, devp
))
215 return device_probe(*devp
);
222 int dm_pci_find_class(uint find_class
, int index
, struct udevice
**devp
)
226 /* Scan all known buses */
227 for (pci_find_first_device(&dev
);
229 pci_find_next_device(&dev
)) {
230 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
232 if (pplat
->class == find_class
&& !index
--) {
234 return device_probe(*devp
);
242 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
243 unsigned long value
, enum pci_size_t size
)
245 struct dm_pci_ops
*ops
;
247 ops
= pci_get_ops(bus
);
248 if (!ops
->write_config
)
250 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
253 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
254 enum pci_size_t size
)
259 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
263 return pci_bus_write_config(bus
, bdf
, offset
, value
, size
);
266 int dm_pci_write_config(struct udevice
*dev
, int offset
, unsigned long value
,
267 enum pci_size_t size
)
271 for (bus
= dev
; device_is_on_pci_bus(bus
);)
273 return pci_bus_write_config(bus
, dm_pci_get_bdf(dev
), offset
, value
,
278 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
280 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
283 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
285 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
288 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
290 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
293 int dm_pci_write_config8(struct udevice
*dev
, int offset
, u8 value
)
295 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_8
);
298 int dm_pci_write_config16(struct udevice
*dev
, int offset
, u16 value
)
300 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_16
);
303 int dm_pci_write_config32(struct udevice
*dev
, int offset
, u32 value
)
305 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_32
);
308 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
309 unsigned long *valuep
, enum pci_size_t size
)
311 struct dm_pci_ops
*ops
;
313 ops
= pci_get_ops(bus
);
314 if (!ops
->read_config
)
316 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
319 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
320 enum pci_size_t size
)
325 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
329 return pci_bus_read_config(bus
, bdf
, offset
, valuep
, size
);
332 int dm_pci_read_config(struct udevice
*dev
, int offset
, unsigned long *valuep
,
333 enum pci_size_t size
)
337 for (bus
= dev
; device_is_on_pci_bus(bus
);)
339 return pci_bus_read_config(bus
, dm_pci_get_bdf(dev
), offset
, valuep
,
343 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
348 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
356 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
361 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
369 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
374 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
382 int dm_pci_read_config8(struct udevice
*dev
, int offset
, u8
*valuep
)
387 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_8
);
395 int dm_pci_read_config16(struct udevice
*dev
, int offset
, u16
*valuep
)
400 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_16
);
408 int dm_pci_read_config32(struct udevice
*dev
, int offset
, u32
*valuep
)
413 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_32
);
421 static void set_vga_bridge_bits(struct udevice
*dev
)
423 struct udevice
*parent
= dev
->parent
;
426 while (parent
->seq
!= 0) {
427 dm_pci_read_config16(parent
, PCI_BRIDGE_CONTROL
, &bc
);
428 bc
|= PCI_BRIDGE_CTL_VGA
;
429 dm_pci_write_config16(parent
, PCI_BRIDGE_CONTROL
, bc
);
430 parent
= parent
->parent
;
434 int pci_auto_config_devices(struct udevice
*bus
)
436 struct pci_controller
*hose
= bus
->uclass_priv
;
437 struct pci_child_platdata
*pplat
;
438 unsigned int sub_bus
;
443 debug("%s: start\n", __func__
);
444 pciauto_config_init(hose
);
445 for (ret
= device_find_first_child(bus
, &dev
);
447 ret
= device_find_next_child(&dev
)) {
448 unsigned int max_bus
;
451 debug("%s: device %s\n", __func__
, dev
->name
);
452 ret
= dm_pciauto_config_device(dev
);
456 sub_bus
= max(sub_bus
, max_bus
);
458 pplat
= dev_get_parent_platdata(dev
);
459 if (pplat
->class == (PCI_CLASS_DISPLAY_VGA
<< 8))
460 set_vga_bridge_bits(dev
);
462 debug("%s: done\n", __func__
);
467 int dm_pci_hose_probe_bus(struct udevice
*bus
)
472 debug("%s\n", __func__
);
474 sub_bus
= pci_get_bus_max() + 1;
475 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
476 dm_pciauto_prescan_setup_bridge(bus
, sub_bus
);
478 ret
= device_probe(bus
);
480 debug("%s: Cannot probe bus %s: %d\n", __func__
, bus
->name
,
484 if (sub_bus
!= bus
->seq
) {
485 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
486 __func__
, bus
->name
, bus
->seq
, sub_bus
);
489 sub_bus
= pci_get_bus_max();
490 dm_pciauto_postscan_setup_bridge(bus
, sub_bus
);
496 * pci_match_one_device - Tell if a PCI device structure has a matching
497 * PCI device id structure
498 * @id: single PCI device id structure to match
499 * @dev: the PCI device structure to match against
501 * Returns the matching pci_device_id structure or %NULL if there is no match.
503 static bool pci_match_one_id(const struct pci_device_id
*id
,
504 const struct pci_device_id
*find
)
506 if ((id
->vendor
== PCI_ANY_ID
|| id
->vendor
== find
->vendor
) &&
507 (id
->device
== PCI_ANY_ID
|| id
->device
== find
->device
) &&
508 (id
->subvendor
== PCI_ANY_ID
|| id
->subvendor
== find
->subvendor
) &&
509 (id
->subdevice
== PCI_ANY_ID
|| id
->subdevice
== find
->subdevice
) &&
510 !((id
->class ^ find
->class) & id
->class_mask
))
517 * pci_find_and_bind_driver() - Find and bind the right PCI driver
519 * This only looks at certain fields in the descriptor.
521 * @parent: Parent bus
522 * @find_id: Specification of the driver to find
523 * @bdf: Bus/device/function addreess - see PCI_BDF()
524 * @devp: Returns a pointer to the device created
525 * @return 0 if OK, -EPERM if the device is not needed before relocation and
526 * therefore was not created, other -ve value on error
528 static int pci_find_and_bind_driver(struct udevice
*parent
,
529 struct pci_device_id
*find_id
,
530 pci_dev_t bdf
, struct udevice
**devp
)
532 struct pci_driver_entry
*start
, *entry
;
541 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__
,
542 find_id
->vendor
, find_id
->device
);
543 start
= ll_entry_start(struct pci_driver_entry
, pci_driver_entry
);
544 n_ents
= ll_entry_count(struct pci_driver_entry
, pci_driver_entry
);
545 for (entry
= start
; entry
!= start
+ n_ents
; entry
++) {
546 const struct pci_device_id
*id
;
548 const struct driver
*drv
;
550 for (id
= entry
->match
;
551 id
->vendor
|| id
->subvendor
|| id
->class_mask
;
553 if (!pci_match_one_id(id
, find_id
))
559 * In the pre-relocation phase, we only bind devices
560 * whose driver has the DM_FLAG_PRE_RELOC set, to save
561 * precious memory space as on some platforms as that
562 * space is pretty limited (ie: using Cache As RAM).
564 if (!(gd
->flags
& GD_FLG_RELOC
) &&
565 !(drv
->flags
& DM_FLAG_PRE_RELOC
))
569 * We could pass the descriptor to the driver as
570 * platdata (instead of NULL) and allow its bind()
571 * method to return -ENOENT if it doesn't support this
572 * device. That way we could continue the search to
573 * find another driver. For now this doesn't seem
574 * necesssary, so just bind the first match.
576 ret
= device_bind(parent
, drv
, drv
->name
, NULL
, -1,
580 debug("%s: Match found: %s\n", __func__
, drv
->name
);
581 dev
->driver_data
= find_id
->driver_data
;
587 bridge
= (find_id
->class >> 8) == PCI_CLASS_BRIDGE_PCI
;
589 * In the pre-relocation phase, we only bind bridge devices to save
590 * precious memory space as on some platforms as that space is pretty
591 * limited (ie: using Cache As RAM).
593 if (!(gd
->flags
& GD_FLG_RELOC
) && !bridge
)
596 /* Bind a generic driver so that the device can be used */
597 sprintf(name
, "pci_%x:%x.%x", parent
->seq
, PCI_DEV(bdf
),
602 drv
= bridge
? "pci_bridge_drv" : "pci_generic_drv";
604 ret
= device_bind_driver(parent
, drv
, str
, devp
);
606 debug("%s: Failed to bind generic driver: %d\n", __func__
, ret
);
609 debug("%s: No match found: bound generic driver instead\n", __func__
);
614 debug("%s: No match found: error %d\n", __func__
, ret
);
618 int pci_bind_bus_devices(struct udevice
*bus
)
620 ulong vendor
, device
;
627 end
= PCI_BDF(bus
->seq
, PCI_MAX_PCI_DEVICES
- 1,
628 PCI_MAX_PCI_FUNCTIONS
- 1);
629 for (bdf
= PCI_BDF(bus
->seq
, 0, 0); bdf
< end
;
630 bdf
+= PCI_BDF(0, 0, 1)) {
631 struct pci_child_platdata
*pplat
;
635 if (PCI_FUNC(bdf
) && !found_multi
)
637 /* Check only the first access, we don't expect problems */
638 ret
= pci_bus_read_config(bus
, bdf
, PCI_HEADER_TYPE
,
639 &header_type
, PCI_SIZE_8
);
642 pci_bus_read_config(bus
, bdf
, PCI_VENDOR_ID
, &vendor
,
644 if (vendor
== 0xffff || vendor
== 0x0000)
648 found_multi
= header_type
& 0x80;
650 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
651 bus
->seq
, bus
->name
, PCI_DEV(bdf
), PCI_FUNC(bdf
));
652 pci_bus_read_config(bus
, bdf
, PCI_DEVICE_ID
, &device
,
654 pci_bus_read_config(bus
, bdf
, PCI_CLASS_REVISION
, &class,
658 /* Find this device in the device tree */
659 ret
= pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), &dev
);
661 /* If nothing in the device tree, bind a device */
662 if (ret
== -ENODEV
) {
663 struct pci_device_id find_id
;
666 memset(&find_id
, '\0', sizeof(find_id
));
667 find_id
.vendor
= vendor
;
668 find_id
.device
= device
;
669 find_id
.class = class;
670 if ((header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
) {
671 pci_bus_read_config(bus
, bdf
,
672 PCI_SUBSYSTEM_VENDOR_ID
,
674 find_id
.subvendor
= val
& 0xffff;
675 find_id
.subdevice
= val
>> 16;
677 ret
= pci_find_and_bind_driver(bus
, &find_id
, bdf
,
685 /* Update the platform data */
686 pplat
= dev_get_parent_platdata(dev
);
687 pplat
->devfn
= PCI_MASK_BUS(bdf
);
688 pplat
->vendor
= vendor
;
689 pplat
->device
= device
;
690 pplat
->class = class;
695 printf("Cannot read bus configuration: %d\n", ret
);
700 static int pci_uclass_post_bind(struct udevice
*bus
)
703 * If there is no pci device listed in the device tree,
704 * don't bother scanning the device tree.
706 if (bus
->of_offset
== -1)
710 * Scan the device tree for devices. This does not probe the PCI bus,
711 * as this is not permitted while binding. It just finds devices
712 * mentioned in the device tree.
714 * Before relocation, only bind devices marked for pre-relocation
717 return dm_scan_fdt_node(bus
, gd
->fdt_blob
, bus
->of_offset
,
718 gd
->flags
& GD_FLG_RELOC
? false : true);
721 static int decode_regions(struct pci_controller
*hose
, const void *blob
,
722 int parent_node
, int node
)
724 int pci_addr_cells
, addr_cells
, size_cells
;
725 phys_addr_t base
= 0, size
;
726 int cells_per_record
;
731 prop
= fdt_getprop(blob
, node
, "ranges", &len
);
734 pci_addr_cells
= fdt_address_cells(blob
, node
);
735 addr_cells
= fdt_address_cells(blob
, parent_node
);
736 size_cells
= fdt_size_cells(blob
, node
);
738 /* PCI addresses are always 3-cells */
740 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
741 hose
->region_count
= 0;
742 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
744 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
745 u64 pci_addr
, addr
, size
;
751 if (len
< cells_per_record
)
753 flags
= fdt32_to_cpu(prop
[0]);
754 space_code
= (flags
>> 24) & 3;
755 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
756 prop
+= pci_addr_cells
;
757 addr
= fdtdec_get_number(prop
, addr_cells
);
759 size
= fdtdec_get_number(prop
, size_cells
);
761 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
762 ", size=%" PRIx64
", space_code=%d\n", __func__
,
763 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
764 if (space_code
& 2) {
765 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
767 } else if (space_code
& 1) {
768 type
= PCI_REGION_IO
;
773 for (i
= 0; i
< hose
->region_count
; i
++) {
774 if (hose
->regions
[i
].flags
== type
)
778 pos
= hose
->region_count
++;
779 debug(" - type=%d, pos=%d\n", type
, pos
);
780 pci_set_region(hose
->regions
+ pos
, pci_addr
, addr
, size
, type
);
783 /* Add a region for our local memory */
785 #ifdef CONFIG_SYS_SDRAM_BASE
786 base
= CONFIG_SYS_SDRAM_BASE
;
788 if (gd
->pci_ram_top
&& gd
->pci_ram_top
< base
+ size
)
789 size
= gd
->pci_ram_top
- base
;
790 pci_set_region(hose
->regions
+ hose
->region_count
++, base
, base
,
791 size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
796 static int pci_uclass_pre_probe(struct udevice
*bus
)
798 struct pci_controller
*hose
;
801 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
803 hose
= bus
->uclass_priv
;
805 /* For bridges, use the top-level PCI controller */
806 if (device_get_uclass_id(bus
->parent
) == UCLASS_ROOT
) {
808 ret
= decode_regions(hose
, gd
->fdt_blob
, bus
->parent
->of_offset
,
811 debug("%s: Cannot decode regions\n", __func__
);
815 struct pci_controller
*parent_hose
;
817 parent_hose
= dev_get_uclass_priv(bus
->parent
);
818 hose
->ctlr
= parent_hose
->bus
;
821 hose
->first_busno
= bus
->seq
;
822 hose
->last_busno
= bus
->seq
;
827 static int pci_uclass_post_probe(struct udevice
*bus
)
831 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
832 ret
= pci_bind_bus_devices(bus
);
836 #ifdef CONFIG_PCI_PNP
837 ret
= pci_auto_config_devices(bus
);
842 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
844 * Per Intel FSP specification, we should call FSP notify API to
845 * inform FSP that PCI enumeration has been done so that FSP will
846 * do any necessary initialization as required by the chipset's
847 * BIOS Writer's Guide (BWG).
849 * Unfortunately we have to put this call here as with driver model,
850 * the enumeration is all done on a lazy basis as needed, so until
851 * something is touched on PCI it won't happen.
853 * Note we only call this 1) after U-Boot is relocated, and 2)
854 * root bus has finished probing.
856 if ((gd
->flags
& GD_FLG_RELOC
) && (bus
->seq
== 0)) {
857 ret
= fsp_init_phase_pci();
866 static int pci_uclass_child_post_bind(struct udevice
*dev
)
868 struct pci_child_platdata
*pplat
;
869 struct fdt_pci_addr addr
;
872 if (dev
->of_offset
== -1)
876 * We could read vendor, device, class if available. But for now we
877 * just check the address.
879 pplat
= dev_get_parent_platdata(dev
);
880 ret
= fdtdec_get_pci_addr(gd
->fdt_blob
, dev
->of_offset
,
881 FDT_PCI_SPACE_CONFIG
, "reg", &addr
);
887 /* extract the devfn from fdt_pci_addr */
888 pplat
->devfn
= addr
.phys_hi
& 0xff00;
894 static int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t bdf
,
895 uint offset
, ulong
*valuep
,
896 enum pci_size_t size
)
898 struct pci_controller
*hose
= bus
->uclass_priv
;
900 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
903 static int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t bdf
,
904 uint offset
, ulong value
,
905 enum pci_size_t size
)
907 struct pci_controller
*hose
= bus
->uclass_priv
;
909 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
912 static int skip_to_next_device(struct udevice
*bus
, struct udevice
**devp
)
918 * Scan through all the PCI controllers. On x86 there will only be one
919 * but that is not necessarily true on other hardware.
922 device_find_first_child(bus
, &dev
);
927 ret
= uclass_next_device(&bus
);
935 int pci_find_next_device(struct udevice
**devp
)
937 struct udevice
*child
= *devp
;
938 struct udevice
*bus
= child
->parent
;
941 /* First try all the siblings */
944 device_find_next_child(&child
);
951 /* We ran out of siblings. Try the next bus */
952 ret
= uclass_next_device(&bus
);
956 return bus
? skip_to_next_device(bus
, devp
) : 0;
959 int pci_find_first_device(struct udevice
**devp
)
965 ret
= uclass_first_device(UCLASS_PCI
, &bus
);
969 return skip_to_next_device(bus
, devp
);
972 ulong
pci_conv_32_to_size(ulong value
, uint offset
, enum pci_size_t size
)
976 return (value
>> ((offset
& 3) * 8)) & 0xff;
978 return (value
>> ((offset
& 2) * 8)) & 0xffff;
984 ulong
pci_conv_size_to_32(ulong old
, ulong value
, uint offset
,
985 enum pci_size_t size
)
988 uint val_mask
, shift
;
1003 shift
= (offset
& off_mask
) * 8;
1004 ldata
= (value
& val_mask
) << shift
;
1005 mask
= val_mask
<< shift
;
1006 value
= (old
& ~mask
) | ldata
;
1011 int pci_get_regions(struct udevice
*dev
, struct pci_region
**iop
,
1012 struct pci_region
**memp
, struct pci_region
**prefp
)
1014 struct udevice
*bus
= pci_get_controller(dev
);
1015 struct pci_controller
*hose
= dev_get_uclass_priv(bus
);
1021 for (i
= 0; i
< hose
->region_count
; i
++) {
1022 switch (hose
->regions
[i
].flags
) {
1024 if (!*iop
|| (*iop
)->size
< hose
->regions
[i
].size
)
1025 *iop
= hose
->regions
+ i
;
1027 case PCI_REGION_MEM
:
1028 if (!*memp
|| (*memp
)->size
< hose
->regions
[i
].size
)
1029 *memp
= hose
->regions
+ i
;
1031 case (PCI_REGION_MEM
| PCI_REGION_PREFETCH
):
1032 if (!*prefp
|| (*prefp
)->size
< hose
->regions
[i
].size
)
1033 *prefp
= hose
->regions
+ i
;
1038 return (*iop
!= NULL
) + (*memp
!= NULL
) + (*prefp
!= NULL
);
1041 u32
dm_pci_read_bar32(struct udevice
*dev
, int barnum
)
1046 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1047 dm_pci_read_config32(dev
, bar
, &addr
);
1048 if (addr
& PCI_BASE_ADDRESS_SPACE_IO
)
1049 return addr
& PCI_BASE_ADDRESS_IO_MASK
;
1051 return addr
& PCI_BASE_ADDRESS_MEM_MASK
;
1054 void dm_pci_write_bar32(struct udevice
*dev
, int barnum
, u32 addr
)
1058 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1059 dm_pci_write_config32(dev
, bar
, addr
);
1062 static int _dm_pci_bus_to_phys(struct udevice
*ctlr
,
1063 pci_addr_t bus_addr
, unsigned long flags
,
1064 unsigned long skip_mask
, phys_addr_t
*pa
)
1066 struct pci_controller
*hose
= dev_get_uclass_priv(ctlr
);
1067 struct pci_region
*res
;
1070 for (i
= 0; i
< hose
->region_count
; i
++) {
1071 res
= &hose
->regions
[i
];
1073 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1076 if (res
->flags
& skip_mask
)
1079 if (bus_addr
>= res
->bus_start
&&
1080 (bus_addr
- res
->bus_start
) < res
->size
) {
1081 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
1089 phys_addr_t
dm_pci_bus_to_phys(struct udevice
*dev
, pci_addr_t bus_addr
,
1090 unsigned long flags
)
1092 phys_addr_t phys_addr
= 0;
1093 struct udevice
*ctlr
;
1096 /* The root controller has the region information */
1097 ctlr
= pci_get_controller(dev
);
1100 * if PCI_REGION_MEM is set we do a two pass search with preference
1101 * on matches that don't have PCI_REGION_SYS_MEMORY set
1103 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1104 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
,
1105 flags
, PCI_REGION_SYS_MEMORY
,
1111 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
, flags
, 0, &phys_addr
);
1114 puts("pci_hose_bus_to_phys: invalid physical address\n");
1119 int _dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1120 unsigned long flags
, unsigned long skip_mask
,
1123 struct pci_region
*res
;
1124 struct udevice
*ctlr
;
1125 pci_addr_t bus_addr
;
1127 struct pci_controller
*hose
;
1129 /* The root controller has the region information */
1130 ctlr
= pci_get_controller(dev
);
1131 hose
= dev_get_uclass_priv(ctlr
);
1133 for (i
= 0; i
< hose
->region_count
; i
++) {
1134 res
= &hose
->regions
[i
];
1136 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1139 if (res
->flags
& skip_mask
)
1142 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
1144 if (bus_addr
>= res
->bus_start
&&
1145 (bus_addr
- res
->bus_start
) < res
->size
) {
1154 pci_addr_t
dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1155 unsigned long flags
)
1157 pci_addr_t bus_addr
= 0;
1161 * if PCI_REGION_MEM is set we do a two pass search with preference
1162 * on matches that don't have PCI_REGION_SYS_MEMORY set
1164 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1165 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
,
1166 PCI_REGION_SYS_MEMORY
, &bus_addr
);
1171 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
, 0, &bus_addr
);
1174 puts("pci_hose_phys_to_bus: invalid physical address\n");
1179 void *dm_pci_map_bar(struct udevice
*dev
, int bar
, int flags
)
1181 pci_addr_t pci_bus_addr
;
1184 /* read BAR address */
1185 dm_pci_read_config32(dev
, bar
, &bar_response
);
1186 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
1189 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1190 * isn't actualy used on any platform because u-boot assumes a static
1191 * linear mapping. In the future, this could read the BAR size
1192 * and pass that as the size if needed.
1194 return dm_pci_bus_to_virt(dev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
1197 UCLASS_DRIVER(pci
) = {
1200 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
1201 .post_bind
= pci_uclass_post_bind
,
1202 .pre_probe
= pci_uclass_pre_probe
,
1203 .post_probe
= pci_uclass_post_probe
,
1204 .child_post_bind
= pci_uclass_child_post_bind
,
1205 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
1206 .per_child_platdata_auto_alloc_size
=
1207 sizeof(struct pci_child_platdata
),
1210 static const struct dm_pci_ops pci_bridge_ops
= {
1211 .read_config
= pci_bridge_read_config
,
1212 .write_config
= pci_bridge_write_config
,
1215 static const struct udevice_id pci_bridge_ids
[] = {
1216 { .compatible
= "pci-bridge" },
1220 U_BOOT_DRIVER(pci_bridge_drv
) = {
1221 .name
= "pci_bridge_drv",
1223 .of_match
= pci_bridge_ids
,
1224 .ops
= &pci_bridge_ops
,
1227 UCLASS_DRIVER(pci_generic
) = {
1228 .id
= UCLASS_PCI_GENERIC
,
1229 .name
= "pci_generic",
1232 static const struct udevice_id pci_generic_ids
[] = {
1233 { .compatible
= "pci-generic" },
1237 U_BOOT_DRIVER(pci_generic_drv
) = {
1238 .name
= "pci_generic_drv",
1239 .id
= UCLASS_PCI_GENERIC
,
1240 .of_match
= pci_generic_ids
,
1245 struct udevice
*bus
;
1248 * Enumerate all known controller devices. Enumeration has the side-
1249 * effect of probing them, so PCIe devices will be enumerated too.
1251 for (uclass_first_device(UCLASS_PCI
, &bus
);
1253 uclass_next_device(&bus
)) {