drivers/pci/pci-uclass.c

   1 /*
   2  * Copyright (c) 2014 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <inttypes.h>
  13 #include <pci.h>
  14 #include <asm/io.h>
  15 #include <dm/lists.h>
  16 #include <dm/root.h>
  17 #include <dm/device-internal.h>
  18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  19 #include <asm/fsp/fsp_support.h>
  20 #endif
  21 #include "pci_internal.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int pci_get_bus(int busnum, struct udevice **busp)
  26 {
  27         int ret;
  28
  29         ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  30
  31         /* Since buses may not be numbered yet try a little harder with bus 0 */
  32         if (ret == -ENODEV) {
  33                 ret = uclass_first_device_err(UCLASS_PCI, busp);
  34                 if (ret)
  35                         return ret;
  36                 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  37         }
  38
  39         return ret;
  40 }
  41
  42 struct udevice *pci_get_controller(struct udevice *dev)
  43 {
  44         while (device_is_on_pci_bus(dev))
  45                 dev = dev->parent;
  46
  47         return dev;
  48 }
  49
  50 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
  51 {
  52         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  53         struct udevice *bus = dev->parent;
  54
  55         return PCI_ADD_BUS(bus->seq, pplat->devfn);
  56 }
  57
  58 /**
  59  * pci_get_bus_max() - returns the bus number of the last active bus
  60  *
  61  * @return last bus number, or -1 if no active buses
  62  */
  63 static int pci_get_bus_max(void)
  64 {
  65         struct udevice *bus;
  66         struct uclass *uc;
  67         int ret = -1;
  68
  69         ret = uclass_get(UCLASS_PCI, &uc);
  70         uclass_foreach_dev(bus, uc) {
  71                 if (bus->seq > ret)
  72                         ret = bus->seq;
  73         }
  74
  75         debug("%s: ret=%d\n", __func__, ret);
  76
  77         return ret;
  78 }
  79
  80 int pci_last_busno(void)
  81 {
  82         return pci_get_bus_max();
  83 }
  84
  85 int pci_get_ff(enum pci_size_t size)
  86 {
  87         switch (size) {
  88         case PCI_SIZE_8:
  89                 return 0xff;
  90         case PCI_SIZE_16:
  91                 return 0xffff;
  92         default:
  93                 return 0xffffffff;
  94         }
  95 }
  96
  97 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
  98                        struct udevice **devp)
  99 {
 100         struct udevice *dev;
 101
 102         for (device_find_first_child(bus, &dev);
 103              dev;
 104              device_find_next_child(&dev)) {
 105                 struct pci_child_platdata *pplat;
 106
 107                 pplat = dev_get_parent_platdata(dev);
 108                 if (pplat && pplat->devfn == find_devfn) {
 109                         *devp = dev;
 110                         return 0;
 111                 }
 112         }
 113
 114         return -ENODEV;
 115 }
 116
 117 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
 118 {
 119         struct udevice *bus;
 120         int ret;
 121
 122         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 123         if (ret)
 124                 return ret;
 125         return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
 126 }
 127
 128 static int pci_device_matches_ids(struct udevice *dev,
 129                                   struct pci_device_id *ids)
 130 {
 131         struct pci_child_platdata *pplat;
 132         int i;
 133
 134         pplat = dev_get_parent_platdata(dev);
 135         if (!pplat)
 136                 return -EINVAL;
 137         for (i = 0; ids[i].vendor != 0; i++) {
 138                 if (pplat->vendor == ids[i].vendor &&
 139                     pplat->device == ids[i].device)
 140                         return i;
 141         }
 142
 143         return -EINVAL;
 144 }
 145
 146 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
 147                          int *indexp, struct udevice **devp)
 148 {
 149         struct udevice *dev;
 150
 151         /* Scan all devices on this bus */
 152         for (device_find_first_child(bus, &dev);
 153              dev;
 154              device_find_next_child(&dev)) {
 155                 if (pci_device_matches_ids(dev, ids) >= 0) {
 156                         if ((*indexp)-- <= 0) {
 157                                 *devp = dev;
 158                                 return 0;
 159                         }
 160                 }
 161         }
 162
 163         return -ENODEV;
 164 }
 165
 166 int pci_find_device_id(struct pci_device_id *ids, int index,
 167                        struct udevice **devp)
 168 {
 169         struct udevice *bus;
 170
 171         /* Scan all known buses */
 172         for (uclass_first_device(UCLASS_PCI, &bus);
 173              bus;
 174              uclass_next_device(&bus)) {
 175                 if (!pci_bus_find_devices(bus, ids, &index, devp))
 176                         return 0;
 177         }
 178         *devp = NULL;
 179
 180         return -ENODEV;
 181 }
 182
 183 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
 184                                   unsigned int device, int *indexp,
 185                                   struct udevice **devp)
 186 {
 187         struct pci_child_platdata *pplat;
 188         struct udevice *dev;
 189
 190         for (device_find_first_child(bus, &dev);
 191              dev;
 192              device_find_next_child(&dev)) {
 193                 pplat = dev_get_parent_platdata(dev);
 194                 if (pplat->vendor == vendor && pplat->device == device) {
 195                         if (!(*indexp)--) {
 196                                 *devp = dev;
 197                                 return 0;
 198                         }
 199                 }
 200         }
 201
 202         return -ENODEV;
 203 }
 204
 205 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
 206                        struct udevice **devp)
 207 {
 208         struct udevice *bus;
 209
 210         /* Scan all known buses */
 211         for (uclass_first_device(UCLASS_PCI, &bus);
 212              bus;
 213              uclass_next_device(&bus)) {
 214                 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
 215                         return device_probe(*devp);
 216         }
 217         *devp = NULL;
 218
 219         return -ENODEV;
 220 }
 221
 222 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
 223 {
 224         struct udevice *dev;
 225
 226         /* Scan all known buses */
 227         for (pci_find_first_device(&dev);
 228              dev;
 229              pci_find_next_device(&dev)) {
 230                 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 231
 232                 if (pplat->class == find_class && !index--) {
 233                         *devp = dev;
 234                         return device_probe(*devp);
 235                 }
 236         }
 237         *devp = NULL;
 238
 239         return -ENODEV;
 240 }
 241
 242 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
 243                          unsigned long value, enum pci_size_t size)
 244 {
 245         struct dm_pci_ops *ops;
 246
 247         ops = pci_get_ops(bus);
 248         if (!ops->write_config)
 249                 return -ENOSYS;
 250         return ops->write_config(bus, bdf, offset, value, size);
 251 }
 252
 253 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
 254                             u32 clr, u32 set)
 255 {
 256         ulong val;
 257         int ret;
 258
 259         ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
 260         if (ret)
 261                 return ret;
 262         val &= ~clr;
 263         val |= set;
 264
 265         return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
 266 }
 267
 268 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
 269                      enum pci_size_t size)
 270 {
 271         struct udevice *bus;
 272         int ret;
 273
 274         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 275         if (ret)
 276                 return ret;
 277
 278         return pci_bus_write_config(bus, bdf, offset, value, size);
 279 }
 280
 281 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
 282                         enum pci_size_t size)
 283 {
 284         struct udevice *bus;
 285
 286         for (bus = dev; device_is_on_pci_bus(bus);)
 287                 bus = bus->parent;
 288         return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
 289                                     size);
 290 }
 291
 292 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
 293 {
 294         return pci_write_config(bdf, offset, value, PCI_SIZE_32);
 295 }
 296
 297 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
 298 {
 299         return pci_write_config(bdf, offset, value, PCI_SIZE_16);
 300 }
 301
 302 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
 303 {
 304         return pci_write_config(bdf, offset, value, PCI_SIZE_8);
 305 }
 306
 307 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
 308 {
 309         return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
 310 }
 311
 312 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
 313 {
 314         return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
 315 }
 316
 317 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
 318 {
 319         return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
 320 }
 321
 322 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
 323                         unsigned long *valuep, enum pci_size_t size)
 324 {
 325         struct dm_pci_ops *ops;
 326
 327         ops = pci_get_ops(bus);
 328         if (!ops->read_config)
 329                 return -ENOSYS;
 330         return ops->read_config(bus, bdf, offset, valuep, size);
 331 }
 332
 333 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
 334                     enum pci_size_t size)
 335 {
 336         struct udevice *bus;
 337         int ret;
 338
 339         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 340         if (ret)
 341                 return ret;
 342
 343         return pci_bus_read_config(bus, bdf, offset, valuep, size);
 344 }
 345
 346 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
 347                        enum pci_size_t size)
 348 {
 349         struct udevice *bus;
 350
 351         for (bus = dev; device_is_on_pci_bus(bus);)
 352                 bus = bus->parent;
 353         return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
 354                                    size);
 355 }
 356
 357 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
 358 {
 359         unsigned long value;
 360         int ret;
 361
 362         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
 363         if (ret)
 364                 return ret;
 365         *valuep = value;
 366
 367         return 0;
 368 }
 369
 370 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
 371 {
 372         unsigned long value;
 373         int ret;
 374
 375         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
 376         if (ret)
 377                 return ret;
 378         *valuep = value;
 379
 380         return 0;
 381 }
 382
 383 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
 384 {
 385         unsigned long value;
 386         int ret;
 387
 388         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
 389         if (ret)
 390                 return ret;
 391         *valuep = value;
 392
 393         return 0;
 394 }
 395
 396 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
 397 {
 398         unsigned long value;
 399         int ret;
 400
 401         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
 402         if (ret)
 403                 return ret;
 404         *valuep = value;
 405
 406         return 0;
 407 }
 408
 409 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
 410 {
 411         unsigned long value;
 412         int ret;
 413
 414         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
 415         if (ret)
 416                 return ret;
 417         *valuep = value;
 418
 419         return 0;
 420 }
 421
 422 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
 423 {
 424         unsigned long value;
 425         int ret;
 426
 427         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
 428         if (ret)
 429                 return ret;
 430         *valuep = value;
 431
 432         return 0;
 433 }
 434
 435 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
 436 {
 437         u8 val;
 438         int ret;
 439
 440         ret = dm_pci_read_config8(dev, offset, &val);
 441         if (ret)
 442                 return ret;
 443         val &= ~clr;
 444         val |= set;
 445
 446         return dm_pci_write_config8(dev, offset, val);
 447 }
 448
 449 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
 450 {
 451         u16 val;
 452         int ret;
 453
 454         ret = dm_pci_read_config16(dev, offset, &val);
 455         if (ret)
 456                 return ret;
 457         val &= ~clr;
 458         val |= set;
 459
 460         return dm_pci_write_config16(dev, offset, val);
 461 }
 462
 463 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
 464 {
 465         u32 val;
 466         int ret;
 467
 468         ret = dm_pci_read_config32(dev, offset, &val);
 469         if (ret)
 470                 return ret;
 471         val &= ~clr;
 472         val |= set;
 473
 474         return dm_pci_write_config32(dev, offset, val);
 475 }
 476
 477 static void set_vga_bridge_bits(struct udevice *dev)
 478 {
 479         struct udevice *parent = dev->parent;
 480         u16 bc;
 481
 482         while (parent->seq != 0) {
 483                 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
 484                 bc |= PCI_BRIDGE_CTL_VGA;
 485                 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
 486                 parent = parent->parent;
 487         }
 488 }
 489
 490 int pci_auto_config_devices(struct udevice *bus)
 491 {
 492         struct pci_controller *hose = bus->uclass_priv;
 493         struct pci_child_platdata *pplat;
 494         unsigned int sub_bus;
 495         struct udevice *dev;
 496         int ret;
 497
 498         sub_bus = bus->seq;
 499         debug("%s: start\n", __func__);
 500         pciauto_config_init(hose);
 501         for (ret = device_find_first_child(bus, &dev);
 502              !ret && dev;
 503              ret = device_find_next_child(&dev)) {
 504                 unsigned int max_bus;
 505                 int ret;
 506
 507                 debug("%s: device %s\n", __func__, dev->name);
 508                 ret = dm_pciauto_config_device(dev);
 509                 if (ret < 0)
 510                         return ret;
 511                 max_bus = ret;
 512                 sub_bus = max(sub_bus, max_bus);
 513
 514                 pplat = dev_get_parent_platdata(dev);
 515                 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
 516                         set_vga_bridge_bits(dev);
 517         }
 518         debug("%s: done\n", __func__);
 519
 520         return sub_bus;
 521 }
 522
 523 int dm_pci_hose_probe_bus(struct udevice *bus)
 524 {
 525         int sub_bus;
 526         int ret;
 527
 528         debug("%s\n", __func__);
 529
 530         sub_bus = pci_get_bus_max() + 1;
 531         debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
 532         dm_pciauto_prescan_setup_bridge(bus, sub_bus);
 533
 534         ret = device_probe(bus);
 535         if (ret) {
 536                 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
 537                       ret);
 538                 return ret;
 539         }
 540         if (sub_bus != bus->seq) {
 541                 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
 542                        __func__, bus->name, bus->seq, sub_bus);
 543                 return -EPIPE;
 544         }
 545         sub_bus = pci_get_bus_max();
 546         dm_pciauto_postscan_setup_bridge(bus, sub_bus);
 547
 548         return sub_bus;
 549 }
 550
 551 /**
 552  * pci_match_one_device - Tell if a PCI device structure has a matching
 553  *                        PCI device id structure
 554  * @id: single PCI device id structure to match
 555  * @dev: the PCI device structure to match against
 556  *
 557  * Returns the matching pci_device_id structure or %NULL if there is no match.
 558  */
 559 static bool pci_match_one_id(const struct pci_device_id *id,
 560                              const struct pci_device_id *find)
 561 {
 562         if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
 563             (id->device == PCI_ANY_ID || id->device == find->device) &&
 564             (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
 565             (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
 566             !((id->class ^ find->class) & id->class_mask))
 567                 return true;
 568
 569         return false;
 570 }
 571
 572 /**
 573  * pci_find_and_bind_driver() - Find and bind the right PCI driver
 574  *
 575  * This only looks at certain fields in the descriptor.
 576  *
 577  * @parent:     Parent bus
 578  * @find_id:    Specification of the driver to find
 579  * @bdf:        Bus/device/function addreess - see PCI_BDF()
 580  * @devp:       Returns a pointer to the device created
 581  * @return 0 if OK, -EPERM if the device is not needed before relocation and
 582  *         therefore was not created, other -ve value on error
 583  */
 584 static int pci_find_and_bind_driver(struct udevice *parent,
 585                                     struct pci_device_id *find_id,
 586                                     pci_dev_t bdf, struct udevice **devp)
 587 {
 588         struct pci_driver_entry *start, *entry;
 589         const char *drv;
 590         int n_ents;
 591         int ret;
 592         char name[30], *str;
 593         bool bridge;
 594
 595         *devp = NULL;
 596
 597         debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
 598               find_id->vendor, find_id->device);
 599         start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
 600         n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
 601         for (entry = start; entry != start + n_ents; entry++) {
 602                 const struct pci_device_id *id;
 603                 struct udevice *dev;
 604                 const struct driver *drv;
 605
 606                 for (id = entry->match;
 607                      id->vendor || id->subvendor || id->class_mask;
 608                      id++) {
 609                         if (!pci_match_one_id(id, find_id))
 610                                 continue;
 611
 612                         drv = entry->driver;
 613
 614                         /*
 615                          * In the pre-relocation phase, we only bind devices
 616                          * whose driver has the DM_FLAG_PRE_RELOC set, to save
 617                          * precious memory space as on some platforms as that
 618                          * space is pretty limited (ie: using Cache As RAM).
 619                          */
 620                         if (!(gd->flags & GD_FLG_RELOC) &&
 621                             !(drv->flags & DM_FLAG_PRE_RELOC))
 622                                 return -EPERM;
 623
 624                         /*
 625                          * We could pass the descriptor to the driver as
 626                          * platdata (instead of NULL) and allow its bind()
 627                          * method to return -ENOENT if it doesn't support this
 628                          * device. That way we could continue the search to
 629                          * find another driver. For now this doesn't seem
 630                          * necesssary, so just bind the first match.
 631                          */
 632                         ret = device_bind(parent, drv, drv->name, NULL, -1,
 633                                           &dev);
 634                         if (ret)
 635                                 goto error;
 636                         debug("%s: Match found: %s\n", __func__, drv->name);
 637                         dev->driver_data = find_id->driver_data;
 638                         *devp = dev;
 639                         return 0;
 640                 }
 641         }
 642
 643         bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
 644         /*
 645          * In the pre-relocation phase, we only bind bridge devices to save
 646          * precious memory space as on some platforms as that space is pretty
 647          * limited (ie: using Cache As RAM).
 648          */
 649         if (!(gd->flags & GD_FLG_RELOC) && !bridge)
 650                 return -EPERM;
 651
 652         /* Bind a generic driver so that the device can be used */
 653         sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
 654                 PCI_FUNC(bdf));
 655         str = strdup(name);
 656         if (!str)
 657                 return -ENOMEM;
 658         drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
 659
 660         ret = device_bind_driver(parent, drv, str, devp);
 661         if (ret) {
 662                 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
 663                 return ret;
 664         }
 665         debug("%s: No match found: bound generic driver instead\n", __func__);
 666
 667         return 0;
 668
 669 error:
 670         debug("%s: No match found: error %d\n", __func__, ret);
 671         return ret;
 672 }
 673
 674 int pci_bind_bus_devices(struct udevice *bus)
 675 {
 676         ulong vendor, device;
 677         ulong header_type;
 678         pci_dev_t bdf, end;
 679         bool found_multi;
 680         int ret;
 681
 682         found_multi = false;
 683         end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
 684                       PCI_MAX_PCI_FUNCTIONS - 1);
 685         for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
 686              bdf += PCI_BDF(0, 0, 1)) {
 687                 struct pci_child_platdata *pplat;
 688                 struct udevice *dev;
 689                 ulong class;
 690
 691                 if (PCI_FUNC(bdf) && !found_multi)
 692                         continue;
 693                 /* Check only the first access, we don't expect problems */
 694                 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
 695                                           &header_type, PCI_SIZE_8);
 696                 if (ret)
 697                         goto error;
 698                 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
 699                                     PCI_SIZE_16);
 700                 if (vendor == 0xffff || vendor == 0x0000)
 701                         continue;
 702
 703                 if (!PCI_FUNC(bdf))
 704                         found_multi = header_type & 0x80;
 705
 706                 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
 707                       bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
 708                 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
 709                                     PCI_SIZE_16);
 710                 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
 711                                     PCI_SIZE_32);
 712                 class >>= 8;
 713
 714                 /* Find this device in the device tree */
 715                 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
 716
 717                 /* If nothing in the device tree, bind a device */
 718                 if (ret == -ENODEV) {
 719                         struct pci_device_id find_id;
 720                         ulong val;
 721
 722                         memset(&find_id, '\0', sizeof(find_id));
 723                         find_id.vendor = vendor;
 724                         find_id.device = device;
 725                         find_id.class = class;
 726                         if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
 727                                 pci_bus_read_config(bus, bdf,
 728                                                     PCI_SUBSYSTEM_VENDOR_ID,
 729                                                     &val, PCI_SIZE_32);
 730                                 find_id.subvendor = val & 0xffff;
 731                                 find_id.subdevice = val >> 16;
 732                         }
 733                         ret = pci_find_and_bind_driver(bus, &find_id, bdf,
 734                                                        &dev);
 735                 }
 736                 if (ret == -EPERM)
 737                         continue;
 738                 else if (ret)
 739                         return ret;
 740
 741                 /* Update the platform data */
 742                 pplat = dev_get_parent_platdata(dev);
 743                 pplat->devfn = PCI_MASK_BUS(bdf);
 744                 pplat->vendor = vendor;
 745                 pplat->device = device;
 746                 pplat->class = class;
 747         }
 748
 749         return 0;
 750 error:
 751         printf("Cannot read bus configuration: %d\n", ret);
 752
 753         return ret;
 754 }
 755
 756 static int pci_uclass_post_bind(struct udevice *bus)
 757 {
 758         /*
 759          * If there is no pci device listed in the device tree,
 760          * don't bother scanning the device tree.
 761          */
 762         if (bus->of_offset == -1)
 763                 return 0;
 764
 765         /*
 766          * Scan the device tree for devices. This does not probe the PCI bus,
 767          * as this is not permitted while binding. It just finds devices
 768          * mentioned in the device tree.
 769          *
 770          * Before relocation, only bind devices marked for pre-relocation
 771          * use.
 772          */
 773         return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
 774                                 gd->flags & GD_FLG_RELOC ? false : true);
 775 }
 776
 777 static int decode_regions(struct pci_controller *hose, const void *blob,
 778                           int parent_node, int node)
 779 {
 780         int pci_addr_cells, addr_cells, size_cells;
 781         phys_addr_t base = 0, size;
 782         int cells_per_record;
 783         const u32 *prop;
 784         int len;
 785         int i;
 786
 787         prop = fdt_getprop(blob, node, "ranges", &len);
 788         if (!prop)
 789                 return -EINVAL;
 790         pci_addr_cells = fdt_address_cells(blob, node);
 791         addr_cells = fdt_address_cells(blob, parent_node);
 792         size_cells = fdt_size_cells(blob, node);
 793
 794         /* PCI addresses are always 3-cells */
 795         len /= sizeof(u32);
 796         cells_per_record = pci_addr_cells + addr_cells + size_cells;
 797         hose->region_count = 0;
 798         debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
 799               cells_per_record);
 800         for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
 801                 u64 pci_addr, addr, size;
 802                 int space_code;
 803                 u32 flags;
 804                 int type;
 805                 int pos;
 806
 807                 if (len < cells_per_record)
 808                         break;
 809                 flags = fdt32_to_cpu(prop[0]);
 810                 space_code = (flags >> 24) & 3;
 811                 pci_addr = fdtdec_get_number(prop + 1, 2);
 812                 prop += pci_addr_cells;
 813                 addr = fdtdec_get_number(prop, addr_cells);
 814                 prop += addr_cells;
 815                 size = fdtdec_get_number(prop, size_cells);
 816                 prop += size_cells;
 817                 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
 818                       ", size=%" PRIx64 ", space_code=%d\n", __func__,
 819                       hose->region_count, pci_addr, addr, size, space_code);
 820                 if (space_code & 2) {
 821                         type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
 822                                         PCI_REGION_MEM;
 823                 } else if (space_code & 1) {
 824                         type = PCI_REGION_IO;
 825                 } else {
 826                         continue;
 827                 }
 828                 pos = -1;
 829                 for (i = 0; i < hose->region_count; i++) {
 830                         if (hose->regions[i].flags == type)
 831                                 pos = i;
 832                 }
 833                 if (pos == -1)
 834                         pos = hose->region_count++;
 835                 debug(" - type=%d, pos=%d\n", type, pos);
 836                 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
 837         }
 838
 839         /* Add a region for our local memory */
 840         size = gd->ram_size;
 841 #ifdef CONFIG_SYS_SDRAM_BASE
 842         base = CONFIG_SYS_SDRAM_BASE;
 843 #endif
 844         if (gd->pci_ram_top && gd->pci_ram_top < base + size)
 845                 size = gd->pci_ram_top - base;
 846         pci_set_region(hose->regions + hose->region_count++, base, base,
 847                        size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 848
 849         return 0;
 850 }
 851
 852 static int pci_uclass_pre_probe(struct udevice *bus)
 853 {
 854         struct pci_controller *hose;
 855         int ret;
 856
 857         debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
 858               bus->parent->name);
 859         hose = bus->uclass_priv;
 860
 861         /* For bridges, use the top-level PCI controller */
 862         if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
 863                 hose->ctlr = bus;
 864                 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
 865                                 bus->of_offset);
 866                 if (ret) {
 867                         debug("%s: Cannot decode regions\n", __func__);
 868                         return ret;
 869                 }
 870         } else {
 871                 struct pci_controller *parent_hose;
 872
 873                 parent_hose = dev_get_uclass_priv(bus->parent);
 874                 hose->ctlr = parent_hose->bus;
 875         }
 876         hose->bus = bus;
 877         hose->first_busno = bus->seq;
 878         hose->last_busno = bus->seq;
 879
 880         return 0;
 881 }
 882
 883 static int pci_uclass_post_probe(struct udevice *bus)
 884 {
 885         int ret;
 886
 887         debug("%s: probing bus %d\n", __func__, bus->seq);
 888         ret = pci_bind_bus_devices(bus);
 889         if (ret)
 890                 return ret;
 891
 892 #ifdef CONFIG_PCI_PNP
 893         ret = pci_auto_config_devices(bus);
 894         if (ret < 0)
 895                 return ret;
 896 #endif
 897
 898 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 899         /*
 900          * Per Intel FSP specification, we should call FSP notify API to
 901          * inform FSP that PCI enumeration has been done so that FSP will
 902          * do any necessary initialization as required by the chipset's
 903          * BIOS Writer's Guide (BWG).
 904          *
 905          * Unfortunately we have to put this call here as with driver model,
 906          * the enumeration is all done on a lazy basis as needed, so until
 907          * something is touched on PCI it won't happen.
 908          *
 909          * Note we only call this 1) after U-Boot is relocated, and 2)
 910          * root bus has finished probing.
 911          */
 912         if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
 913                 ret = fsp_init_phase_pci();
 914                 if (ret)
 915                         return ret;
 916         }
 917 #endif
 918
 919         return 0;
 920 }
 921
 922 static int pci_uclass_child_post_bind(struct udevice *dev)
 923 {
 924         struct pci_child_platdata *pplat;
 925         struct fdt_pci_addr addr;
 926         int ret;
 927
 928         if (dev->of_offset == -1)
 929                 return 0;
 930
 931         /*
 932          * We could read vendor, device, class if available. But for now we
 933          * just check the address.
 934          */
 935         pplat = dev_get_parent_platdata(dev);
 936         ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
 937                                   FDT_PCI_SPACE_CONFIG, "reg", &addr);
 938
 939         if (ret) {
 940                 if (ret != -ENOENT)
 941                         return -EINVAL;
 942         } else {
 943                 /* extract the devfn from fdt_pci_addr */
 944                 pplat->devfn = addr.phys_hi & 0xff00;
 945         }
 946
 947         return 0;
 948 }
 949
 950 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
 951                                   uint offset, ulong *valuep,
 952                                   enum pci_size_t size)
 953 {
 954         struct pci_controller *hose = bus->uclass_priv;
 955
 956         return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
 957 }
 958
 959 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
 960                                    uint offset, ulong value,
 961                                    enum pci_size_t size)
 962 {
 963         struct pci_controller *hose = bus->uclass_priv;
 964
 965         return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
 966 }
 967
 968 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
 969 {
 970         struct udevice *dev;
 971         int ret = 0;
 972
 973         /*
 974          * Scan through all the PCI controllers. On x86 there will only be one
 975          * but that is not necessarily true on other hardware.
 976          */
 977         do {
 978                 device_find_first_child(bus, &dev);
 979                 if (dev) {
 980                         *devp = dev;
 981                         return 0;
 982                 }
 983                 ret = uclass_next_device(&bus);
 984                 if (ret)
 985                         return ret;
 986         } while (bus);
 987
 988         return 0;
 989 }
 990
 991 int pci_find_next_device(struct udevice **devp)
 992 {
 993         struct udevice *child = *devp;
 994         struct udevice *bus = child->parent;
 995         int ret;
 996
 997         /* First try all the siblings */
 998         *devp = NULL;
 999         while (child) {
1000                 device_find_next_child(&child);
1001                 if (child) {
1002                         *devp = child;
1003                         return 0;
1004                 }
1005         }
1006
1007         /* We ran out of siblings. Try the next bus */
1008         ret = uclass_next_device(&bus);
1009         if (ret)
1010                 return ret;
1011
1012         return bus ? skip_to_next_device(bus, devp) : 0;
1013 }
1014
1015 int pci_find_first_device(struct udevice **devp)
1016 {
1017         struct udevice *bus;
1018         int ret;
1019
1020         *devp = NULL;
1021         ret = uclass_first_device(UCLASS_PCI, &bus);
1022         if (ret)
1023                 return ret;
1024
1025         return skip_to_next_device(bus, devp);
1026 }
1027
1028 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1029 {
1030         switch (size) {
1031         case PCI_SIZE_8:
1032                 return (value >> ((offset & 3) * 8)) & 0xff;
1033         case PCI_SIZE_16:
1034                 return (value >> ((offset & 2) * 8)) & 0xffff;
1035         default:
1036                 return value;
1037         }
1038 }
1039
1040 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1041                           enum pci_size_t size)
1042 {
1043         uint off_mask;
1044         uint val_mask, shift;
1045         ulong ldata, mask;
1046
1047         switch (size) {
1048         case PCI_SIZE_8:
1049                 off_mask = 3;
1050                 val_mask = 0xff;
1051                 break;
1052         case PCI_SIZE_16:
1053                 off_mask = 2;
1054                 val_mask = 0xffff;
1055                 break;
1056         default:
1057                 return value;
1058         }
1059         shift = (offset & off_mask) * 8;
1060         ldata = (value & val_mask) << shift;
1061         mask = val_mask << shift;
1062         value = (old & ~mask) | ldata;
1063
1064         return value;
1065 }
1066
1067 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1068                     struct pci_region **memp, struct pci_region **prefp)
1069 {
1070         struct udevice *bus = pci_get_controller(dev);
1071         struct pci_controller *hose = dev_get_uclass_priv(bus);
1072         int i;
1073
1074         *iop = NULL;
1075         *memp = NULL;
1076         *prefp = NULL;
1077         for (i = 0; i < hose->region_count; i++) {
1078                 switch (hose->regions[i].flags) {
1079                 case PCI_REGION_IO:
1080                         if (!*iop || (*iop)->size < hose->regions[i].size)
1081                                 *iop = hose->regions + i;
1082                         break;
1083                 case PCI_REGION_MEM:
1084                         if (!*memp || (*memp)->size < hose->regions[i].size)
1085                                 *memp = hose->regions + i;
1086                         break;
1087                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1088                         if (!*prefp || (*prefp)->size < hose->regions[i].size)
1089                                 *prefp = hose->regions + i;
1090                         break;
1091                 }
1092         }
1093
1094         return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1095 }
1096
1097 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1098 {
1099         u32 addr;
1100         int bar;
1101
1102         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1103         dm_pci_read_config32(dev, bar, &addr);
1104         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1105                 return addr & PCI_BASE_ADDRESS_IO_MASK;
1106         else
1107                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1108 }
1109
1110 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1111 {
1112         int bar;
1113
1114         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1115         dm_pci_write_config32(dev, bar, addr);
1116 }
1117
1118 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1119                                pci_addr_t bus_addr, unsigned long flags,
1120                                unsigned long skip_mask, phys_addr_t *pa)
1121 {
1122         struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1123         struct pci_region *res;
1124         int i;
1125
1126         for (i = 0; i < hose->region_count; i++) {
1127                 res = &hose->regions[i];
1128
1129                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1130                         continue;
1131
1132                 if (res->flags & skip_mask)
1133                         continue;
1134
1135                 if (bus_addr >= res->bus_start &&
1136                     (bus_addr - res->bus_start) < res->size) {
1137                         *pa = (bus_addr - res->bus_start + res->phys_start);
1138                         return 0;
1139                 }
1140         }
1141
1142         return 1;
1143 }
1144
1145 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1146                                unsigned long flags)
1147 {
1148         phys_addr_t phys_addr = 0;
1149         struct udevice *ctlr;
1150         int ret;
1151
1152         /* The root controller has the region information */
1153         ctlr = pci_get_controller(dev);
1154
1155         /*
1156          * if PCI_REGION_MEM is set we do a two pass search with preference
1157          * on matches that don't have PCI_REGION_SYS_MEMORY set
1158          */
1159         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1160                 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1161                                           flags, PCI_REGION_SYS_MEMORY,
1162                                           &phys_addr);
1163                 if (!ret)
1164                         return phys_addr;
1165         }
1166
1167         ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1168
1169         if (ret)
1170                 puts("pci_hose_bus_to_phys: invalid physical address\n");
1171
1172         return phys_addr;
1173 }
1174
1175 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1176                         unsigned long flags, unsigned long skip_mask,
1177                         pci_addr_t *ba)
1178 {
1179         struct pci_region *res;
1180         struct udevice *ctlr;
1181         pci_addr_t bus_addr;
1182         int i;
1183         struct pci_controller *hose;
1184
1185         /* The root controller has the region information */
1186         ctlr = pci_get_controller(dev);
1187         hose = dev_get_uclass_priv(ctlr);
1188
1189         for (i = 0; i < hose->region_count; i++) {
1190                 res = &hose->regions[i];
1191
1192                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1193                         continue;
1194
1195                 if (res->flags & skip_mask)
1196                         continue;
1197
1198                 bus_addr = phys_addr - res->phys_start + res->bus_start;
1199
1200                 if (bus_addr >= res->bus_start &&
1201                     (bus_addr - res->bus_start) < res->size) {
1202                         *ba = bus_addr;
1203                         return 0;
1204                 }
1205         }
1206
1207         return 1;
1208 }
1209
1210 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1211                               unsigned long flags)
1212 {
1213         pci_addr_t bus_addr = 0;
1214         int ret;
1215
1216         /*
1217          * if PCI_REGION_MEM is set we do a two pass search with preference
1218          * on matches that don't have PCI_REGION_SYS_MEMORY set
1219          */
1220         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1221                 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1222                                           PCI_REGION_SYS_MEMORY, &bus_addr);
1223                 if (!ret)
1224                         return bus_addr;
1225         }
1226
1227         ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1228
1229         if (ret)
1230                 puts("pci_hose_phys_to_bus: invalid physical address\n");
1231
1232         return bus_addr;
1233 }
1234
1235 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1236 {
1237         pci_addr_t pci_bus_addr;
1238         u32 bar_response;
1239
1240         /* read BAR address */
1241         dm_pci_read_config32(dev, bar, &bar_response);
1242         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1243
1244         /*
1245          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
1246          * isn't actualy used on any platform because u-boot assumes a static
1247          * linear mapping.  In the future, this could read the BAR size
1248          * and pass that as the size if needed.
1249          */
1250         return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1251 }
1252
1253 UCLASS_DRIVER(pci) = {
1254         .id             = UCLASS_PCI,
1255         .name           = "pci",
1256         .flags          = DM_UC_FLAG_SEQ_ALIAS,
1257         .post_bind      = pci_uclass_post_bind,
1258         .pre_probe      = pci_uclass_pre_probe,
1259         .post_probe     = pci_uclass_post_probe,
1260         .child_post_bind = pci_uclass_child_post_bind,
1261         .per_device_auto_alloc_size = sizeof(struct pci_controller),
1262         .per_child_platdata_auto_alloc_size =
1263                         sizeof(struct pci_child_platdata),
1264 };
1265
1266 static const struct dm_pci_ops pci_bridge_ops = {
1267         .read_config    = pci_bridge_read_config,
1268         .write_config   = pci_bridge_write_config,
1269 };
1270
1271 static const struct udevice_id pci_bridge_ids[] = {
1272         { .compatible = "pci-bridge" },
1273         { }
1274 };
1275
1276 U_BOOT_DRIVER(pci_bridge_drv) = {
1277         .name           = "pci_bridge_drv",
1278         .id             = UCLASS_PCI,
1279         .of_match       = pci_bridge_ids,
1280         .ops            = &pci_bridge_ops,
1281 };
1282
1283 UCLASS_DRIVER(pci_generic) = {
1284         .id             = UCLASS_PCI_GENERIC,
1285         .name           = "pci_generic",
1286 };
1287
1288 static const struct udevice_id pci_generic_ids[] = {
1289         { .compatible = "pci-generic" },
1290         { }
1291 };
1292
1293 U_BOOT_DRIVER(pci_generic_drv) = {
1294         .name           = "pci_generic_drv",
1295         .id             = UCLASS_PCI_GENERIC,
1296         .of_match       = pci_generic_ids,
1297 };
1298
1299 void pci_init(void)
1300 {
1301         struct udevice *bus;
1302
1303         /*
1304          * Enumerate all known controller devices. Enumeration has the side-
1305          * effect of probing them, so PCIe devices will be enumerated too.
1306          */
1307         for (uclass_first_device(UCLASS_PCI, &bus);
1308              bus;
1309              uclass_next_device(&bus)) {
1310                 ;
1311         }
1312 }