drivers/pci/pci-uclass.c

   1 /*
   2  * Copyright (c) 2014 Google, Inc
   3  * Written by Simon Glass <sjg@chromium.org>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <fdtdec.h>
  12 #include <inttypes.h>
  13 #include <pci.h>
  14 #include <asm/io.h>
  15 #include <dm/lists.h>
  16 #include <dm/root.h>
  17 #include <dm/device-internal.h>
  18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
  19 #include <asm/fsp/fsp_support.h>
  20 #endif
  21 #include "pci_internal.h"
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 int pci_get_bus(int busnum, struct udevice **busp)
  26 {
  27         int ret;
  28
  29         ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  30
  31         /* Since buses may not be numbered yet try a little harder with bus 0 */
  32         if (ret == -ENODEV) {
  33                 ret = uclass_first_device(UCLASS_PCI, busp);
  34                 if (ret)
  35                         return ret;
  36                 else if (!*busp)
  37                         return -ENODEV;
  38                 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
  39         }
  40
  41         return ret;
  42 }
  43
  44 struct udevice *pci_get_controller(struct udevice *dev)
  45 {
  46         while (device_is_on_pci_bus(dev))
  47                 dev = dev->parent;
  48
  49         return dev;
  50 }
  51
  52 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
  53 {
  54         struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  55         struct udevice *bus = dev->parent;
  56
  57         return PCI_ADD_BUS(bus->seq, pplat->devfn);
  58 }
  59
  60 /**
  61  * pci_get_bus_max() - returns the bus number of the last active bus
  62  *
  63  * @return last bus number, or -1 if no active buses
  64  */
  65 static int pci_get_bus_max(void)
  66 {
  67         struct udevice *bus;
  68         struct uclass *uc;
  69         int ret = -1;
  70
  71         ret = uclass_get(UCLASS_PCI, &uc);
  72         uclass_foreach_dev(bus, uc) {
  73                 if (bus->seq > ret)
  74                         ret = bus->seq;
  75         }
  76
  77         debug("%s: ret=%d\n", __func__, ret);
  78
  79         return ret;
  80 }
  81
  82 int pci_last_busno(void)
  83 {
  84         return pci_get_bus_max();
  85 }
  86
  87 int pci_get_ff(enum pci_size_t size)
  88 {
  89         switch (size) {
  90         case PCI_SIZE_8:
  91                 return 0xff;
  92         case PCI_SIZE_16:
  93                 return 0xffff;
  94         default:
  95                 return 0xffffffff;
  96         }
  97 }
  98
  99 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
 100                        struct udevice **devp)
 101 {
 102         struct udevice *dev;
 103
 104         for (device_find_first_child(bus, &dev);
 105              dev;
 106              device_find_next_child(&dev)) {
 107                 struct pci_child_platdata *pplat;
 108
 109                 pplat = dev_get_parent_platdata(dev);
 110                 if (pplat && pplat->devfn == find_devfn) {
 111                         *devp = dev;
 112                         return 0;
 113                 }
 114         }
 115
 116         return -ENODEV;
 117 }
 118
 119 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
 120 {
 121         struct udevice *bus;
 122         int ret;
 123
 124         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 125         if (ret)
 126                 return ret;
 127         return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
 128 }
 129
 130 static int pci_device_matches_ids(struct udevice *dev,
 131                                   struct pci_device_id *ids)
 132 {
 133         struct pci_child_platdata *pplat;
 134         int i;
 135
 136         pplat = dev_get_parent_platdata(dev);
 137         if (!pplat)
 138                 return -EINVAL;
 139         for (i = 0; ids[i].vendor != 0; i++) {
 140                 if (pplat->vendor == ids[i].vendor &&
 141                     pplat->device == ids[i].device)
 142                         return i;
 143         }
 144
 145         return -EINVAL;
 146 }
 147
 148 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
 149                          int *indexp, struct udevice **devp)
 150 {
 151         struct udevice *dev;
 152
 153         /* Scan all devices on this bus */
 154         for (device_find_first_child(bus, &dev);
 155              dev;
 156              device_find_next_child(&dev)) {
 157                 if (pci_device_matches_ids(dev, ids) >= 0) {
 158                         if ((*indexp)-- <= 0) {
 159                                 *devp = dev;
 160                                 return 0;
 161                         }
 162                 }
 163         }
 164
 165         return -ENODEV;
 166 }
 167
 168 int pci_find_device_id(struct pci_device_id *ids, int index,
 169                        struct udevice **devp)
 170 {
 171         struct udevice *bus;
 172
 173         /* Scan all known buses */
 174         for (uclass_first_device(UCLASS_PCI, &bus);
 175              bus;
 176              uclass_next_device(&bus)) {
 177                 if (!pci_bus_find_devices(bus, ids, &index, devp))
 178                         return 0;
 179         }
 180         *devp = NULL;
 181
 182         return -ENODEV;
 183 }
 184
 185 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
 186                                   unsigned int device, int *indexp,
 187                                   struct udevice **devp)
 188 {
 189         struct pci_child_platdata *pplat;
 190         struct udevice *dev;
 191
 192         for (device_find_first_child(bus, &dev);
 193              dev;
 194              device_find_next_child(&dev)) {
 195                 pplat = dev_get_parent_platdata(dev);
 196                 if (pplat->vendor == vendor && pplat->device == device) {
 197                         if (!(*indexp)--) {
 198                                 *devp = dev;
 199                                 return 0;
 200                         }
 201                 }
 202         }
 203
 204         return -ENODEV;
 205 }
 206
 207 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
 208                        struct udevice **devp)
 209 {
 210         struct udevice *bus;
 211
 212         /* Scan all known buses */
 213         for (uclass_first_device(UCLASS_PCI, &bus);
 214              bus;
 215              uclass_next_device(&bus)) {
 216                 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
 217                         return device_probe(*devp);
 218         }
 219         *devp = NULL;
 220
 221         return -ENODEV;
 222 }
 223
 224 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
 225 {
 226         struct udevice *dev;
 227
 228         /* Scan all known buses */
 229         for (pci_find_first_device(&dev);
 230              dev;
 231              pci_find_next_device(&dev)) {
 232                 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
 233
 234                 if (pplat->class == find_class && !index--) {
 235                         *devp = dev;
 236                         return device_probe(*devp);
 237                 }
 238         }
 239         *devp = NULL;
 240
 241         return -ENODEV;
 242 }
 243
 244 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
 245                          unsigned long value, enum pci_size_t size)
 246 {
 247         struct dm_pci_ops *ops;
 248
 249         ops = pci_get_ops(bus);
 250         if (!ops->write_config)
 251                 return -ENOSYS;
 252         return ops->write_config(bus, bdf, offset, value, size);
 253 }
 254
 255 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
 256                      enum pci_size_t size)
 257 {
 258         struct udevice *bus;
 259         int ret;
 260
 261         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 262         if (ret)
 263                 return ret;
 264
 265         return pci_bus_write_config(bus, bdf, offset, value, size);
 266 }
 267
 268 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
 269                         enum pci_size_t size)
 270 {
 271         struct udevice *bus;
 272
 273         for (bus = dev; device_is_on_pci_bus(bus);)
 274                 bus = bus->parent;
 275         return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
 276                                     size);
 277 }
 278
 279
 280 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
 281 {
 282         return pci_write_config(bdf, offset, value, PCI_SIZE_32);
 283 }
 284
 285 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
 286 {
 287         return pci_write_config(bdf, offset, value, PCI_SIZE_16);
 288 }
 289
 290 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
 291 {
 292         return pci_write_config(bdf, offset, value, PCI_SIZE_8);
 293 }
 294
 295 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
 296 {
 297         return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
 298 }
 299
 300 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
 301 {
 302         return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
 303 }
 304
 305 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
 306 {
 307         return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
 308 }
 309
 310 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
 311                         unsigned long *valuep, enum pci_size_t size)
 312 {
 313         struct dm_pci_ops *ops;
 314
 315         ops = pci_get_ops(bus);
 316         if (!ops->read_config)
 317                 return -ENOSYS;
 318         return ops->read_config(bus, bdf, offset, valuep, size);
 319 }
 320
 321 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
 322                     enum pci_size_t size)
 323 {
 324         struct udevice *bus;
 325         int ret;
 326
 327         ret = pci_get_bus(PCI_BUS(bdf), &bus);
 328         if (ret)
 329                 return ret;
 330
 331         return pci_bus_read_config(bus, bdf, offset, valuep, size);
 332 }
 333
 334 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
 335                        enum pci_size_t size)
 336 {
 337         struct udevice *bus;
 338
 339         for (bus = dev; device_is_on_pci_bus(bus);)
 340                 bus = bus->parent;
 341         return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
 342                                    size);
 343 }
 344
 345 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
 346 {
 347         unsigned long value;
 348         int ret;
 349
 350         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
 351         if (ret)
 352                 return ret;
 353         *valuep = value;
 354
 355         return 0;
 356 }
 357
 358 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
 359 {
 360         unsigned long value;
 361         int ret;
 362
 363         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
 364         if (ret)
 365                 return ret;
 366         *valuep = value;
 367
 368         return 0;
 369 }
 370
 371 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
 372 {
 373         unsigned long value;
 374         int ret;
 375
 376         ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
 377         if (ret)
 378                 return ret;
 379         *valuep = value;
 380
 381         return 0;
 382 }
 383
 384 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
 385 {
 386         unsigned long value;
 387         int ret;
 388
 389         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
 390         if (ret)
 391                 return ret;
 392         *valuep = value;
 393
 394         return 0;
 395 }
 396
 397 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
 398 {
 399         unsigned long value;
 400         int ret;
 401
 402         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
 403         if (ret)
 404                 return ret;
 405         *valuep = value;
 406
 407         return 0;
 408 }
 409
 410 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
 411 {
 412         unsigned long value;
 413         int ret;
 414
 415         ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
 416         if (ret)
 417                 return ret;
 418         *valuep = value;
 419
 420         return 0;
 421 }
 422
 423 static void set_vga_bridge_bits(struct udevice *dev)
 424 {
 425         struct udevice *parent = dev->parent;
 426         u16 bc;
 427
 428         while (parent->seq != 0) {
 429                 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
 430                 bc |= PCI_BRIDGE_CTL_VGA;
 431                 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
 432                 parent = parent->parent;
 433         }
 434 }
 435
 436 int pci_auto_config_devices(struct udevice *bus)
 437 {
 438         struct pci_controller *hose = bus->uclass_priv;
 439         struct pci_child_platdata *pplat;
 440         unsigned int sub_bus;
 441         struct udevice *dev;
 442         int ret;
 443
 444         sub_bus = bus->seq;
 445         debug("%s: start\n", __func__);
 446         pciauto_config_init(hose);
 447         for (ret = device_find_first_child(bus, &dev);
 448              !ret && dev;
 449              ret = device_find_next_child(&dev)) {
 450                 unsigned int max_bus;
 451                 int ret;
 452
 453                 debug("%s: device %s\n", __func__, dev->name);
 454                 ret = dm_pciauto_config_device(dev);
 455                 if (ret < 0)
 456                         return ret;
 457                 max_bus = ret;
 458                 sub_bus = max(sub_bus, max_bus);
 459
 460                 pplat = dev_get_parent_platdata(dev);
 461                 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
 462                         set_vga_bridge_bits(dev);
 463         }
 464         debug("%s: done\n", __func__);
 465
 466         return sub_bus;
 467 }
 468
 469 int dm_pci_hose_probe_bus(struct udevice *bus)
 470 {
 471         int sub_bus;
 472         int ret;
 473
 474         debug("%s\n", __func__);
 475
 476         sub_bus = pci_get_bus_max() + 1;
 477         debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
 478         dm_pciauto_prescan_setup_bridge(bus, sub_bus);
 479
 480         ret = device_probe(bus);
 481         if (ret) {
 482                 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
 483                       ret);
 484                 return ret;
 485         }
 486         if (sub_bus != bus->seq) {
 487                 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
 488                        __func__, bus->name, bus->seq, sub_bus);
 489                 return -EPIPE;
 490         }
 491         sub_bus = pci_get_bus_max();
 492         dm_pciauto_postscan_setup_bridge(bus, sub_bus);
 493
 494         return sub_bus;
 495 }
 496
 497 /**
 498  * pci_match_one_device - Tell if a PCI device structure has a matching
 499  *                        PCI device id structure
 500  * @id: single PCI device id structure to match
 501  * @dev: the PCI device structure to match against
 502  *
 503  * Returns the matching pci_device_id structure or %NULL if there is no match.
 504  */
 505 static bool pci_match_one_id(const struct pci_device_id *id,
 506                              const struct pci_device_id *find)
 507 {
 508         if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
 509             (id->device == PCI_ANY_ID || id->device == find->device) &&
 510             (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
 511             (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
 512             !((id->class ^ find->class) & id->class_mask))
 513                 return true;
 514
 515         return false;
 516 }
 517
 518 /**
 519  * pci_find_and_bind_driver() - Find and bind the right PCI driver
 520  *
 521  * This only looks at certain fields in the descriptor.
 522  *
 523  * @parent:     Parent bus
 524  * @find_id:    Specification of the driver to find
 525  * @bdf:        Bus/device/function addreess - see PCI_BDF()
 526  * @devp:       Returns a pointer to the device created
 527  * @return 0 if OK, -EPERM if the device is not needed before relocation and
 528  *         therefore was not created, other -ve value on error
 529  */
 530 static int pci_find_and_bind_driver(struct udevice *parent,
 531                                     struct pci_device_id *find_id,
 532                                     pci_dev_t bdf, struct udevice **devp)
 533 {
 534         struct pci_driver_entry *start, *entry;
 535         const char *drv;
 536         int n_ents;
 537         int ret;
 538         char name[30], *str;
 539         bool bridge;
 540
 541         *devp = NULL;
 542
 543         debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
 544               find_id->vendor, find_id->device);
 545         start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
 546         n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
 547         for (entry = start; entry != start + n_ents; entry++) {
 548                 const struct pci_device_id *id;
 549                 struct udevice *dev;
 550                 const struct driver *drv;
 551
 552                 for (id = entry->match;
 553                      id->vendor || id->subvendor || id->class_mask;
 554                      id++) {
 555                         if (!pci_match_one_id(id, find_id))
 556                                 continue;
 557
 558                         drv = entry->driver;
 559
 560                         /*
 561                          * In the pre-relocation phase, we only bind devices
 562                          * whose driver has the DM_FLAG_PRE_RELOC set, to save
 563                          * precious memory space as on some platforms as that
 564                          * space is pretty limited (ie: using Cache As RAM).
 565                          */
 566                         if (!(gd->flags & GD_FLG_RELOC) &&
 567                             !(drv->flags & DM_FLAG_PRE_RELOC))
 568                                 return -EPERM;
 569
 570                         /*
 571                          * We could pass the descriptor to the driver as
 572                          * platdata (instead of NULL) and allow its bind()
 573                          * method to return -ENOENT if it doesn't support this
 574                          * device. That way we could continue the search to
 575                          * find another driver. For now this doesn't seem
 576                          * necesssary, so just bind the first match.
 577                          */
 578                         ret = device_bind(parent, drv, drv->name, NULL, -1,
 579                                           &dev);
 580                         if (ret)
 581                                 goto error;
 582                         debug("%s: Match found: %s\n", __func__, drv->name);
 583                         dev->driver_data = find_id->driver_data;
 584                         *devp = dev;
 585                         return 0;
 586                 }
 587         }
 588
 589         bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
 590         /*
 591          * In the pre-relocation phase, we only bind bridge devices to save
 592          * precious memory space as on some platforms as that space is pretty
 593          * limited (ie: using Cache As RAM).
 594          */
 595         if (!(gd->flags & GD_FLG_RELOC) && !bridge)
 596                 return -EPERM;
 597
 598         /* Bind a generic driver so that the device can be used */
 599         sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
 600                 PCI_FUNC(bdf));
 601         str = strdup(name);
 602         if (!str)
 603                 return -ENOMEM;
 604         drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
 605
 606         ret = device_bind_driver(parent, drv, str, devp);
 607         if (ret) {
 608                 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
 609                 return ret;
 610         }
 611         debug("%s: No match found: bound generic driver instead\n", __func__);
 612
 613         return 0;
 614
 615 error:
 616         debug("%s: No match found: error %d\n", __func__, ret);
 617         return ret;
 618 }
 619
 620 int pci_bind_bus_devices(struct udevice *bus)
 621 {
 622         ulong vendor, device;
 623         ulong header_type;
 624         pci_dev_t bdf, end;
 625         bool found_multi;
 626         int ret;
 627
 628         found_multi = false;
 629         end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
 630                       PCI_MAX_PCI_FUNCTIONS - 1);
 631         for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
 632              bdf += PCI_BDF(0, 0, 1)) {
 633                 struct pci_child_platdata *pplat;
 634                 struct udevice *dev;
 635                 ulong class;
 636
 637                 if (PCI_FUNC(bdf) && !found_multi)
 638                         continue;
 639                 /* Check only the first access, we don't expect problems */
 640                 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
 641                                           &header_type, PCI_SIZE_8);
 642                 if (ret)
 643                         goto error;
 644                 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
 645                                     PCI_SIZE_16);
 646                 if (vendor == 0xffff || vendor == 0x0000)
 647                         continue;
 648
 649                 if (!PCI_FUNC(bdf))
 650                         found_multi = header_type & 0x80;
 651
 652                 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
 653                       bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
 654                 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
 655                                     PCI_SIZE_16);
 656                 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
 657                                     PCI_SIZE_32);
 658                 class >>= 8;
 659
 660                 /* Find this device in the device tree */
 661                 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
 662
 663                 /* If nothing in the device tree, bind a device */
 664                 if (ret == -ENODEV) {
 665                         struct pci_device_id find_id;
 666                         ulong val;
 667
 668                         memset(&find_id, '\0', sizeof(find_id));
 669                         find_id.vendor = vendor;
 670                         find_id.device = device;
 671                         find_id.class = class;
 672                         if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
 673                                 pci_bus_read_config(bus, bdf,
 674                                                     PCI_SUBSYSTEM_VENDOR_ID,
 675                                                     &val, PCI_SIZE_32);
 676                                 find_id.subvendor = val & 0xffff;
 677                                 find_id.subdevice = val >> 16;
 678                         }
 679                         ret = pci_find_and_bind_driver(bus, &find_id, bdf,
 680                                                        &dev);
 681                 }
 682                 if (ret == -EPERM)
 683                         continue;
 684                 else if (ret)
 685                         return ret;
 686
 687                 /* Update the platform data */
 688                 pplat = dev_get_parent_platdata(dev);
 689                 pplat->devfn = PCI_MASK_BUS(bdf);
 690                 pplat->vendor = vendor;
 691                 pplat->device = device;
 692                 pplat->class = class;
 693         }
 694
 695         return 0;
 696 error:
 697         printf("Cannot read bus configuration: %d\n", ret);
 698
 699         return ret;
 700 }
 701
 702 static int pci_uclass_post_bind(struct udevice *bus)
 703 {
 704         /*
 705          * If there is no pci device listed in the device tree,
 706          * don't bother scanning the device tree.
 707          */
 708         if (bus->of_offset == -1)
 709                 return 0;
 710
 711         /*
 712          * Scan the device tree for devices. This does not probe the PCI bus,
 713          * as this is not permitted while binding. It just finds devices
 714          * mentioned in the device tree.
 715          *
 716          * Before relocation, only bind devices marked for pre-relocation
 717          * use.
 718          */
 719         return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
 720                                 gd->flags & GD_FLG_RELOC ? false : true);
 721 }
 722
 723 static int decode_regions(struct pci_controller *hose, const void *blob,
 724                           int parent_node, int node)
 725 {
 726         int pci_addr_cells, addr_cells, size_cells;
 727         phys_addr_t base = 0, size;
 728         int cells_per_record;
 729         const u32 *prop;
 730         int len;
 731         int i;
 732
 733         prop = fdt_getprop(blob, node, "ranges", &len);
 734         if (!prop)
 735                 return -EINVAL;
 736         pci_addr_cells = fdt_address_cells(blob, node);
 737         addr_cells = fdt_address_cells(blob, parent_node);
 738         size_cells = fdt_size_cells(blob, node);
 739
 740         /* PCI addresses are always 3-cells */
 741         len /= sizeof(u32);
 742         cells_per_record = pci_addr_cells + addr_cells + size_cells;
 743         hose->region_count = 0;
 744         debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
 745               cells_per_record);
 746         for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
 747                 u64 pci_addr, addr, size;
 748                 int space_code;
 749                 u32 flags;
 750                 int type;
 751                 int pos;
 752
 753                 if (len < cells_per_record)
 754                         break;
 755                 flags = fdt32_to_cpu(prop[0]);
 756                 space_code = (flags >> 24) & 3;
 757                 pci_addr = fdtdec_get_number(prop + 1, 2);
 758                 prop += pci_addr_cells;
 759                 addr = fdtdec_get_number(prop, addr_cells);
 760                 prop += addr_cells;
 761                 size = fdtdec_get_number(prop, size_cells);
 762                 prop += size_cells;
 763                 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
 764                       ", size=%" PRIx64 ", space_code=%d\n", __func__,
 765                       hose->region_count, pci_addr, addr, size, space_code);
 766                 if (space_code & 2) {
 767                         type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
 768                                         PCI_REGION_MEM;
 769                 } else if (space_code & 1) {
 770                         type = PCI_REGION_IO;
 771                 } else {
 772                         continue;
 773                 }
 774                 pos = -1;
 775                 for (i = 0; i < hose->region_count; i++) {
 776                         if (hose->regions[i].flags == type)
 777                                 pos = i;
 778                 }
 779                 if (pos == -1)
 780                         pos = hose->region_count++;
 781                 debug(" - type=%d, pos=%d\n", type, pos);
 782                 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
 783         }
 784
 785         /* Add a region for our local memory */
 786         size = gd->ram_size;
 787 #ifdef CONFIG_SYS_SDRAM_BASE
 788         base = CONFIG_SYS_SDRAM_BASE;
 789 #endif
 790         if (gd->pci_ram_top && gd->pci_ram_top < base + size)
 791                 size = gd->pci_ram_top - base;
 792         pci_set_region(hose->regions + hose->region_count++, base, base,
 793                        size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 794
 795         return 0;
 796 }
 797
 798 static int pci_uclass_pre_probe(struct udevice *bus)
 799 {
 800         struct pci_controller *hose;
 801         int ret;
 802
 803         debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
 804               bus->parent->name);
 805         hose = bus->uclass_priv;
 806
 807         /* For bridges, use the top-level PCI controller */
 808         if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
 809                 hose->ctlr = bus;
 810                 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
 811                                 bus->of_offset);
 812                 if (ret) {
 813                         debug("%s: Cannot decode regions\n", __func__);
 814                         return ret;
 815                 }
 816         } else {
 817                 struct pci_controller *parent_hose;
 818
 819                 parent_hose = dev_get_uclass_priv(bus->parent);
 820                 hose->ctlr = parent_hose->bus;
 821         }
 822         hose->bus = bus;
 823         hose->first_busno = bus->seq;
 824         hose->last_busno = bus->seq;
 825
 826         return 0;
 827 }
 828
 829 static int pci_uclass_post_probe(struct udevice *bus)
 830 {
 831         int ret;
 832
 833         debug("%s: probing bus %d\n", __func__, bus->seq);
 834         ret = pci_bind_bus_devices(bus);
 835         if (ret)
 836                 return ret;
 837
 838 #ifdef CONFIG_PCI_PNP
 839         ret = pci_auto_config_devices(bus);
 840         if (ret < 0)
 841                 return ret;
 842 #endif
 843
 844 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
 845         /*
 846          * Per Intel FSP specification, we should call FSP notify API to
 847          * inform FSP that PCI enumeration has been done so that FSP will
 848          * do any necessary initialization as required by the chipset's
 849          * BIOS Writer's Guide (BWG).
 850          *
 851          * Unfortunately we have to put this call here as with driver model,
 852          * the enumeration is all done on a lazy basis as needed, so until
 853          * something is touched on PCI it won't happen.
 854          *
 855          * Note we only call this 1) after U-Boot is relocated, and 2)
 856          * root bus has finished probing.
 857          */
 858         if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
 859                 ret = fsp_init_phase_pci();
 860                 if (ret)
 861                         return ret;
 862         }
 863 #endif
 864
 865         return 0;
 866 }
 867
 868 static int pci_uclass_child_post_bind(struct udevice *dev)
 869 {
 870         struct pci_child_platdata *pplat;
 871         struct fdt_pci_addr addr;
 872         int ret;
 873
 874         if (dev->of_offset == -1)
 875                 return 0;
 876
 877         /*
 878          * We could read vendor, device, class if available. But for now we
 879          * just check the address.
 880          */
 881         pplat = dev_get_parent_platdata(dev);
 882         ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
 883                                   FDT_PCI_SPACE_CONFIG, "reg", &addr);
 884
 885         if (ret) {
 886                 if (ret != -ENOENT)
 887                         return -EINVAL;
 888         } else {
 889                 /* extract the devfn from fdt_pci_addr */
 890                 pplat->devfn = addr.phys_hi & 0xff00;
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
 897                                   uint offset, ulong *valuep,
 898                                   enum pci_size_t size)
 899 {
 900         struct pci_controller *hose = bus->uclass_priv;
 901
 902         return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
 903 }
 904
 905 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
 906                                    uint offset, ulong value,
 907                                    enum pci_size_t size)
 908 {
 909         struct pci_controller *hose = bus->uclass_priv;
 910
 911         return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
 912 }
 913
 914 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
 915 {
 916         struct udevice *dev;
 917         int ret = 0;
 918
 919         /*
 920          * Scan through all the PCI controllers. On x86 there will only be one
 921          * but that is not necessarily true on other hardware.
 922          */
 923         do {
 924                 device_find_first_child(bus, &dev);
 925                 if (dev) {
 926                         *devp = dev;
 927                         return 0;
 928                 }
 929                 ret = uclass_next_device(&bus);
 930                 if (ret)
 931                         return ret;
 932         } while (bus);
 933
 934         return 0;
 935 }
 936
 937 int pci_find_next_device(struct udevice **devp)
 938 {
 939         struct udevice *child = *devp;
 940         struct udevice *bus = child->parent;
 941         int ret;
 942
 943         /* First try all the siblings */
 944         *devp = NULL;
 945         while (child) {
 946                 device_find_next_child(&child);
 947                 if (child) {
 948                         *devp = child;
 949                         return 0;
 950                 }
 951         }
 952
 953         /* We ran out of siblings. Try the next bus */
 954         ret = uclass_next_device(&bus);
 955         if (ret)
 956                 return ret;
 957
 958         return bus ? skip_to_next_device(bus, devp) : 0;
 959 }
 960
 961 int pci_find_first_device(struct udevice **devp)
 962 {
 963         struct udevice *bus;
 964         int ret;
 965
 966         *devp = NULL;
 967         ret = uclass_first_device(UCLASS_PCI, &bus);
 968         if (ret)
 969                 return ret;
 970
 971         return skip_to_next_device(bus, devp);
 972 }
 973
 974 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
 975 {
 976         switch (size) {
 977         case PCI_SIZE_8:
 978                 return (value >> ((offset & 3) * 8)) & 0xff;
 979         case PCI_SIZE_16:
 980                 return (value >> ((offset & 2) * 8)) & 0xffff;
 981         default:
 982                 return value;
 983         }
 984 }
 985
 986 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
 987                           enum pci_size_t size)
 988 {
 989         uint off_mask;
 990         uint val_mask, shift;
 991         ulong ldata, mask;
 992
 993         switch (size) {
 994         case PCI_SIZE_8:
 995                 off_mask = 3;
 996                 val_mask = 0xff;
 997                 break;
 998         case PCI_SIZE_16:
 999                 off_mask = 2;
1000                 val_mask = 0xffff;
1001                 break;
1002         default:
1003                 return value;
1004         }
1005         shift = (offset & off_mask) * 8;
1006         ldata = (value & val_mask) << shift;
1007         mask = val_mask << shift;
1008         value = (old & ~mask) | ldata;
1009
1010         return value;
1011 }
1012
1013 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1014                     struct pci_region **memp, struct pci_region **prefp)
1015 {
1016         struct udevice *bus = pci_get_controller(dev);
1017         struct pci_controller *hose = dev_get_uclass_priv(bus);
1018         int i;
1019
1020         *iop = NULL;
1021         *memp = NULL;
1022         *prefp = NULL;
1023         for (i = 0; i < hose->region_count; i++) {
1024                 switch (hose->regions[i].flags) {
1025                 case PCI_REGION_IO:
1026                         if (!*iop || (*iop)->size < hose->regions[i].size)
1027                                 *iop = hose->regions + i;
1028                         break;
1029                 case PCI_REGION_MEM:
1030                         if (!*memp || (*memp)->size < hose->regions[i].size)
1031                                 *memp = hose->regions + i;
1032                         break;
1033                 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1034                         if (!*prefp || (*prefp)->size < hose->regions[i].size)
1035                                 *prefp = hose->regions + i;
1036                         break;
1037                 }
1038         }
1039
1040         return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1041 }
1042
1043 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1044 {
1045         u32 addr;
1046         int bar;
1047
1048         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1049         dm_pci_read_config32(dev, bar, &addr);
1050         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1051                 return addr & PCI_BASE_ADDRESS_IO_MASK;
1052         else
1053                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1054 }
1055
1056 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1057 {
1058         int bar;
1059
1060         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1061         dm_pci_write_config32(dev, bar, addr);
1062 }
1063
1064 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1065                                pci_addr_t bus_addr, unsigned long flags,
1066                                unsigned long skip_mask, phys_addr_t *pa)
1067 {
1068         struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1069         struct pci_region *res;
1070         int i;
1071
1072         for (i = 0; i < hose->region_count; i++) {
1073                 res = &hose->regions[i];
1074
1075                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1076                         continue;
1077
1078                 if (res->flags & skip_mask)
1079                         continue;
1080
1081                 if (bus_addr >= res->bus_start &&
1082                     (bus_addr - res->bus_start) < res->size) {
1083                         *pa = (bus_addr - res->bus_start + res->phys_start);
1084                         return 0;
1085                 }
1086         }
1087
1088         return 1;
1089 }
1090
1091 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1092                                unsigned long flags)
1093 {
1094         phys_addr_t phys_addr = 0;
1095         struct udevice *ctlr;
1096         int ret;
1097
1098         /* The root controller has the region information */
1099         ctlr = pci_get_controller(dev);
1100
1101         /*
1102          * if PCI_REGION_MEM is set we do a two pass search with preference
1103          * on matches that don't have PCI_REGION_SYS_MEMORY set
1104          */
1105         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1106                 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1107                                           flags, PCI_REGION_SYS_MEMORY,
1108                                           &phys_addr);
1109                 if (!ret)
1110                         return phys_addr;
1111         }
1112
1113         ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1114
1115         if (ret)
1116                 puts("pci_hose_bus_to_phys: invalid physical address\n");
1117
1118         return phys_addr;
1119 }
1120
1121 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1122                         unsigned long flags, unsigned long skip_mask,
1123                         pci_addr_t *ba)
1124 {
1125         struct pci_region *res;
1126         struct udevice *ctlr;
1127         pci_addr_t bus_addr;
1128         int i;
1129         struct pci_controller *hose;
1130
1131         /* The root controller has the region information */
1132         ctlr = pci_get_controller(dev);
1133         hose = dev_get_uclass_priv(ctlr);
1134
1135         for (i = 0; i < hose->region_count; i++) {
1136                 res = &hose->regions[i];
1137
1138                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1139                         continue;
1140
1141                 if (res->flags & skip_mask)
1142                         continue;
1143
1144                 bus_addr = phys_addr - res->phys_start + res->bus_start;
1145
1146                 if (bus_addr >= res->bus_start &&
1147                     (bus_addr - res->bus_start) < res->size) {
1148                         *ba = bus_addr;
1149                         return 0;
1150                 }
1151         }
1152
1153         return 1;
1154 }
1155
1156 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1157                               unsigned long flags)
1158 {
1159         pci_addr_t bus_addr = 0;
1160         int ret;
1161
1162         /*
1163          * if PCI_REGION_MEM is set we do a two pass search with preference
1164          * on matches that don't have PCI_REGION_SYS_MEMORY set
1165          */
1166         if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1167                 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1168                                           PCI_REGION_SYS_MEMORY, &bus_addr);
1169                 if (!ret)
1170                         return bus_addr;
1171         }
1172
1173         ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1174
1175         if (ret)
1176                 puts("pci_hose_phys_to_bus: invalid physical address\n");
1177
1178         return bus_addr;
1179 }
1180
1181 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1182 {
1183         pci_addr_t pci_bus_addr;
1184         u32 bar_response;
1185
1186         /* read BAR address */
1187         dm_pci_read_config32(dev, bar, &bar_response);
1188         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1189
1190         /*
1191          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
1192          * isn't actualy used on any platform because u-boot assumes a static
1193          * linear mapping.  In the future, this could read the BAR size
1194          * and pass that as the size if needed.
1195          */
1196         return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1197 }
1198
1199 UCLASS_DRIVER(pci) = {
1200         .id             = UCLASS_PCI,
1201         .name           = "pci",
1202         .flags          = DM_UC_FLAG_SEQ_ALIAS,
1203         .post_bind      = pci_uclass_post_bind,
1204         .pre_probe      = pci_uclass_pre_probe,
1205         .post_probe     = pci_uclass_post_probe,
1206         .child_post_bind = pci_uclass_child_post_bind,
1207         .per_device_auto_alloc_size = sizeof(struct pci_controller),
1208         .per_child_platdata_auto_alloc_size =
1209                         sizeof(struct pci_child_platdata),
1210 };
1211
1212 static const struct dm_pci_ops pci_bridge_ops = {
1213         .read_config    = pci_bridge_read_config,
1214         .write_config   = pci_bridge_write_config,
1215 };
1216
1217 static const struct udevice_id pci_bridge_ids[] = {
1218         { .compatible = "pci-bridge" },
1219         { }
1220 };
1221
1222 U_BOOT_DRIVER(pci_bridge_drv) = {
1223         .name           = "pci_bridge_drv",
1224         .id             = UCLASS_PCI,
1225         .of_match       = pci_bridge_ids,
1226         .ops            = &pci_bridge_ops,
1227 };
1228
1229 UCLASS_DRIVER(pci_generic) = {
1230         .id             = UCLASS_PCI_GENERIC,
1231         .name           = "pci_generic",
1232 };
1233
1234 static const struct udevice_id pci_generic_ids[] = {
1235         { .compatible = "pci-generic" },
1236         { }
1237 };
1238
1239 U_BOOT_DRIVER(pci_generic_drv) = {
1240         .name           = "pci_generic_drv",
1241         .id             = UCLASS_PCI_GENERIC,
1242         .of_match       = pci_generic_ids,
1243 };