2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
17 #include <dm/device-internal.h>
18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
19 #include <asm/fsp/fsp_support.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR
;
25 int pci_get_bus(int busnum
, struct udevice
**busp
)
29 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret
= uclass_first_device(UCLASS_PCI
, busp
);
38 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, busp
);
44 struct udevice
*pci_get_controller(struct udevice
*dev
)
46 while (device_is_on_pci_bus(dev
))
52 pci_dev_t
dm_pci_get_bdf(struct udevice
*dev
)
54 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
55 struct udevice
*bus
= dev
->parent
;
57 return PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
61 * pci_get_bus_max() - returns the bus number of the last active bus
63 * @return last bus number, or -1 if no active buses
65 static int pci_get_bus_max(void)
71 ret
= uclass_get(UCLASS_PCI
, &uc
);
72 uclass_foreach_dev(bus
, uc
) {
77 debug("%s: ret=%d\n", __func__
, ret
);
82 int pci_last_busno(void)
84 return pci_get_bus_max();
87 int pci_get_ff(enum pci_size_t size
)
99 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
100 struct udevice
**devp
)
104 for (device_find_first_child(bus
, &dev
);
106 device_find_next_child(&dev
)) {
107 struct pci_child_platdata
*pplat
;
109 pplat
= dev_get_parent_platdata(dev
);
110 if (pplat
&& pplat
->devfn
== find_devfn
) {
119 int dm_pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
124 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
127 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
130 static int pci_device_matches_ids(struct udevice
*dev
,
131 struct pci_device_id
*ids
)
133 struct pci_child_platdata
*pplat
;
136 pplat
= dev_get_parent_platdata(dev
);
139 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
140 if (pplat
->vendor
== ids
[i
].vendor
&&
141 pplat
->device
== ids
[i
].device
)
148 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
149 int *indexp
, struct udevice
**devp
)
153 /* Scan all devices on this bus */
154 for (device_find_first_child(bus
, &dev
);
156 device_find_next_child(&dev
)) {
157 if (pci_device_matches_ids(dev
, ids
) >= 0) {
158 if ((*indexp
)-- <= 0) {
168 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
169 struct udevice
**devp
)
173 /* Scan all known buses */
174 for (uclass_first_device(UCLASS_PCI
, &bus
);
176 uclass_next_device(&bus
)) {
177 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
185 static int dm_pci_bus_find_device(struct udevice
*bus
, unsigned int vendor
,
186 unsigned int device
, int *indexp
,
187 struct udevice
**devp
)
189 struct pci_child_platdata
*pplat
;
192 for (device_find_first_child(bus
, &dev
);
194 device_find_next_child(&dev
)) {
195 pplat
= dev_get_parent_platdata(dev
);
196 if (pplat
->vendor
== vendor
&& pplat
->device
== device
) {
207 int dm_pci_find_device(unsigned int vendor
, unsigned int device
, int index
,
208 struct udevice
**devp
)
212 /* Scan all known buses */
213 for (uclass_first_device(UCLASS_PCI
, &bus
);
215 uclass_next_device(&bus
)) {
216 if (!dm_pci_bus_find_device(bus
, vendor
, device
, &index
, devp
))
217 return device_probe(*devp
);
224 int dm_pci_find_class(uint find_class
, int index
, struct udevice
**devp
)
228 /* Scan all known buses */
229 for (pci_find_first_device(&dev
);
231 pci_find_next_device(&dev
)) {
232 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
234 if (pplat
->class == find_class
&& !index
--) {
236 return device_probe(*devp
);
244 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
245 unsigned long value
, enum pci_size_t size
)
247 struct dm_pci_ops
*ops
;
249 ops
= pci_get_ops(bus
);
250 if (!ops
->write_config
)
252 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
255 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
256 enum pci_size_t size
)
261 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
265 return pci_bus_write_config(bus
, bdf
, offset
, value
, size
);
268 int dm_pci_write_config(struct udevice
*dev
, int offset
, unsigned long value
,
269 enum pci_size_t size
)
273 for (bus
= dev
; device_is_on_pci_bus(bus
);)
275 return pci_bus_write_config(bus
, dm_pci_get_bdf(dev
), offset
, value
,
280 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
282 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
285 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
287 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
290 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
292 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
295 int dm_pci_write_config8(struct udevice
*dev
, int offset
, u8 value
)
297 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_8
);
300 int dm_pci_write_config16(struct udevice
*dev
, int offset
, u16 value
)
302 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_16
);
305 int dm_pci_write_config32(struct udevice
*dev
, int offset
, u32 value
)
307 return dm_pci_write_config(dev
, offset
, value
, PCI_SIZE_32
);
310 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
311 unsigned long *valuep
, enum pci_size_t size
)
313 struct dm_pci_ops
*ops
;
315 ops
= pci_get_ops(bus
);
316 if (!ops
->read_config
)
318 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
321 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
322 enum pci_size_t size
)
327 ret
= pci_get_bus(PCI_BUS(bdf
), &bus
);
331 return pci_bus_read_config(bus
, bdf
, offset
, valuep
, size
);
334 int dm_pci_read_config(struct udevice
*dev
, int offset
, unsigned long *valuep
,
335 enum pci_size_t size
)
339 for (bus
= dev
; device_is_on_pci_bus(bus
);)
341 return pci_bus_read_config(bus
, dm_pci_get_bdf(dev
), offset
, valuep
,
345 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
350 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
358 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
363 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
371 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
376 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
384 int dm_pci_read_config8(struct udevice
*dev
, int offset
, u8
*valuep
)
389 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_8
);
397 int dm_pci_read_config16(struct udevice
*dev
, int offset
, u16
*valuep
)
402 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_16
);
410 int dm_pci_read_config32(struct udevice
*dev
, int offset
, u32
*valuep
)
415 ret
= dm_pci_read_config(dev
, offset
, &value
, PCI_SIZE_32
);
423 static void set_vga_bridge_bits(struct udevice
*dev
)
425 struct udevice
*parent
= dev
->parent
;
428 while (parent
->seq
!= 0) {
429 dm_pci_read_config16(parent
, PCI_BRIDGE_CONTROL
, &bc
);
430 bc
|= PCI_BRIDGE_CTL_VGA
;
431 dm_pci_write_config16(parent
, PCI_BRIDGE_CONTROL
, bc
);
432 parent
= parent
->parent
;
436 int pci_auto_config_devices(struct udevice
*bus
)
438 struct pci_controller
*hose
= bus
->uclass_priv
;
439 struct pci_child_platdata
*pplat
;
440 unsigned int sub_bus
;
445 debug("%s: start\n", __func__
);
446 pciauto_config_init(hose
);
447 for (ret
= device_find_first_child(bus
, &dev
);
449 ret
= device_find_next_child(&dev
)) {
450 unsigned int max_bus
;
453 debug("%s: device %s\n", __func__
, dev
->name
);
454 ret
= dm_pciauto_config_device(dev
);
458 sub_bus
= max(sub_bus
, max_bus
);
460 pplat
= dev_get_parent_platdata(dev
);
461 if (pplat
->class == (PCI_CLASS_DISPLAY_VGA
<< 8))
462 set_vga_bridge_bits(dev
);
464 debug("%s: done\n", __func__
);
469 int dm_pci_hose_probe_bus(struct udevice
*bus
)
474 debug("%s\n", __func__
);
476 sub_bus
= pci_get_bus_max() + 1;
477 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
478 dm_pciauto_prescan_setup_bridge(bus
, sub_bus
);
480 ret
= device_probe(bus
);
482 debug("%s: Cannot probe bus %s: %d\n", __func__
, bus
->name
,
486 if (sub_bus
!= bus
->seq
) {
487 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
488 __func__
, bus
->name
, bus
->seq
, sub_bus
);
491 sub_bus
= pci_get_bus_max();
492 dm_pciauto_postscan_setup_bridge(bus
, sub_bus
);
498 * pci_match_one_device - Tell if a PCI device structure has a matching
499 * PCI device id structure
500 * @id: single PCI device id structure to match
501 * @dev: the PCI device structure to match against
503 * Returns the matching pci_device_id structure or %NULL if there is no match.
505 static bool pci_match_one_id(const struct pci_device_id
*id
,
506 const struct pci_device_id
*find
)
508 if ((id
->vendor
== PCI_ANY_ID
|| id
->vendor
== find
->vendor
) &&
509 (id
->device
== PCI_ANY_ID
|| id
->device
== find
->device
) &&
510 (id
->subvendor
== PCI_ANY_ID
|| id
->subvendor
== find
->subvendor
) &&
511 (id
->subdevice
== PCI_ANY_ID
|| id
->subdevice
== find
->subdevice
) &&
512 !((id
->class ^ find
->class) & id
->class_mask
))
519 * pci_find_and_bind_driver() - Find and bind the right PCI driver
521 * This only looks at certain fields in the descriptor.
523 * @parent: Parent bus
524 * @find_id: Specification of the driver to find
525 * @bdf: Bus/device/function addreess - see PCI_BDF()
526 * @devp: Returns a pointer to the device created
527 * @return 0 if OK, -EPERM if the device is not needed before relocation and
528 * therefore was not created, other -ve value on error
530 static int pci_find_and_bind_driver(struct udevice
*parent
,
531 struct pci_device_id
*find_id
,
532 pci_dev_t bdf
, struct udevice
**devp
)
534 struct pci_driver_entry
*start
, *entry
;
543 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__
,
544 find_id
->vendor
, find_id
->device
);
545 start
= ll_entry_start(struct pci_driver_entry
, pci_driver_entry
);
546 n_ents
= ll_entry_count(struct pci_driver_entry
, pci_driver_entry
);
547 for (entry
= start
; entry
!= start
+ n_ents
; entry
++) {
548 const struct pci_device_id
*id
;
550 const struct driver
*drv
;
552 for (id
= entry
->match
;
553 id
->vendor
|| id
->subvendor
|| id
->class_mask
;
555 if (!pci_match_one_id(id
, find_id
))
561 * In the pre-relocation phase, we only bind devices
562 * whose driver has the DM_FLAG_PRE_RELOC set, to save
563 * precious memory space as on some platforms as that
564 * space is pretty limited (ie: using Cache As RAM).
566 if (!(gd
->flags
& GD_FLG_RELOC
) &&
567 !(drv
->flags
& DM_FLAG_PRE_RELOC
))
571 * We could pass the descriptor to the driver as
572 * platdata (instead of NULL) and allow its bind()
573 * method to return -ENOENT if it doesn't support this
574 * device. That way we could continue the search to
575 * find another driver. For now this doesn't seem
576 * necesssary, so just bind the first match.
578 ret
= device_bind(parent
, drv
, drv
->name
, NULL
, -1,
582 debug("%s: Match found: %s\n", __func__
, drv
->name
);
583 dev
->driver_data
= find_id
->driver_data
;
589 bridge
= (find_id
->class >> 8) == PCI_CLASS_BRIDGE_PCI
;
591 * In the pre-relocation phase, we only bind bridge devices to save
592 * precious memory space as on some platforms as that space is pretty
593 * limited (ie: using Cache As RAM).
595 if (!(gd
->flags
& GD_FLG_RELOC
) && !bridge
)
598 /* Bind a generic driver so that the device can be used */
599 sprintf(name
, "pci_%x:%x.%x", parent
->seq
, PCI_DEV(bdf
),
604 drv
= bridge
? "pci_bridge_drv" : "pci_generic_drv";
606 ret
= device_bind_driver(parent
, drv
, str
, devp
);
608 debug("%s: Failed to bind generic driver: %d\n", __func__
, ret
);
611 debug("%s: No match found: bound generic driver instead\n", __func__
);
616 debug("%s: No match found: error %d\n", __func__
, ret
);
620 int pci_bind_bus_devices(struct udevice
*bus
)
622 ulong vendor
, device
;
629 end
= PCI_BDF(bus
->seq
, PCI_MAX_PCI_DEVICES
- 1,
630 PCI_MAX_PCI_FUNCTIONS
- 1);
631 for (bdf
= PCI_BDF(bus
->seq
, 0, 0); bdf
< end
;
632 bdf
+= PCI_BDF(0, 0, 1)) {
633 struct pci_child_platdata
*pplat
;
637 if (PCI_FUNC(bdf
) && !found_multi
)
639 /* Check only the first access, we don't expect problems */
640 ret
= pci_bus_read_config(bus
, bdf
, PCI_HEADER_TYPE
,
641 &header_type
, PCI_SIZE_8
);
644 pci_bus_read_config(bus
, bdf
, PCI_VENDOR_ID
, &vendor
,
646 if (vendor
== 0xffff || vendor
== 0x0000)
650 found_multi
= header_type
& 0x80;
652 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
653 bus
->seq
, bus
->name
, PCI_DEV(bdf
), PCI_FUNC(bdf
));
654 pci_bus_read_config(bus
, bdf
, PCI_DEVICE_ID
, &device
,
656 pci_bus_read_config(bus
, bdf
, PCI_CLASS_REVISION
, &class,
660 /* Find this device in the device tree */
661 ret
= pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), &dev
);
663 /* If nothing in the device tree, bind a device */
664 if (ret
== -ENODEV
) {
665 struct pci_device_id find_id
;
668 memset(&find_id
, '\0', sizeof(find_id
));
669 find_id
.vendor
= vendor
;
670 find_id
.device
= device
;
671 find_id
.class = class;
672 if ((header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
) {
673 pci_bus_read_config(bus
, bdf
,
674 PCI_SUBSYSTEM_VENDOR_ID
,
676 find_id
.subvendor
= val
& 0xffff;
677 find_id
.subdevice
= val
>> 16;
679 ret
= pci_find_and_bind_driver(bus
, &find_id
, bdf
,
687 /* Update the platform data */
688 pplat
= dev_get_parent_platdata(dev
);
689 pplat
->devfn
= PCI_MASK_BUS(bdf
);
690 pplat
->vendor
= vendor
;
691 pplat
->device
= device
;
692 pplat
->class = class;
697 printf("Cannot read bus configuration: %d\n", ret
);
702 static int pci_uclass_post_bind(struct udevice
*bus
)
705 * If there is no pci device listed in the device tree,
706 * don't bother scanning the device tree.
708 if (bus
->of_offset
== -1)
712 * Scan the device tree for devices. This does not probe the PCI bus,
713 * as this is not permitted while binding. It just finds devices
714 * mentioned in the device tree.
716 * Before relocation, only bind devices marked for pre-relocation
719 return dm_scan_fdt_node(bus
, gd
->fdt_blob
, bus
->of_offset
,
720 gd
->flags
& GD_FLG_RELOC
? false : true);
723 static int decode_regions(struct pci_controller
*hose
, const void *blob
,
724 int parent_node
, int node
)
726 int pci_addr_cells
, addr_cells
, size_cells
;
727 phys_addr_t base
= 0, size
;
728 int cells_per_record
;
733 prop
= fdt_getprop(blob
, node
, "ranges", &len
);
736 pci_addr_cells
= fdt_address_cells(blob
, node
);
737 addr_cells
= fdt_address_cells(blob
, parent_node
);
738 size_cells
= fdt_size_cells(blob
, node
);
740 /* PCI addresses are always 3-cells */
742 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
743 hose
->region_count
= 0;
744 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
746 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
747 u64 pci_addr
, addr
, size
;
753 if (len
< cells_per_record
)
755 flags
= fdt32_to_cpu(prop
[0]);
756 space_code
= (flags
>> 24) & 3;
757 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
758 prop
+= pci_addr_cells
;
759 addr
= fdtdec_get_number(prop
, addr_cells
);
761 size
= fdtdec_get_number(prop
, size_cells
);
763 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
764 ", size=%" PRIx64
", space_code=%d\n", __func__
,
765 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
766 if (space_code
& 2) {
767 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
769 } else if (space_code
& 1) {
770 type
= PCI_REGION_IO
;
775 for (i
= 0; i
< hose
->region_count
; i
++) {
776 if (hose
->regions
[i
].flags
== type
)
780 pos
= hose
->region_count
++;
781 debug(" - type=%d, pos=%d\n", type
, pos
);
782 pci_set_region(hose
->regions
+ pos
, pci_addr
, addr
, size
, type
);
785 /* Add a region for our local memory */
787 #ifdef CONFIG_SYS_SDRAM_BASE
788 base
= CONFIG_SYS_SDRAM_BASE
;
790 if (gd
->pci_ram_top
&& gd
->pci_ram_top
< base
+ size
)
791 size
= gd
->pci_ram_top
- base
;
792 pci_set_region(hose
->regions
+ hose
->region_count
++, base
, base
,
793 size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
798 static int pci_uclass_pre_probe(struct udevice
*bus
)
800 struct pci_controller
*hose
;
803 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
805 hose
= bus
->uclass_priv
;
807 /* For bridges, use the top-level PCI controller */
808 if (device_get_uclass_id(bus
->parent
) == UCLASS_ROOT
) {
810 ret
= decode_regions(hose
, gd
->fdt_blob
, bus
->parent
->of_offset
,
813 debug("%s: Cannot decode regions\n", __func__
);
817 struct pci_controller
*parent_hose
;
819 parent_hose
= dev_get_uclass_priv(bus
->parent
);
820 hose
->ctlr
= parent_hose
->bus
;
823 hose
->first_busno
= bus
->seq
;
824 hose
->last_busno
= bus
->seq
;
829 static int pci_uclass_post_probe(struct udevice
*bus
)
833 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
834 ret
= pci_bind_bus_devices(bus
);
838 #ifdef CONFIG_PCI_PNP
839 ret
= pci_auto_config_devices(bus
);
844 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
846 * Per Intel FSP specification, we should call FSP notify API to
847 * inform FSP that PCI enumeration has been done so that FSP will
848 * do any necessary initialization as required by the chipset's
849 * BIOS Writer's Guide (BWG).
851 * Unfortunately we have to put this call here as with driver model,
852 * the enumeration is all done on a lazy basis as needed, so until
853 * something is touched on PCI it won't happen.
855 * Note we only call this 1) after U-Boot is relocated, and 2)
856 * root bus has finished probing.
858 if ((gd
->flags
& GD_FLG_RELOC
) && (bus
->seq
== 0)) {
859 ret
= fsp_init_phase_pci();
868 static int pci_uclass_child_post_bind(struct udevice
*dev
)
870 struct pci_child_platdata
*pplat
;
871 struct fdt_pci_addr addr
;
874 if (dev
->of_offset
== -1)
878 * We could read vendor, device, class if available. But for now we
879 * just check the address.
881 pplat
= dev_get_parent_platdata(dev
);
882 ret
= fdtdec_get_pci_addr(gd
->fdt_blob
, dev
->of_offset
,
883 FDT_PCI_SPACE_CONFIG
, "reg", &addr
);
889 /* extract the devfn from fdt_pci_addr */
890 pplat
->devfn
= addr
.phys_hi
& 0xff00;
896 static int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t bdf
,
897 uint offset
, ulong
*valuep
,
898 enum pci_size_t size
)
900 struct pci_controller
*hose
= bus
->uclass_priv
;
902 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
905 static int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t bdf
,
906 uint offset
, ulong value
,
907 enum pci_size_t size
)
909 struct pci_controller
*hose
= bus
->uclass_priv
;
911 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
914 static int skip_to_next_device(struct udevice
*bus
, struct udevice
**devp
)
920 * Scan through all the PCI controllers. On x86 there will only be one
921 * but that is not necessarily true on other hardware.
924 device_find_first_child(bus
, &dev
);
929 ret
= uclass_next_device(&bus
);
937 int pci_find_next_device(struct udevice
**devp
)
939 struct udevice
*child
= *devp
;
940 struct udevice
*bus
= child
->parent
;
943 /* First try all the siblings */
946 device_find_next_child(&child
);
953 /* We ran out of siblings. Try the next bus */
954 ret
= uclass_next_device(&bus
);
958 return bus
? skip_to_next_device(bus
, devp
) : 0;
961 int pci_find_first_device(struct udevice
**devp
)
967 ret
= uclass_first_device(UCLASS_PCI
, &bus
);
971 return skip_to_next_device(bus
, devp
);
974 ulong
pci_conv_32_to_size(ulong value
, uint offset
, enum pci_size_t size
)
978 return (value
>> ((offset
& 3) * 8)) & 0xff;
980 return (value
>> ((offset
& 2) * 8)) & 0xffff;
986 ulong
pci_conv_size_to_32(ulong old
, ulong value
, uint offset
,
987 enum pci_size_t size
)
990 uint val_mask
, shift
;
1005 shift
= (offset
& off_mask
) * 8;
1006 ldata
= (value
& val_mask
) << shift
;
1007 mask
= val_mask
<< shift
;
1008 value
= (old
& ~mask
) | ldata
;
1013 int pci_get_regions(struct udevice
*dev
, struct pci_region
**iop
,
1014 struct pci_region
**memp
, struct pci_region
**prefp
)
1016 struct udevice
*bus
= pci_get_controller(dev
);
1017 struct pci_controller
*hose
= dev_get_uclass_priv(bus
);
1023 for (i
= 0; i
< hose
->region_count
; i
++) {
1024 switch (hose
->regions
[i
].flags
) {
1026 if (!*iop
|| (*iop
)->size
< hose
->regions
[i
].size
)
1027 *iop
= hose
->regions
+ i
;
1029 case PCI_REGION_MEM
:
1030 if (!*memp
|| (*memp
)->size
< hose
->regions
[i
].size
)
1031 *memp
= hose
->regions
+ i
;
1033 case (PCI_REGION_MEM
| PCI_REGION_PREFETCH
):
1034 if (!*prefp
|| (*prefp
)->size
< hose
->regions
[i
].size
)
1035 *prefp
= hose
->regions
+ i
;
1040 return (*iop
!= NULL
) + (*memp
!= NULL
) + (*prefp
!= NULL
);
1043 u32
dm_pci_read_bar32(struct udevice
*dev
, int barnum
)
1048 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1049 dm_pci_read_config32(dev
, bar
, &addr
);
1050 if (addr
& PCI_BASE_ADDRESS_SPACE_IO
)
1051 return addr
& PCI_BASE_ADDRESS_IO_MASK
;
1053 return addr
& PCI_BASE_ADDRESS_MEM_MASK
;
1056 void dm_pci_write_bar32(struct udevice
*dev
, int barnum
, u32 addr
)
1060 bar
= PCI_BASE_ADDRESS_0
+ barnum
* 4;
1061 dm_pci_write_config32(dev
, bar
, addr
);
1064 static int _dm_pci_bus_to_phys(struct udevice
*ctlr
,
1065 pci_addr_t bus_addr
, unsigned long flags
,
1066 unsigned long skip_mask
, phys_addr_t
*pa
)
1068 struct pci_controller
*hose
= dev_get_uclass_priv(ctlr
);
1069 struct pci_region
*res
;
1072 for (i
= 0; i
< hose
->region_count
; i
++) {
1073 res
= &hose
->regions
[i
];
1075 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1078 if (res
->flags
& skip_mask
)
1081 if (bus_addr
>= res
->bus_start
&&
1082 (bus_addr
- res
->bus_start
) < res
->size
) {
1083 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
1091 phys_addr_t
dm_pci_bus_to_phys(struct udevice
*dev
, pci_addr_t bus_addr
,
1092 unsigned long flags
)
1094 phys_addr_t phys_addr
= 0;
1095 struct udevice
*ctlr
;
1098 /* The root controller has the region information */
1099 ctlr
= pci_get_controller(dev
);
1102 * if PCI_REGION_MEM is set we do a two pass search with preference
1103 * on matches that don't have PCI_REGION_SYS_MEMORY set
1105 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1106 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
,
1107 flags
, PCI_REGION_SYS_MEMORY
,
1113 ret
= _dm_pci_bus_to_phys(ctlr
, bus_addr
, flags
, 0, &phys_addr
);
1116 puts("pci_hose_bus_to_phys: invalid physical address\n");
1121 int _dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1122 unsigned long flags
, unsigned long skip_mask
,
1125 struct pci_region
*res
;
1126 struct udevice
*ctlr
;
1127 pci_addr_t bus_addr
;
1129 struct pci_controller
*hose
;
1131 /* The root controller has the region information */
1132 ctlr
= pci_get_controller(dev
);
1133 hose
= dev_get_uclass_priv(ctlr
);
1135 for (i
= 0; i
< hose
->region_count
; i
++) {
1136 res
= &hose
->regions
[i
];
1138 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
1141 if (res
->flags
& skip_mask
)
1144 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
1146 if (bus_addr
>= res
->bus_start
&&
1147 (bus_addr
- res
->bus_start
) < res
->size
) {
1156 pci_addr_t
dm_pci_phys_to_bus(struct udevice
*dev
, phys_addr_t phys_addr
,
1157 unsigned long flags
)
1159 pci_addr_t bus_addr
= 0;
1163 * if PCI_REGION_MEM is set we do a two pass search with preference
1164 * on matches that don't have PCI_REGION_SYS_MEMORY set
1166 if ((flags
& PCI_REGION_TYPE
) == PCI_REGION_MEM
) {
1167 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
,
1168 PCI_REGION_SYS_MEMORY
, &bus_addr
);
1173 ret
= _dm_pci_phys_to_bus(dev
, phys_addr
, flags
, 0, &bus_addr
);
1176 puts("pci_hose_phys_to_bus: invalid physical address\n");
1181 void *dm_pci_map_bar(struct udevice
*dev
, int bar
, int flags
)
1183 pci_addr_t pci_bus_addr
;
1186 /* read BAR address */
1187 dm_pci_read_config32(dev
, bar
, &bar_response
);
1188 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
1191 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1192 * isn't actualy used on any platform because u-boot assumes a static
1193 * linear mapping. In the future, this could read the BAR size
1194 * and pass that as the size if needed.
1196 return dm_pci_bus_to_virt(dev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
1199 UCLASS_DRIVER(pci
) = {
1202 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
1203 .post_bind
= pci_uclass_post_bind
,
1204 .pre_probe
= pci_uclass_pre_probe
,
1205 .post_probe
= pci_uclass_post_probe
,
1206 .child_post_bind
= pci_uclass_child_post_bind
,
1207 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
1208 .per_child_platdata_auto_alloc_size
=
1209 sizeof(struct pci_child_platdata
),
1212 static const struct dm_pci_ops pci_bridge_ops
= {
1213 .read_config
= pci_bridge_read_config
,
1214 .write_config
= pci_bridge_write_config
,
1217 static const struct udevice_id pci_bridge_ids
[] = {
1218 { .compatible
= "pci-bridge" },
1222 U_BOOT_DRIVER(pci_bridge_drv
) = {
1223 .name
= "pci_bridge_drv",
1225 .of_match
= pci_bridge_ids
,
1226 .ops
= &pci_bridge_ops
,
1229 UCLASS_DRIVER(pci_generic
) = {
1230 .id
= UCLASS_PCI_GENERIC
,
1231 .name
= "pci_generic",
1234 static const struct udevice_id pci_generic_ids
[] = {
1235 { .compatible
= "pci-generic" },
1239 U_BOOT_DRIVER(pci_generic_drv
) = {
1240 .name
= "pci_generic_drv",
1241 .id
= UCLASS_PCI_GENERIC
,
1242 .of_match
= pci_generic_ids
,