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dm: pci: Allow scan bridge child devices before relocation
[people/ms/u-boot.git] / drivers / pci / pci-uclass.c
1 /*
2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <errno.h>
11 #include <fdtdec.h>
12 #include <inttypes.h>
13 #include <pci.h>
14 #include <dm/lists.h>
15 #include <dm/root.h>
16 #include <dm/device-internal.h>
17
18 DECLARE_GLOBAL_DATA_PTR;
19
20 struct pci_controller *pci_bus_to_hose(int busnum)
21 {
22 struct udevice *bus;
23 int ret;
24
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
26 if (ret) {
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__, busnum, ret);
28 return NULL;
29 }
30 return dev_get_uclass_priv(bus);
31 }
32
33 pci_dev_t pci_get_bdf(struct udevice *dev)
34 {
35 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
36 struct udevice *bus = dev->parent;
37
38 return PCI_ADD_BUS(bus->seq, pplat->devfn);
39 }
40
41 /**
42 * pci_get_bus_max() - returns the bus number of the last active bus
43 *
44 * @return last bus number, or -1 if no active buses
45 */
46 static int pci_get_bus_max(void)
47 {
48 struct udevice *bus;
49 struct uclass *uc;
50 int ret = -1;
51
52 ret = uclass_get(UCLASS_PCI, &uc);
53 uclass_foreach_dev(bus, uc) {
54 if (bus->seq > ret)
55 ret = bus->seq;
56 }
57
58 debug("%s: ret=%d\n", __func__, ret);
59
60 return ret;
61 }
62
63 int pci_last_busno(void)
64 {
65 struct pci_controller *hose;
66 struct udevice *bus;
67 struct uclass *uc;
68 int ret;
69
70 debug("pci_last_busno\n");
71 ret = uclass_get(UCLASS_PCI, &uc);
72 if (ret || list_empty(&uc->dev_head))
73 return -1;
74
75 /* Probe the last bus */
76 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
77 debug("bus = %p, %s\n", bus, bus->name);
78 assert(bus);
79 ret = device_probe(bus);
80 if (ret)
81 return ret;
82
83 /* If that bus has bridges, we may have new buses now. Get the last */
84 bus = list_entry(uc->dev_head.prev, struct udevice, uclass_node);
85 hose = dev_get_uclass_priv(bus);
86 debug("bus = %s, hose = %p\n", bus->name, hose);
87
88 return hose->last_busno;
89 }
90
91 int pci_get_ff(enum pci_size_t size)
92 {
93 switch (size) {
94 case PCI_SIZE_8:
95 return 0xff;
96 case PCI_SIZE_16:
97 return 0xffff;
98 default:
99 return 0xffffffff;
100 }
101 }
102
103 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
104 struct udevice **devp)
105 {
106 struct udevice *dev;
107
108 for (device_find_first_child(bus, &dev);
109 dev;
110 device_find_next_child(&dev)) {
111 struct pci_child_platdata *pplat;
112
113 pplat = dev_get_parent_platdata(dev);
114 if (pplat && pplat->devfn == find_devfn) {
115 *devp = dev;
116 return 0;
117 }
118 }
119
120 return -ENODEV;
121 }
122
123 int pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
124 {
125 struct udevice *bus;
126 int ret;
127
128 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
129 if (ret)
130 return ret;
131 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
132 }
133
134 static int pci_device_matches_ids(struct udevice *dev,
135 struct pci_device_id *ids)
136 {
137 struct pci_child_platdata *pplat;
138 int i;
139
140 pplat = dev_get_parent_platdata(dev);
141 if (!pplat)
142 return -EINVAL;
143 for (i = 0; ids[i].vendor != 0; i++) {
144 if (pplat->vendor == ids[i].vendor &&
145 pplat->device == ids[i].device)
146 return i;
147 }
148
149 return -EINVAL;
150 }
151
152 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
153 int *indexp, struct udevice **devp)
154 {
155 struct udevice *dev;
156
157 /* Scan all devices on this bus */
158 for (device_find_first_child(bus, &dev);
159 dev;
160 device_find_next_child(&dev)) {
161 if (pci_device_matches_ids(dev, ids) >= 0) {
162 if ((*indexp)-- <= 0) {
163 *devp = dev;
164 return 0;
165 }
166 }
167 }
168
169 return -ENODEV;
170 }
171
172 int pci_find_device_id(struct pci_device_id *ids, int index,
173 struct udevice **devp)
174 {
175 struct udevice *bus;
176
177 /* Scan all known buses */
178 for (uclass_first_device(UCLASS_PCI, &bus);
179 bus;
180 uclass_next_device(&bus)) {
181 if (!pci_bus_find_devices(bus, ids, &index, devp))
182 return 0;
183 }
184 *devp = NULL;
185
186 return -ENODEV;
187 }
188
189 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
190 unsigned long value, enum pci_size_t size)
191 {
192 struct dm_pci_ops *ops;
193
194 ops = pci_get_ops(bus);
195 if (!ops->write_config)
196 return -ENOSYS;
197 return ops->write_config(bus, bdf, offset, value, size);
198 }
199
200 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
201 enum pci_size_t size)
202 {
203 struct udevice *bus;
204 int ret;
205
206 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
207 if (ret)
208 return ret;
209
210 return pci_bus_write_config(bus, bdf, offset, value, size);
211 }
212
213 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
214 {
215 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
216 }
217
218 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
219 {
220 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
221 }
222
223 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
224 {
225 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
226 }
227
228 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
229 unsigned long *valuep, enum pci_size_t size)
230 {
231 struct dm_pci_ops *ops;
232
233 ops = pci_get_ops(bus);
234 if (!ops->read_config)
235 return -ENOSYS;
236 return ops->read_config(bus, bdf, offset, valuep, size);
237 }
238
239 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
240 enum pci_size_t size)
241 {
242 struct udevice *bus;
243 int ret;
244
245 ret = uclass_get_device_by_seq(UCLASS_PCI, PCI_BUS(bdf), &bus);
246 if (ret)
247 return ret;
248
249 return pci_bus_read_config(bus, bdf, offset, valuep, size);
250 }
251
252 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
253 {
254 unsigned long value;
255 int ret;
256
257 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
258 if (ret)
259 return ret;
260 *valuep = value;
261
262 return 0;
263 }
264
265 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
266 {
267 unsigned long value;
268 int ret;
269
270 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
271 if (ret)
272 return ret;
273 *valuep = value;
274
275 return 0;
276 }
277
278 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
279 {
280 unsigned long value;
281 int ret;
282
283 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
284 if (ret)
285 return ret;
286 *valuep = value;
287
288 return 0;
289 }
290
291 int pci_auto_config_devices(struct udevice *bus)
292 {
293 struct pci_controller *hose = bus->uclass_priv;
294 unsigned int sub_bus;
295 struct udevice *dev;
296 int ret;
297
298 sub_bus = bus->seq;
299 debug("%s: start\n", __func__);
300 pciauto_config_init(hose);
301 for (ret = device_find_first_child(bus, &dev);
302 !ret && dev;
303 ret = device_find_next_child(&dev)) {
304 unsigned int max_bus;
305
306 debug("%s: device %s\n", __func__, dev->name);
307 max_bus = pciauto_config_device(hose, pci_get_bdf(dev));
308 sub_bus = max(sub_bus, max_bus);
309 }
310 debug("%s: done\n", __func__);
311
312 return sub_bus;
313 }
314
315 int dm_pci_hose_probe_bus(struct pci_controller *hose, pci_dev_t bdf)
316 {
317 struct udevice *parent, *bus;
318 int sub_bus;
319 int ret;
320
321 debug("%s\n", __func__);
322 parent = hose->bus;
323
324 /* Find the bus within the parent */
325 ret = pci_bus_find_devfn(parent, PCI_MASK_BUS(bdf), &bus);
326 if (ret) {
327 debug("%s: Cannot find device %x on bus %s: %d\n", __func__,
328 bdf, parent->name, ret);
329 return ret;
330 }
331
332 sub_bus = pci_get_bus_max() + 1;
333 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
334 pciauto_prescan_setup_bridge(hose, bdf, sub_bus);
335
336 ret = device_probe(bus);
337 if (ret) {
338 debug("%s: Cannot probe bus bus %s: %d\n", __func__, bus->name,
339 ret);
340 return ret;
341 }
342 if (sub_bus != bus->seq) {
343 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
344 __func__, bus->name, bus->seq, sub_bus);
345 return -EPIPE;
346 }
347 sub_bus = pci_get_bus_max();
348 pciauto_postscan_setup_bridge(hose, bdf, sub_bus);
349
350 return sub_bus;
351 }
352
353 /**
354 * pci_match_one_device - Tell if a PCI device structure has a matching
355 * PCI device id structure
356 * @id: single PCI device id structure to match
357 * @dev: the PCI device structure to match against
358 *
359 * Returns the matching pci_device_id structure or %NULL if there is no match.
360 */
361 static bool pci_match_one_id(const struct pci_device_id *id,
362 const struct pci_device_id *find)
363 {
364 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
365 (id->device == PCI_ANY_ID || id->device == find->device) &&
366 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
367 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
368 !((id->class ^ find->class) & id->class_mask))
369 return true;
370
371 return false;
372 }
373
374 /**
375 * pci_find_and_bind_driver() - Find and bind the right PCI driver
376 *
377 * This only looks at certain fields in the descriptor.
378 */
379 static int pci_find_and_bind_driver(struct udevice *parent,
380 struct pci_device_id *find_id, pci_dev_t bdf,
381 struct udevice **devp)
382 {
383 struct pci_driver_entry *start, *entry;
384 const char *drv;
385 int n_ents;
386 int ret;
387 char name[30], *str;
388
389 *devp = NULL;
390
391 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
392 find_id->vendor, find_id->device);
393 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
394 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
395 for (entry = start; entry != start + n_ents; entry++) {
396 const struct pci_device_id *id;
397 struct udevice *dev;
398 const struct driver *drv;
399
400 for (id = entry->match;
401 id->vendor || id->subvendor || id->class_mask;
402 id++) {
403 if (!pci_match_one_id(id, find_id))
404 continue;
405
406 drv = entry->driver;
407 /*
408 * We could pass the descriptor to the driver as
409 * platdata (instead of NULL) and allow its bind()
410 * method to return -ENOENT if it doesn't support this
411 * device. That way we could continue the search to
412 * find another driver. For now this doesn't seem
413 * necesssary, so just bind the first match.
414 */
415 ret = device_bind(parent, drv, drv->name, NULL, -1,
416 &dev);
417 if (ret)
418 goto error;
419 debug("%s: Match found: %s\n", __func__, drv->name);
420 dev->driver_data = find_id->driver_data;
421 *devp = dev;
422 return 0;
423 }
424 }
425
426 /* Bind a generic driver so that the device can be used */
427 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
428 PCI_FUNC(bdf));
429 str = strdup(name);
430 if (!str)
431 return -ENOMEM;
432 drv = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI ? "pci_bridge_drv" :
433 "pci_generic_drv";
434 ret = device_bind_driver(parent, drv, str, devp);
435 if (ret) {
436 debug("%s: Failed to bind generic driver: %d", __func__, ret);
437 return ret;
438 }
439 debug("%s: No match found: bound generic driver instead\n", __func__);
440
441 return 0;
442
443 error:
444 debug("%s: No match found: error %d\n", __func__, ret);
445 return ret;
446 }
447
448 int pci_bind_bus_devices(struct udevice *bus)
449 {
450 ulong vendor, device;
451 ulong header_type;
452 pci_dev_t bdf, end;
453 bool found_multi;
454 int ret;
455
456 found_multi = false;
457 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
458 PCI_MAX_PCI_FUNCTIONS - 1);
459 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf < end;
460 bdf += PCI_BDF(0, 0, 1)) {
461 struct pci_child_platdata *pplat;
462 struct udevice *dev;
463 ulong class;
464
465 if (PCI_FUNC(bdf) && !found_multi)
466 continue;
467 /* Check only the first access, we don't expect problems */
468 ret = pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
469 &header_type, PCI_SIZE_8);
470 if (ret)
471 goto error;
472 pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
473 PCI_SIZE_16);
474 if (vendor == 0xffff || vendor == 0x0000)
475 continue;
476
477 if (!PCI_FUNC(bdf))
478 found_multi = header_type & 0x80;
479
480 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
481 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
482 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
483 PCI_SIZE_16);
484 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
485 PCI_SIZE_32);
486 class >>= 8;
487
488 /* Find this device in the device tree */
489 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
490
491 /* Search for a driver */
492
493 /* If nothing in the device tree, bind a generic device */
494 if (ret == -ENODEV) {
495 struct pci_device_id find_id;
496 ulong val;
497
498 memset(&find_id, '\0', sizeof(find_id));
499 find_id.vendor = vendor;
500 find_id.device = device;
501 find_id.class = class;
502 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
503 pci_bus_read_config(bus, bdf,
504 PCI_SUBSYSTEM_VENDOR_ID,
505 &val, PCI_SIZE_32);
506 find_id.subvendor = val & 0xffff;
507 find_id.subdevice = val >> 16;
508 }
509 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
510 &dev);
511 }
512 if (ret)
513 return ret;
514
515 /* Update the platform data */
516 pplat = dev_get_parent_platdata(dev);
517 pplat->devfn = PCI_MASK_BUS(bdf);
518 pplat->vendor = vendor;
519 pplat->device = device;
520 pplat->class = class;
521 }
522
523 return 0;
524 error:
525 printf("Cannot read bus configuration: %d\n", ret);
526
527 return ret;
528 }
529
530 static int pci_uclass_post_bind(struct udevice *bus)
531 {
532 /*
533 * Scan the device tree for devices. This does not probe the PCI bus,
534 * as this is not permitted while binding. It just finds devices
535 * mentioned in the device tree.
536 *
537 * Before relocation, only bind devices marked for pre-relocation
538 * use.
539 */
540 return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset,
541 gd->flags & GD_FLG_RELOC ? false : true);
542 }
543
544 static int decode_regions(struct pci_controller *hose, const void *blob,
545 int parent_node, int node)
546 {
547 int pci_addr_cells, addr_cells, size_cells;
548 int cells_per_record;
549 phys_addr_t addr;
550 const u32 *prop;
551 int len;
552 int i;
553
554 prop = fdt_getprop(blob, node, "ranges", &len);
555 if (!prop)
556 return -EINVAL;
557 pci_addr_cells = fdt_address_cells(blob, node);
558 addr_cells = fdt_address_cells(blob, parent_node);
559 size_cells = fdt_size_cells(blob, node);
560
561 /* PCI addresses are always 3-cells */
562 len /= sizeof(u32);
563 cells_per_record = pci_addr_cells + addr_cells + size_cells;
564 hose->region_count = 0;
565 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
566 cells_per_record);
567 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
568 u64 pci_addr, addr, size;
569 int space_code;
570 u32 flags;
571 int type;
572
573 if (len < cells_per_record)
574 break;
575 flags = fdt32_to_cpu(prop[0]);
576 space_code = (flags >> 24) & 3;
577 pci_addr = fdtdec_get_number(prop + 1, 2);
578 prop += pci_addr_cells;
579 addr = fdtdec_get_number(prop, addr_cells);
580 prop += addr_cells;
581 size = fdtdec_get_number(prop, size_cells);
582 prop += size_cells;
583 debug("%s: region %d, pci_addr=%" PRIx64 ", addr=%" PRIx64
584 ", size=%" PRIx64 ", space_code=%d\n", __func__,
585 hose->region_count, pci_addr, addr, size, space_code);
586 if (space_code & 2) {
587 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
588 PCI_REGION_MEM;
589 } else if (space_code & 1) {
590 type = PCI_REGION_IO;
591 } else {
592 continue;
593 }
594 debug(" - type=%d\n", type);
595 pci_set_region(hose->regions + hose->region_count++, pci_addr,
596 addr, size, type);
597 }
598
599 /* Add a region for our local memory */
600 addr = gd->ram_size;
601 if (gd->pci_ram_top && gd->pci_ram_top < addr)
602 addr = gd->pci_ram_top;
603 pci_set_region(hose->regions + hose->region_count++, 0, 0, addr,
604 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
605
606 return 0;
607 }
608
609 static int pci_uclass_pre_probe(struct udevice *bus)
610 {
611 struct pci_controller *hose;
612 int ret;
613
614 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
615 bus->parent->name);
616 hose = bus->uclass_priv;
617
618 /* For bridges, use the top-level PCI controller */
619 if (device_get_uclass_id(bus->parent) == UCLASS_ROOT) {
620 hose->ctlr = bus;
621 ret = decode_regions(hose, gd->fdt_blob, bus->parent->of_offset,
622 bus->of_offset);
623 if (ret) {
624 debug("%s: Cannot decode regions\n", __func__);
625 return ret;
626 }
627 } else {
628 struct pci_controller *parent_hose;
629
630 parent_hose = dev_get_uclass_priv(bus->parent);
631 hose->ctlr = parent_hose->bus;
632 }
633 hose->bus = bus;
634 hose->first_busno = bus->seq;
635 hose->last_busno = bus->seq;
636
637 return 0;
638 }
639
640 static int pci_uclass_post_probe(struct udevice *bus)
641 {
642 int ret;
643
644 debug("%s: probing bus %d\n", __func__, bus->seq);
645 ret = pci_bind_bus_devices(bus);
646 if (ret)
647 return ret;
648
649 #ifdef CONFIG_PCI_PNP
650 ret = pci_auto_config_devices(bus);
651 #endif
652
653 return ret < 0 ? ret : 0;
654 }
655
656 static int pci_uclass_child_post_bind(struct udevice *dev)
657 {
658 struct pci_child_platdata *pplat;
659 struct fdt_pci_addr addr;
660 int ret;
661
662 if (dev->of_offset == -1)
663 return 0;
664
665 /*
666 * We could read vendor, device, class if available. But for now we
667 * just check the address.
668 */
669 pplat = dev_get_parent_platdata(dev);
670 ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset,
671 FDT_PCI_SPACE_CONFIG, "reg", &addr);
672
673 if (ret) {
674 if (ret != -ENOENT)
675 return -EINVAL;
676 } else {
677 /* extract the bdf from fdt_pci_addr */
678 pplat->devfn = addr.phys_hi & 0xffff00;
679 }
680
681 return 0;
682 }
683
684 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
685 uint offset, ulong *valuep,
686 enum pci_size_t size)
687 {
688 struct pci_controller *hose = bus->uclass_priv;
689
690 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
691 }
692
693 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
694 uint offset, ulong value,
695 enum pci_size_t size)
696 {
697 struct pci_controller *hose = bus->uclass_priv;
698
699 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
700 }
701
702 UCLASS_DRIVER(pci) = {
703 .id = UCLASS_PCI,
704 .name = "pci",
705 .flags = DM_UC_FLAG_SEQ_ALIAS,
706 .post_bind = pci_uclass_post_bind,
707 .pre_probe = pci_uclass_pre_probe,
708 .post_probe = pci_uclass_post_probe,
709 .child_post_bind = pci_uclass_child_post_bind,
710 .per_device_auto_alloc_size = sizeof(struct pci_controller),
711 .per_child_platdata_auto_alloc_size =
712 sizeof(struct pci_child_platdata),
713 };
714
715 static const struct dm_pci_ops pci_bridge_ops = {
716 .read_config = pci_bridge_read_config,
717 .write_config = pci_bridge_write_config,
718 };
719
720 static const struct udevice_id pci_bridge_ids[] = {
721 { .compatible = "pci-bridge" },
722 { }
723 };
724
725 U_BOOT_DRIVER(pci_bridge_drv) = {
726 .name = "pci_bridge_drv",
727 .id = UCLASS_PCI,
728 .of_match = pci_bridge_ids,
729 .ops = &pci_bridge_ops,
730 };
731
732 UCLASS_DRIVER(pci_generic) = {
733 .id = UCLASS_PCI_GENERIC,
734 .name = "pci_generic",
735 };
736
737 static const struct udevice_id pci_generic_ids[] = {
738 { .compatible = "pci-generic" },
739 { }
740 };
741
742 U_BOOT_DRIVER(pci_generic_drv) = {
743 .name = "pci_generic_drv",
744 .id = UCLASS_PCI_GENERIC,
745 .of_match = pci_generic_ids,
746 };