2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct pci_controller
*pci_bus_to_hose(int busnum
)
25 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, &bus
);
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__
, busnum
, ret
);
30 return dev_get_uclass_priv(bus
);
33 pci_dev_t
pci_get_bdf(struct udevice
*dev
)
35 struct pci_child_platdata
*pplat
= dev_get_parent_platdata(dev
);
36 struct udevice
*bus
= dev
->parent
;
38 return PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
42 * pci_get_bus_max() - returns the bus number of the last active bus
44 * @return last bus number, or -1 if no active buses
46 static int pci_get_bus_max(void)
52 ret
= uclass_get(UCLASS_PCI
, &uc
);
53 uclass_foreach_dev(bus
, uc
) {
58 debug("%s: ret=%d\n", __func__
, ret
);
63 int pci_last_busno(void)
65 struct pci_controller
*hose
;
70 debug("pci_last_busno\n");
71 ret
= uclass_get(UCLASS_PCI
, &uc
);
72 if (ret
|| list_empty(&uc
->dev_head
))
75 /* Probe the last bus */
76 bus
= list_entry(uc
->dev_head
.prev
, struct udevice
, uclass_node
);
77 debug("bus = %p, %s\n", bus
, bus
->name
);
79 ret
= device_probe(bus
);
83 /* If that bus has bridges, we may have new buses now. Get the last */
84 bus
= list_entry(uc
->dev_head
.prev
, struct udevice
, uclass_node
);
85 hose
= dev_get_uclass_priv(bus
);
86 debug("bus = %s, hose = %p\n", bus
->name
, hose
);
88 return hose
->last_busno
;
91 int pci_get_ff(enum pci_size_t size
)
103 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
104 struct udevice
**devp
)
108 for (device_find_first_child(bus
, &dev
);
110 device_find_next_child(&dev
)) {
111 struct pci_child_platdata
*pplat
;
113 pplat
= dev_get_parent_platdata(dev
);
114 if (pplat
&& pplat
->devfn
== find_devfn
) {
123 int pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
128 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
131 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
134 static int pci_device_matches_ids(struct udevice
*dev
,
135 struct pci_device_id
*ids
)
137 struct pci_child_platdata
*pplat
;
140 pplat
= dev_get_parent_platdata(dev
);
143 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
144 if (pplat
->vendor
== ids
[i
].vendor
&&
145 pplat
->device
== ids
[i
].device
)
152 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
153 int *indexp
, struct udevice
**devp
)
157 /* Scan all devices on this bus */
158 for (device_find_first_child(bus
, &dev
);
160 device_find_next_child(&dev
)) {
161 if (pci_device_matches_ids(dev
, ids
) >= 0) {
162 if ((*indexp
)-- <= 0) {
172 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
173 struct udevice
**devp
)
177 /* Scan all known buses */
178 for (uclass_first_device(UCLASS_PCI
, &bus
);
180 uclass_next_device(&bus
)) {
181 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
189 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
190 unsigned long value
, enum pci_size_t size
)
192 struct dm_pci_ops
*ops
;
194 ops
= pci_get_ops(bus
);
195 if (!ops
->write_config
)
197 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
200 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
201 enum pci_size_t size
)
206 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
210 return pci_bus_write_config(bus
, bdf
, offset
, value
, size
);
213 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
215 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
218 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
220 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
223 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
225 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
228 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
229 unsigned long *valuep
, enum pci_size_t size
)
231 struct dm_pci_ops
*ops
;
233 ops
= pci_get_ops(bus
);
234 if (!ops
->read_config
)
236 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
239 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
240 enum pci_size_t size
)
245 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
249 return pci_bus_read_config(bus
, bdf
, offset
, valuep
, size
);
252 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
257 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
265 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
270 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
278 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
283 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
291 int pci_auto_config_devices(struct udevice
*bus
)
293 struct pci_controller
*hose
= bus
->uclass_priv
;
294 unsigned int sub_bus
;
299 debug("%s: start\n", __func__
);
300 pciauto_config_init(hose
);
301 for (ret
= device_find_first_child(bus
, &dev
);
303 ret
= device_find_next_child(&dev
)) {
304 unsigned int max_bus
;
306 debug("%s: device %s\n", __func__
, dev
->name
);
307 max_bus
= pciauto_config_device(hose
, pci_get_bdf(dev
));
308 sub_bus
= max(sub_bus
, max_bus
);
310 debug("%s: done\n", __func__
);
315 int dm_pci_hose_probe_bus(struct pci_controller
*hose
, pci_dev_t bdf
)
317 struct udevice
*parent
, *bus
;
321 debug("%s\n", __func__
);
324 /* Find the bus within the parent */
325 ret
= pci_bus_find_devfn(parent
, PCI_MASK_BUS(bdf
), &bus
);
327 debug("%s: Cannot find device %x on bus %s: %d\n", __func__
,
328 bdf
, parent
->name
, ret
);
332 sub_bus
= pci_get_bus_max() + 1;
333 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
334 pciauto_prescan_setup_bridge(hose
, bdf
, sub_bus
);
336 ret
= device_probe(bus
);
338 debug("%s: Cannot probe bus bus %s: %d\n", __func__
, bus
->name
,
342 if (sub_bus
!= bus
->seq
) {
343 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
344 __func__
, bus
->name
, bus
->seq
, sub_bus
);
347 sub_bus
= pci_get_bus_max();
348 pciauto_postscan_setup_bridge(hose
, bdf
, sub_bus
);
354 * pci_match_one_device - Tell if a PCI device structure has a matching
355 * PCI device id structure
356 * @id: single PCI device id structure to match
357 * @dev: the PCI device structure to match against
359 * Returns the matching pci_device_id structure or %NULL if there is no match.
361 static bool pci_match_one_id(const struct pci_device_id
*id
,
362 const struct pci_device_id
*find
)
364 if ((id
->vendor
== PCI_ANY_ID
|| id
->vendor
== find
->vendor
) &&
365 (id
->device
== PCI_ANY_ID
|| id
->device
== find
->device
) &&
366 (id
->subvendor
== PCI_ANY_ID
|| id
->subvendor
== find
->subvendor
) &&
367 (id
->subdevice
== PCI_ANY_ID
|| id
->subdevice
== find
->subdevice
) &&
368 !((id
->class ^ find
->class) & id
->class_mask
))
375 * pci_find_and_bind_driver() - Find and bind the right PCI driver
377 * This only looks at certain fields in the descriptor.
379 static int pci_find_and_bind_driver(struct udevice
*parent
,
380 struct pci_device_id
*find_id
, pci_dev_t bdf
,
381 struct udevice
**devp
)
383 struct pci_driver_entry
*start
, *entry
;
391 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__
,
392 find_id
->vendor
, find_id
->device
);
393 start
= ll_entry_start(struct pci_driver_entry
, pci_driver_entry
);
394 n_ents
= ll_entry_count(struct pci_driver_entry
, pci_driver_entry
);
395 for (entry
= start
; entry
!= start
+ n_ents
; entry
++) {
396 const struct pci_device_id
*id
;
398 const struct driver
*drv
;
400 for (id
= entry
->match
;
401 id
->vendor
|| id
->subvendor
|| id
->class_mask
;
403 if (!pci_match_one_id(id
, find_id
))
408 * We could pass the descriptor to the driver as
409 * platdata (instead of NULL) and allow its bind()
410 * method to return -ENOENT if it doesn't support this
411 * device. That way we could continue the search to
412 * find another driver. For now this doesn't seem
413 * necesssary, so just bind the first match.
415 ret
= device_bind(parent
, drv
, drv
->name
, NULL
, -1,
419 debug("%s: Match found: %s\n", __func__
, drv
->name
);
420 dev
->driver_data
= find_id
->driver_data
;
426 /* Bind a generic driver so that the device can be used */
427 sprintf(name
, "pci_%x:%x.%x", parent
->seq
, PCI_DEV(bdf
),
432 drv
= (find_id
->class >> 8) == PCI_CLASS_BRIDGE_PCI
? "pci_bridge_drv" :
434 ret
= device_bind_driver(parent
, drv
, str
, devp
);
436 debug("%s: Failed to bind generic driver: %d", __func__
, ret
);
439 debug("%s: No match found: bound generic driver instead\n", __func__
);
444 debug("%s: No match found: error %d\n", __func__
, ret
);
448 int pci_bind_bus_devices(struct udevice
*bus
)
450 ulong vendor
, device
;
457 end
= PCI_BDF(bus
->seq
, PCI_MAX_PCI_DEVICES
- 1,
458 PCI_MAX_PCI_FUNCTIONS
- 1);
459 for (bdf
= PCI_BDF(bus
->seq
, 0, 0); bdf
< end
;
460 bdf
+= PCI_BDF(0, 0, 1)) {
461 struct pci_child_platdata
*pplat
;
465 if (PCI_FUNC(bdf
) && !found_multi
)
467 /* Check only the first access, we don't expect problems */
468 ret
= pci_bus_read_config(bus
, bdf
, PCI_HEADER_TYPE
,
469 &header_type
, PCI_SIZE_8
);
472 pci_bus_read_config(bus
, bdf
, PCI_VENDOR_ID
, &vendor
,
474 if (vendor
== 0xffff || vendor
== 0x0000)
478 found_multi
= header_type
& 0x80;
480 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
481 bus
->seq
, bus
->name
, PCI_DEV(bdf
), PCI_FUNC(bdf
));
482 pci_bus_read_config(bus
, bdf
, PCI_DEVICE_ID
, &device
,
484 pci_bus_read_config(bus
, bdf
, PCI_CLASS_REVISION
, &class,
488 /* Find this device in the device tree */
489 ret
= pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), &dev
);
491 /* Search for a driver */
493 /* If nothing in the device tree, bind a generic device */
494 if (ret
== -ENODEV
) {
495 struct pci_device_id find_id
;
498 memset(&find_id
, '\0', sizeof(find_id
));
499 find_id
.vendor
= vendor
;
500 find_id
.device
= device
;
501 find_id
.class = class;
502 if ((header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
) {
503 pci_bus_read_config(bus
, bdf
,
504 PCI_SUBSYSTEM_VENDOR_ID
,
506 find_id
.subvendor
= val
& 0xffff;
507 find_id
.subdevice
= val
>> 16;
509 ret
= pci_find_and_bind_driver(bus
, &find_id
, bdf
,
515 /* Update the platform data */
516 pplat
= dev_get_parent_platdata(dev
);
517 pplat
->devfn
= PCI_MASK_BUS(bdf
);
518 pplat
->vendor
= vendor
;
519 pplat
->device
= device
;
520 pplat
->class = class;
525 printf("Cannot read bus configuration: %d\n", ret
);
530 static int pci_uclass_post_bind(struct udevice
*bus
)
533 * Scan the device tree for devices. This does not probe the PCI bus,
534 * as this is not permitted while binding. It just finds devices
535 * mentioned in the device tree.
537 * Before relocation, only bind devices marked for pre-relocation
540 return dm_scan_fdt_node(bus
, gd
->fdt_blob
, bus
->of_offset
,
541 gd
->flags
& GD_FLG_RELOC
? false : true);
544 static int decode_regions(struct pci_controller
*hose
, const void *blob
,
545 int parent_node
, int node
)
547 int pci_addr_cells
, addr_cells
, size_cells
;
548 int cells_per_record
;
554 prop
= fdt_getprop(blob
, node
, "ranges", &len
);
557 pci_addr_cells
= fdt_address_cells(blob
, node
);
558 addr_cells
= fdt_address_cells(blob
, parent_node
);
559 size_cells
= fdt_size_cells(blob
, node
);
561 /* PCI addresses are always 3-cells */
563 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
564 hose
->region_count
= 0;
565 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
567 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
568 u64 pci_addr
, addr
, size
;
573 if (len
< cells_per_record
)
575 flags
= fdt32_to_cpu(prop
[0]);
576 space_code
= (flags
>> 24) & 3;
577 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
578 prop
+= pci_addr_cells
;
579 addr
= fdtdec_get_number(prop
, addr_cells
);
581 size
= fdtdec_get_number(prop
, size_cells
);
583 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
584 ", size=%" PRIx64
", space_code=%d\n", __func__
,
585 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
586 if (space_code
& 2) {
587 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
589 } else if (space_code
& 1) {
590 type
= PCI_REGION_IO
;
594 debug(" - type=%d\n", type
);
595 pci_set_region(hose
->regions
+ hose
->region_count
++, pci_addr
,
599 /* Add a region for our local memory */
601 if (gd
->pci_ram_top
&& gd
->pci_ram_top
< addr
)
602 addr
= gd
->pci_ram_top
;
603 pci_set_region(hose
->regions
+ hose
->region_count
++, 0, 0, addr
,
604 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
609 static int pci_uclass_pre_probe(struct udevice
*bus
)
611 struct pci_controller
*hose
;
614 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
616 hose
= bus
->uclass_priv
;
618 /* For bridges, use the top-level PCI controller */
619 if (device_get_uclass_id(bus
->parent
) == UCLASS_ROOT
) {
621 ret
= decode_regions(hose
, gd
->fdt_blob
, bus
->parent
->of_offset
,
624 debug("%s: Cannot decode regions\n", __func__
);
628 struct pci_controller
*parent_hose
;
630 parent_hose
= dev_get_uclass_priv(bus
->parent
);
631 hose
->ctlr
= parent_hose
->bus
;
634 hose
->first_busno
= bus
->seq
;
635 hose
->last_busno
= bus
->seq
;
640 static int pci_uclass_post_probe(struct udevice
*bus
)
644 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
645 ret
= pci_bind_bus_devices(bus
);
649 #ifdef CONFIG_PCI_PNP
650 ret
= pci_auto_config_devices(bus
);
653 return ret
< 0 ? ret
: 0;
656 static int pci_uclass_child_post_bind(struct udevice
*dev
)
658 struct pci_child_platdata
*pplat
;
659 struct fdt_pci_addr addr
;
662 if (dev
->of_offset
== -1)
666 * We could read vendor, device, class if available. But for now we
667 * just check the address.
669 pplat
= dev_get_parent_platdata(dev
);
670 ret
= fdtdec_get_pci_addr(gd
->fdt_blob
, dev
->of_offset
,
671 FDT_PCI_SPACE_CONFIG
, "reg", &addr
);
677 /* extract the bdf from fdt_pci_addr */
678 pplat
->devfn
= addr
.phys_hi
& 0xffff00;
684 static int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t bdf
,
685 uint offset
, ulong
*valuep
,
686 enum pci_size_t size
)
688 struct pci_controller
*hose
= bus
->uclass_priv
;
690 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
693 static int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t bdf
,
694 uint offset
, ulong value
,
695 enum pci_size_t size
)
697 struct pci_controller
*hose
= bus
->uclass_priv
;
699 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
702 UCLASS_DRIVER(pci
) = {
705 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
706 .post_bind
= pci_uclass_post_bind
,
707 .pre_probe
= pci_uclass_pre_probe
,
708 .post_probe
= pci_uclass_post_probe
,
709 .child_post_bind
= pci_uclass_child_post_bind
,
710 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
711 .per_child_platdata_auto_alloc_size
=
712 sizeof(struct pci_child_platdata
),
715 static const struct dm_pci_ops pci_bridge_ops
= {
716 .read_config
= pci_bridge_read_config
,
717 .write_config
= pci_bridge_write_config
,
720 static const struct udevice_id pci_bridge_ids
[] = {
721 { .compatible
= "pci-bridge" },
725 U_BOOT_DRIVER(pci_bridge_drv
) = {
726 .name
= "pci_bridge_drv",
728 .of_match
= pci_bridge_ids
,
729 .ops
= &pci_bridge_ops
,
732 UCLASS_DRIVER(pci_generic
) = {
733 .id
= UCLASS_PCI_GENERIC
,
734 .name
= "pci_generic",
737 static const struct udevice_id pci_generic_ids
[] = {
738 { .compatible
= "pci-generic" },
742 U_BOOT_DRIVER(pci_generic_drv
) = {
743 .name
= "pci_generic_drv",
744 .id
= UCLASS_PCI_GENERIC
,
745 .of_match
= pci_generic_ids
,