2 * Copyright (c) 2014 Google, Inc
3 * Written by Simon Glass <sjg@chromium.org>
5 * SPDX-License-Identifier: GPL-2.0+
16 #include <dm/device-internal.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct pci_controller
*pci_bus_to_hose(int busnum
)
25 ret
= uclass_get_device_by_seq(UCLASS_PCI
, busnum
, &bus
);
27 debug("%s: Cannot get bus %d: ret=%d\n", __func__
, busnum
, ret
);
30 return dev_get_uclass_priv(bus
);
34 * pci_get_bus_max() - returns the bus number of the last active bus
36 * @return last bus number, or -1 if no active buses
38 static int pci_get_bus_max(void)
44 ret
= uclass_get(UCLASS_PCI
, &uc
);
45 uclass_foreach_dev(bus
, uc
) {
50 debug("%s: ret=%d\n", __func__
, ret
);
55 int pci_last_busno(void)
57 struct pci_controller
*hose
;
62 debug("pci_last_busno\n");
63 ret
= uclass_get(UCLASS_PCI
, &uc
);
64 if (ret
|| list_empty(&uc
->dev_head
))
67 /* Probe the last bus */
68 bus
= list_entry(uc
->dev_head
.prev
, struct udevice
, uclass_node
);
69 debug("bus = %p, %s\n", bus
, bus
->name
);
71 ret
= device_probe(bus
);
75 /* If that bus has bridges, we may have new buses now. Get the last */
76 bus
= list_entry(uc
->dev_head
.prev
, struct udevice
, uclass_node
);
77 hose
= dev_get_uclass_priv(bus
);
78 debug("bus = %s, hose = %p\n", bus
->name
, hose
);
80 return hose
->last_busno
;
83 int pci_get_ff(enum pci_size_t size
)
95 int pci_bus_find_devfn(struct udevice
*bus
, pci_dev_t find_devfn
,
96 struct udevice
**devp
)
100 for (device_find_first_child(bus
, &dev
);
102 device_find_next_child(&dev
)) {
103 struct pci_child_platdata
*pplat
;
105 pplat
= dev_get_parent_platdata(dev
);
106 if (pplat
&& pplat
->devfn
== find_devfn
) {
115 int pci_bus_find_bdf(pci_dev_t bdf
, struct udevice
**devp
)
120 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
123 return pci_bus_find_devfn(bus
, PCI_MASK_BUS(bdf
), devp
);
126 static int pci_device_matches_ids(struct udevice
*dev
,
127 struct pci_device_id
*ids
)
129 struct pci_child_platdata
*pplat
;
132 pplat
= dev_get_parent_platdata(dev
);
135 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
136 if (pplat
->vendor
== ids
[i
].vendor
&&
137 pplat
->device
== ids
[i
].device
)
144 int pci_bus_find_devices(struct udevice
*bus
, struct pci_device_id
*ids
,
145 int *indexp
, struct udevice
**devp
)
149 /* Scan all devices on this bus */
150 for (device_find_first_child(bus
, &dev
);
152 device_find_next_child(&dev
)) {
153 if (pci_device_matches_ids(dev
, ids
) >= 0) {
154 if ((*indexp
)-- <= 0) {
164 int pci_find_device_id(struct pci_device_id
*ids
, int index
,
165 struct udevice
**devp
)
169 /* Scan all known buses */
170 for (uclass_first_device(UCLASS_PCI
, &bus
);
172 uclass_next_device(&bus
)) {
173 if (!pci_bus_find_devices(bus
, ids
, &index
, devp
))
181 int pci_bus_write_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
182 unsigned long value
, enum pci_size_t size
)
184 struct dm_pci_ops
*ops
;
186 ops
= pci_get_ops(bus
);
187 if (!ops
->write_config
)
189 return ops
->write_config(bus
, bdf
, offset
, value
, size
);
192 int pci_write_config(pci_dev_t bdf
, int offset
, unsigned long value
,
193 enum pci_size_t size
)
198 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
202 return pci_bus_write_config(bus
, PCI_MASK_BUS(bdf
), offset
, value
,
206 int pci_write_config32(pci_dev_t bdf
, int offset
, u32 value
)
208 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_32
);
211 int pci_write_config16(pci_dev_t bdf
, int offset
, u16 value
)
213 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_16
);
216 int pci_write_config8(pci_dev_t bdf
, int offset
, u8 value
)
218 return pci_write_config(bdf
, offset
, value
, PCI_SIZE_8
);
221 int pci_bus_read_config(struct udevice
*bus
, pci_dev_t bdf
, int offset
,
222 unsigned long *valuep
, enum pci_size_t size
)
224 struct dm_pci_ops
*ops
;
226 ops
= pci_get_ops(bus
);
227 if (!ops
->read_config
)
229 return ops
->read_config(bus
, bdf
, offset
, valuep
, size
);
232 int pci_read_config(pci_dev_t bdf
, int offset
, unsigned long *valuep
,
233 enum pci_size_t size
)
238 ret
= uclass_get_device_by_seq(UCLASS_PCI
, PCI_BUS(bdf
), &bus
);
242 return pci_bus_read_config(bus
, PCI_MASK_BUS(bdf
), offset
, valuep
,
246 int pci_read_config32(pci_dev_t bdf
, int offset
, u32
*valuep
)
251 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_32
);
259 int pci_read_config16(pci_dev_t bdf
, int offset
, u16
*valuep
)
264 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_16
);
272 int pci_read_config8(pci_dev_t bdf
, int offset
, u8
*valuep
)
277 ret
= pci_read_config(bdf
, offset
, &value
, PCI_SIZE_8
);
285 int pci_auto_config_devices(struct udevice
*bus
)
287 struct pci_controller
*hose
= bus
->uclass_priv
;
288 unsigned int sub_bus
;
293 debug("%s: start\n", __func__
);
294 pciauto_config_init(hose
);
295 for (ret
= device_find_first_child(bus
, &dev
);
297 ret
= device_find_next_child(&dev
)) {
298 struct pci_child_platdata
*pplat
;
300 pplat
= dev_get_parent_platdata(dev
);
301 unsigned int max_bus
;
304 bdf
= PCI_ADD_BUS(bus
->seq
, pplat
->devfn
);
305 debug("%s: device %s\n", __func__
, dev
->name
);
306 max_bus
= pciauto_config_device(hose
, bdf
);
307 sub_bus
= max(sub_bus
, max_bus
);
309 debug("%s: done\n", __func__
);
314 int dm_pci_hose_probe_bus(struct pci_controller
*hose
, pci_dev_t bdf
)
316 struct udevice
*parent
, *bus
;
320 debug("%s\n", __func__
);
323 /* Find the bus within the parent */
324 ret
= pci_bus_find_devfn(parent
, bdf
, &bus
);
326 debug("%s: Cannot find device %x on bus %s: %d\n", __func__
,
327 bdf
, parent
->name
, ret
);
331 sub_bus
= pci_get_bus_max() + 1;
332 debug("%s: bus = %d/%s\n", __func__
, sub_bus
, bus
->name
);
333 pciauto_prescan_setup_bridge(hose
, bdf
, bus
->seq
);
335 ret
= device_probe(bus
);
337 debug("%s: Cannot probe bus bus %s: %d\n", __func__
, bus
->name
,
341 if (sub_bus
!= bus
->seq
) {
342 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
343 __func__
, bus
->name
, bus
->seq
, sub_bus
);
346 sub_bus
= pci_get_bus_max();
347 pciauto_postscan_setup_bridge(hose
, bdf
, sub_bus
);
352 int pci_bind_bus_devices(struct udevice
*bus
)
354 ulong vendor
, device
;
356 pci_dev_t devfn
, end
;
361 end
= PCI_DEVFN(PCI_MAX_PCI_DEVICES
- 1, PCI_MAX_PCI_FUNCTIONS
- 1);
362 for (devfn
= PCI_DEVFN(0, 0); devfn
< end
; devfn
+= PCI_DEVFN(0, 1)) {
363 struct pci_child_platdata
*pplat
;
367 if (PCI_FUNC(devfn
) && !found_multi
)
369 /* Check only the first access, we don't expect problems */
370 ret
= pci_bus_read_config(bus
, devfn
, PCI_HEADER_TYPE
,
371 &header_type
, PCI_SIZE_8
);
374 pci_bus_read_config(bus
, devfn
, PCI_VENDOR_ID
, &vendor
,
376 if (vendor
== 0xffff || vendor
== 0x0000)
379 if (!PCI_FUNC(devfn
))
380 found_multi
= header_type
& 0x80;
382 debug("%s: bus %d/%s: found device %x, function %d\n", __func__
,
383 bus
->seq
, bus
->name
, PCI_DEV(devfn
), PCI_FUNC(devfn
));
384 pci_bus_read_config(bus
, devfn
, PCI_DEVICE_ID
, &device
,
386 pci_bus_read_config(bus
, devfn
, PCI_CLASS_DEVICE
, &class,
389 /* Find this device in the device tree */
390 ret
= pci_bus_find_devfn(bus
, devfn
, &dev
);
392 /* If nothing in the device tree, bind a generic device */
393 if (ret
== -ENODEV
) {
397 sprintf(name
, "pci_%x:%x.%x", bus
->seq
,
398 PCI_DEV(devfn
), PCI_FUNC(devfn
));
402 drv
= class == PCI_CLASS_BRIDGE_PCI
?
403 "pci_bridge_drv" : "pci_generic_drv";
404 ret
= device_bind_driver(bus
, drv
, str
, &dev
);
409 /* Update the platform data */
410 pplat
= dev_get_parent_platdata(dev
);
411 pplat
->devfn
= devfn
;
412 pplat
->vendor
= vendor
;
413 pplat
->device
= device
;
414 pplat
->class = class;
419 printf("Cannot read bus configuration: %d\n", ret
);
424 static int pci_uclass_post_bind(struct udevice
*bus
)
427 * Scan the device tree for devices. This does not probe the PCI bus,
428 * as this is not permitted while binding. It just finds devices
429 * mentioned in the device tree.
431 * Before relocation, only bind devices marked for pre-relocation
434 return dm_scan_fdt_node(bus
, gd
->fdt_blob
, bus
->of_offset
,
435 gd
->flags
& GD_FLG_RELOC
? false : true);
438 static int decode_regions(struct pci_controller
*hose
, const void *blob
,
439 int parent_node
, int node
)
441 int pci_addr_cells
, addr_cells
, size_cells
;
442 int cells_per_record
;
447 prop
= fdt_getprop(blob
, node
, "ranges", &len
);
450 pci_addr_cells
= fdt_address_cells(blob
, node
);
451 addr_cells
= fdt_address_cells(blob
, parent_node
);
452 size_cells
= fdt_size_cells(blob
, node
);
454 /* PCI addresses are always 3-cells */
456 cells_per_record
= pci_addr_cells
+ addr_cells
+ size_cells
;
457 hose
->region_count
= 0;
458 debug("%s: len=%d, cells_per_record=%d\n", __func__
, len
,
460 for (i
= 0; i
< MAX_PCI_REGIONS
; i
++, len
-= cells_per_record
) {
461 u64 pci_addr
, addr
, size
;
466 if (len
< cells_per_record
)
468 flags
= fdt32_to_cpu(prop
[0]);
469 space_code
= (flags
>> 24) & 3;
470 pci_addr
= fdtdec_get_number(prop
+ 1, 2);
471 prop
+= pci_addr_cells
;
472 addr
= fdtdec_get_number(prop
, addr_cells
);
474 size
= fdtdec_get_number(prop
, size_cells
);
476 debug("%s: region %d, pci_addr=%" PRIx64
", addr=%" PRIx64
477 ", size=%" PRIx64
", space_code=%d\n", __func__
,
478 hose
->region_count
, pci_addr
, addr
, size
, space_code
);
479 if (space_code
& 2) {
480 type
= flags
& (1U << 30) ? PCI_REGION_PREFETCH
:
482 } else if (space_code
& 1) {
483 type
= PCI_REGION_IO
;
487 debug(" - type=%d\n", type
);
488 pci_set_region(hose
->regions
+ hose
->region_count
++, pci_addr
,
492 /* Add a region for our local memory */
493 pci_set_region(hose
->regions
+ hose
->region_count
++, 0, 0,
494 gd
->ram_size
, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
499 static int pci_uclass_pre_probe(struct udevice
*bus
)
501 struct pci_controller
*hose
;
504 debug("%s, bus=%d/%s, parent=%s\n", __func__
, bus
->seq
, bus
->name
,
506 hose
= bus
->uclass_priv
;
508 /* For bridges, use the top-level PCI controller */
509 if (device_get_uclass_id(bus
->parent
) == UCLASS_ROOT
) {
511 ret
= decode_regions(hose
, gd
->fdt_blob
, bus
->parent
->of_offset
,
514 debug("%s: Cannot decode regions\n", __func__
);
518 struct pci_controller
*parent_hose
;
520 parent_hose
= dev_get_uclass_priv(bus
->parent
);
521 hose
->ctlr
= parent_hose
->bus
;
524 hose
->first_busno
= bus
->seq
;
525 hose
->last_busno
= bus
->seq
;
530 static int pci_uclass_post_probe(struct udevice
*bus
)
534 /* Don't scan buses before relocation */
535 if (!(gd
->flags
& GD_FLG_RELOC
))
538 debug("%s: probing bus %d\n", __func__
, bus
->seq
);
539 ret
= pci_bind_bus_devices(bus
);
543 #ifdef CONFIG_PCI_PNP
544 ret
= pci_auto_config_devices(bus
);
547 return ret
< 0 ? ret
: 0;
550 static int pci_uclass_child_post_bind(struct udevice
*dev
)
552 struct pci_child_platdata
*pplat
;
553 struct fdt_pci_addr addr
;
556 if (dev
->of_offset
== -1)
560 * We could read vendor, device, class if available. But for now we
561 * just check the address.
563 pplat
= dev_get_parent_platdata(dev
);
564 ret
= fdtdec_get_pci_addr(gd
->fdt_blob
, dev
->of_offset
,
565 FDT_PCI_SPACE_CONFIG
, "reg", &addr
);
571 /* extract the bdf from fdt_pci_addr */
572 pplat
->devfn
= addr
.phys_hi
& 0xffff00;
578 int pci_bridge_read_config(struct udevice
*bus
, pci_dev_t devfn
, uint offset
,
579 ulong
*valuep
, enum pci_size_t size
)
581 struct pci_controller
*hose
= bus
->uclass_priv
;
582 pci_dev_t bdf
= PCI_ADD_BUS(bus
->seq
, devfn
);
584 return pci_bus_read_config(hose
->ctlr
, bdf
, offset
, valuep
, size
);
587 int pci_bridge_write_config(struct udevice
*bus
, pci_dev_t devfn
, uint offset
,
588 ulong value
, enum pci_size_t size
)
590 struct pci_controller
*hose
= bus
->uclass_priv
;
591 pci_dev_t bdf
= PCI_ADD_BUS(bus
->seq
, devfn
);
593 return pci_bus_write_config(hose
->ctlr
, bdf
, offset
, value
, size
);
596 UCLASS_DRIVER(pci
) = {
599 .flags
= DM_UC_FLAG_SEQ_ALIAS
,
600 .post_bind
= pci_uclass_post_bind
,
601 .pre_probe
= pci_uclass_pre_probe
,
602 .post_probe
= pci_uclass_post_probe
,
603 .child_post_bind
= pci_uclass_child_post_bind
,
604 .per_device_auto_alloc_size
= sizeof(struct pci_controller
),
605 .per_child_platdata_auto_alloc_size
=
606 sizeof(struct pci_child_platdata
),
609 static const struct dm_pci_ops pci_bridge_ops
= {
610 .read_config
= pci_bridge_read_config
,
611 .write_config
= pci_bridge_write_config
,
614 static const struct udevice_id pci_bridge_ids
[] = {
615 { .compatible
= "pci-bridge" },
619 U_BOOT_DRIVER(pci_bridge_drv
) = {
620 .name
= "pci_bridge_drv",
622 .of_match
= pci_bridge_ids
,
623 .ops
= &pci_bridge_ops
,
626 UCLASS_DRIVER(pci_generic
) = {
627 .id
= UCLASS_PCI_GENERIC
,
628 .name
= "pci_generic",
631 static const struct udevice_id pci_generic_ids
[] = {
632 { .compatible
= "pci-generic" },
636 U_BOOT_DRIVER(pci_generic_drv
) = {
637 .name
= "pci_generic_drv",
638 .id
= UCLASS_PCI_GENERIC
,
639 .of_match
= pci_generic_ids
,