drivers/pci/pci.c

   1 /*
   2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   3  * Andreas Heppel <aheppel@sysgo.de>
   4  *
   5  * (C) Copyright 2002, 2003
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  * PCI routines
  13  */
  14
  15 #include <common.h>
  16
  17 #include <command.h>
  18 #include <errno.h>
  19 #include <asm/processor.h>
  20 #include <asm/io.h>
  21 #include <pci.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define PCI_HOSE_OP(rw, size, type)                                     \
  26 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
  27                                   pci_dev_t dev,                        \
  28                                   int offset, type value)               \
  29 {                                                                       \
  30         return hose->rw##_##size(hose, dev, offset, value);             \
  31 }
  32
  33 PCI_HOSE_OP(read, byte, u8 *)
  34 PCI_HOSE_OP(read, word, u16 *)
  35 PCI_HOSE_OP(read, dword, u32 *)
  36 PCI_HOSE_OP(write, byte, u8)
  37 PCI_HOSE_OP(write, word, u16)
  38 PCI_HOSE_OP(write, dword, u32)
  39
  40 #define PCI_OP(rw, size, type, error_code)                              \
  41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
  42 {                                                                       \
  43         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
  44                                                                         \
  45         if (!hose)                                                      \
  46         {                                                               \
  47                 error_code;                                             \
  48                 return -1;                                              \
  49         }                                                               \
  50                                                                         \
  51         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
  52 }
  53
  54 PCI_OP(read, byte, u8 *, *value = 0xff)
  55 PCI_OP(read, word, u16 *, *value = 0xffff)
  56 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
  57 PCI_OP(write, byte, u8, )
  58 PCI_OP(write, word, u16, )
  59 PCI_OP(write, dword, u32, )
  60
  61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
  62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
  63                                         pci_dev_t dev,                  \
  64                                         int offset, type val)           \
  65 {                                                                       \
  66         u32 val32;                                                      \
  67                                                                         \
  68         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
  69                 *val = -1;                                              \
  70                 return -1;                                              \
  71         }                                                               \
  72                                                                         \
  73         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
  74                                                                         \
  75         return 0;                                                       \
  76 }
  77
  78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
  79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
  80                                              pci_dev_t dev,             \
  81                                              int offset, type val)      \
  82 {                                                                       \
  83         u32 val32, mask, ldata, shift;                                  \
  84                                                                         \
  85         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
  86                 return -1;                                              \
  87                                                                         \
  88         shift = ((offset & (int)off_mask) * 8);                         \
  89         ldata = (((unsigned long)val) & val_mask) << shift;             \
  90         mask = val_mask << shift;                                       \
  91         val32 = (val32 & ~mask) | ldata;                                \
  92                                                                         \
  93         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
  94                 return -1;                                              \
  95                                                                         \
  96         return 0;                                                       \
  97 }
  98
  99 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
 100 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
 101 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
 102 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
 103
 104 /* Get a virtual address associated with a BAR region */
 105 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 106 {
 107         pci_addr_t pci_bus_addr;
 108         u32 bar_response;
 109
 110         /* read BAR address */
 111         pci_read_config_dword(pdev, bar, &bar_response);
 112         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
 113
 114         /*
 115          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
 116          * isn't actualy used on any platform because u-boot assumes a static
 117          * linear mapping.  In the future, this could read the BAR size
 118          * and pass that as the size if needed.
 119          */
 120         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
 121 }
 122
 123 /*
 124  *
 125  */
 126
 127 static struct pci_controller* hose_head;
 128
 129 struct pci_controller *pci_get_hose_head(void)
 130 {
 131         if (gd->hose)
 132                 return gd->hose;
 133
 134         return hose_head;
 135 }
 136
 137 void pci_register_hose(struct pci_controller* hose)
 138 {
 139         struct pci_controller **phose = &hose_head;
 140
 141         while(*phose)
 142                 phose = &(*phose)->next;
 143
 144         hose->next = NULL;
 145
 146         *phose = hose;
 147 }
 148
 149 struct pci_controller *pci_bus_to_hose(int bus)
 150 {
 151         struct pci_controller *hose;
 152
 153         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 154                 if (bus >= hose->first_busno && bus <= hose->last_busno)
 155                         return hose;
 156         }
 157
 158         printf("pci_bus_to_hose() failed\n");
 159         return NULL;
 160 }
 161
 162 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
 163 {
 164         struct pci_controller *hose;
 165
 166         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 167                 if (hose->cfg_addr == cfg_addr)
 168                         return hose;
 169         }
 170
 171         return NULL;
 172 }
 173
 174 int pci_last_busno(void)
 175 {
 176         struct pci_controller *hose = pci_get_hose_head();
 177
 178         if (!hose)
 179                 return -1;
 180
 181         while (hose->next)
 182                 hose = hose->next;
 183
 184         return hose->last_busno;
 185 }
 186
 187 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
 188 {
 189         struct pci_controller * hose;
 190         u16 vendor, device;
 191         u8 header_type;
 192         pci_dev_t bdf;
 193         int i, bus, found_multi = 0;
 194
 195         for (hose = pci_get_hose_head(); hose; hose = hose->next) {
 196 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
 197                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
 198 #else
 199                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
 200 #endif
 201                         for (bdf = PCI_BDF(bus, 0, 0);
 202                              bdf < PCI_BDF(bus + 1, 0, 0);
 203                              bdf += PCI_BDF(0, 0, 1)) {
 204                                 if (pci_skip_dev(hose, bdf))
 205                                         continue;
 206
 207                                 if (!PCI_FUNC(bdf)) {
 208                                         pci_read_config_byte(bdf,
 209                                                              PCI_HEADER_TYPE,
 210                                                              &header_type);
 211
 212                                         found_multi = header_type & 0x80;
 213                                 } else {
 214                                         if (!found_multi)
 215                                                 continue;
 216                                 }
 217
 218                                 pci_read_config_word(bdf,
 219                                                      PCI_VENDOR_ID,
 220                                                      &vendor);
 221                                 pci_read_config_word(bdf,
 222                                                      PCI_DEVICE_ID,
 223                                                      &device);
 224
 225                                 for (i = 0; ids[i].vendor != 0; i++) {
 226                                         if (vendor == ids[i].vendor &&
 227                                             device == ids[i].device) {
 228                                                 if (index <= 0)
 229                                                         return bdf;
 230
 231                                                 index--;
 232                                         }
 233                                 }
 234                         }
 235         }
 236
 237         return -1;
 238 }
 239
 240 pci_dev_t pci_find_class(uint find_class, int index)
 241 {
 242         int bus;
 243         int devnum;
 244         pci_dev_t bdf;
 245         uint32_t class;
 246
 247         for (bus = 0; bus <= pci_last_busno(); bus++) {
 248                 for (devnum = 0; devnum < PCI_MAX_PCI_DEVICES - 1; devnum++) {
 249                         pci_read_config_dword(PCI_BDF(bus, devnum, 0),
 250                                               PCI_CLASS_REVISION, &class);
 251                         if (class >> 16 == 0xffff)
 252                                 continue;
 253
 254                         for (bdf = PCI_BDF(bus, devnum, 0);
 255                                         bdf <= PCI_BDF(bus, devnum,
 256                                                 PCI_MAX_PCI_FUNCTIONS - 1);
 257                                         bdf += PCI_BDF(0, 0, 1)) {
 258                                 pci_read_config_dword(bdf, PCI_CLASS_REVISION,
 259                                                       &class);
 260                                 class >>= 8;
 261
 262                                 if (class != find_class)
 263                                         continue;
 264                                 /*
 265                                  * Decrement the index. We want to return the
 266                                  * correct device, so index is 0 for the first
 267                                  * matching device, 1 for the second, etc.
 268                                  */
 269                                 if (index) {
 270                                         index--;
 271                                         continue;
 272                                 }
 273                                 /* Return index'th controller. */
 274                                 return bdf;
 275                         }
 276                 }
 277         }
 278
 279         return -ENODEV;
 280 }
 281
 282 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
 283 {
 284         struct pci_device_id ids[2] = { {}, {0, 0} };
 285
 286         ids[0].vendor = vendor;
 287         ids[0].device = device;
 288
 289         return pci_find_devices(ids, index);
 290 }
 291
 292 /*
 293  *
 294  */
 295
 296 int __pci_hose_phys_to_bus(struct pci_controller *hose,
 297                                 phys_addr_t phys_addr,
 298                                 unsigned long flags,
 299                                 unsigned long skip_mask,
 300                                 pci_addr_t *ba)
 301 {
 302         struct pci_region *res;
 303         pci_addr_t bus_addr;
 304         int i;
 305
 306         for (i = 0; i < hose->region_count; i++) {
 307                 res = &hose->regions[i];
 308
 309                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 310                         continue;
 311
 312                 if (res->flags & skip_mask)
 313                         continue;
 314
 315                 bus_addr = phys_addr - res->phys_start + res->bus_start;
 316
 317                 if (bus_addr >= res->bus_start &&
 318                         bus_addr < res->bus_start + res->size) {
 319                         *ba = bus_addr;
 320                         return 0;
 321                 }
 322         }
 323
 324         return 1;
 325 }
 326
 327 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
 328                                     phys_addr_t phys_addr,
 329                                     unsigned long flags)
 330 {
 331         pci_addr_t bus_addr = 0;
 332         int ret;
 333
 334         if (!hose) {
 335                 puts("pci_hose_phys_to_bus: invalid hose\n");
 336                 return bus_addr;
 337         }
 338
 339         /*
 340          * if PCI_REGION_MEM is set we do a two pass search with preference
 341          * on matches that don't have PCI_REGION_SYS_MEMORY set
 342          */
 343         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 344                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
 345                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
 346                 if (!ret)
 347                         return bus_addr;
 348         }
 349
 350         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
 351
 352         if (ret)
 353                 puts("pci_hose_phys_to_bus: invalid physical address\n");
 354
 355         return bus_addr;
 356 }
 357
 358 int __pci_hose_bus_to_phys(struct pci_controller *hose,
 359                                 pci_addr_t bus_addr,
 360                                 unsigned long flags,
 361                                 unsigned long skip_mask,
 362                                 phys_addr_t *pa)
 363 {
 364         struct pci_region *res;
 365         int i;
 366
 367         for (i = 0; i < hose->region_count; i++) {
 368                 res = &hose->regions[i];
 369
 370                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
 371                         continue;
 372
 373                 if (res->flags & skip_mask)
 374                         continue;
 375
 376                 if (bus_addr >= res->bus_start &&
 377                         (bus_addr - res->bus_start) < res->size) {
 378                         *pa = (bus_addr - res->bus_start + res->phys_start);
 379                         return 0;
 380                 }
 381         }
 382
 383         return 1;
 384 }
 385
 386 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
 387                                  pci_addr_t bus_addr,
 388                                  unsigned long flags)
 389 {
 390         phys_addr_t phys_addr = 0;
 391         int ret;
 392
 393         if (!hose) {
 394                 puts("pci_hose_bus_to_phys: invalid hose\n");
 395                 return phys_addr;
 396         }
 397
 398         /*
 399          * if PCI_REGION_MEM is set we do a two pass search with preference
 400          * on matches that don't have PCI_REGION_SYS_MEMORY set
 401          */
 402         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
 403                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
 404                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
 405                 if (!ret)
 406                         return phys_addr;
 407         }
 408
 409         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
 410
 411         if (ret)
 412                 puts("pci_hose_bus_to_phys: invalid physical address\n");
 413
 414         return phys_addr;
 415 }
 416
 417 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
 418                      u32 addr_and_ctrl)
 419 {
 420         int bar;
 421
 422         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
 423         pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
 424 }
 425
 426 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
 427 {
 428         u32 addr;
 429         int bar;
 430
 431         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
 432         pci_hose_read_config_dword(hose, dev, bar, &addr);
 433         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
 434                 return addr & PCI_BASE_ADDRESS_IO_MASK;
 435         else
 436                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
 437 }
 438
 439 int pci_hose_config_device(struct pci_controller *hose,
 440                            pci_dev_t dev,
 441                            unsigned long io,
 442                            pci_addr_t mem,
 443                            unsigned long command)
 444 {
 445         u32 bar_response;
 446         unsigned int old_command;
 447         pci_addr_t bar_value;
 448         pci_size_t bar_size;
 449         unsigned char pin;
 450         int bar, found_mem64;
 451
 452         debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
 453                 (u64)mem, command);
 454
 455         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
 456
 457         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
 458                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
 459                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
 460
 461                 if (!bar_response)
 462                         continue;
 463
 464                 found_mem64 = 0;
 465
 466                 /* Check the BAR type and set our address mask */
 467                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
 468                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 469                         /* round up region base address to a multiple of size */
 470                         io = ((io - 1) | (bar_size - 1)) + 1;
 471                         bar_value = io;
 472                         /* compute new region base address */
 473                         io = io + bar_size;
 474                 } else {
 475                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 476                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
 477                                 u32 bar_response_upper;
 478                                 u64 bar64;
 479                                 pci_hose_write_config_dword(hose, dev, bar + 4,
 480                                         0xffffffff);
 481                                 pci_hose_read_config_dword(hose, dev, bar + 4,
 482                                         &bar_response_upper);
 483
 484                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
 485
 486                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 487                                 found_mem64 = 1;
 488                         } else {
 489                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
 490                         }
 491
 492                         /* round up region base address to multiple of size */
 493                         mem = ((mem - 1) | (bar_size - 1)) + 1;
 494                         bar_value = mem;
 495                         /* compute new region base address */
 496                         mem = mem + bar_size;
 497                 }
 498
 499                 /* Write it out and update our limit */
 500                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
 501
 502                 if (found_mem64) {
 503                         bar += 4;
 504 #ifdef CONFIG_SYS_PCI_64BIT
 505                         pci_hose_write_config_dword(hose, dev, bar,
 506                                 (u32)(bar_value >> 32));
 507 #else
 508                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 509 #endif
 510                 }
 511         }
 512
 513         /* Configure Cache Line Size Register */
 514         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 515
 516         /* Configure Latency Timer */
 517         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 518
 519         /* Disable interrupt line, if device says it wants to use interrupts */
 520         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
 521         if (pin != 0) {
 522                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
 523         }
 524
 525         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
 526         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
 527                                      (old_command & 0xffff0000) | command);
 528
 529         return 0;
 530 }
 531
 532 /*
 533  *
 534  */
 535
 536 struct pci_config_table *pci_find_config(struct pci_controller *hose,
 537                                          unsigned short class,
 538                                          unsigned int vendor,
 539                                          unsigned int device,
 540                                          unsigned int bus,
 541                                          unsigned int dev,
 542                                          unsigned int func)
 543 {
 544         struct pci_config_table *table;
 545
 546         for (table = hose->config_table; table && table->vendor; table++) {
 547                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
 548                     (table->device == PCI_ANY_ID || table->device == device) &&
 549                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
 550                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
 551                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
 552                     (table->func   == PCI_ANY_ID || table->func   == func)) {
 553                         return table;
 554                 }
 555         }
 556
 557         return NULL;
 558 }
 559
 560 void pci_cfgfunc_config_device(struct pci_controller *hose,
 561                                pci_dev_t dev,
 562                                struct pci_config_table *entry)
 563 {
 564         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
 565                 entry->priv[2]);
 566 }
 567
 568 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
 569                             pci_dev_t dev, struct pci_config_table *entry)
 570 {
 571 }
 572
 573 /*
 574  * HJF: Changed this to return int. I think this is required
 575  * to get the correct result when scanning bridges
 576  */
 577 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
 578
 579 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
 580 const char * pci_class_str(u8 class)
 581 {
 582         switch (class) {
 583         case PCI_CLASS_NOT_DEFINED:
 584                 return "Build before PCI Rev2.0";
 585                 break;
 586         case PCI_BASE_CLASS_STORAGE:
 587                 return "Mass storage controller";
 588                 break;
 589         case PCI_BASE_CLASS_NETWORK:
 590                 return "Network controller";
 591                 break;
 592         case PCI_BASE_CLASS_DISPLAY:
 593                 return "Display controller";
 594                 break;
 595         case PCI_BASE_CLASS_MULTIMEDIA:
 596                 return "Multimedia device";
 597                 break;
 598         case PCI_BASE_CLASS_MEMORY:
 599                 return "Memory controller";
 600                 break;
 601         case PCI_BASE_CLASS_BRIDGE:
 602                 return "Bridge device";
 603                 break;
 604         case PCI_BASE_CLASS_COMMUNICATION:
 605                 return "Simple comm. controller";
 606                 break;
 607         case PCI_BASE_CLASS_SYSTEM:
 608                 return "Base system peripheral";
 609                 break;
 610         case PCI_BASE_CLASS_INPUT:
 611                 return "Input device";
 612                 break;
 613         case PCI_BASE_CLASS_DOCKING:
 614                 return "Docking station";
 615                 break;
 616         case PCI_BASE_CLASS_PROCESSOR:
 617                 return "Processor";
 618                 break;
 619         case PCI_BASE_CLASS_SERIAL:
 620                 return "Serial bus controller";
 621                 break;
 622         case PCI_BASE_CLASS_INTELLIGENT:
 623                 return "Intelligent controller";
 624                 break;
 625         case PCI_BASE_CLASS_SATELLITE:
 626                 return "Satellite controller";
 627                 break;
 628         case PCI_BASE_CLASS_CRYPT:
 629                 return "Cryptographic device";
 630                 break;
 631         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
 632                 return "DSP";
 633                 break;
 634         case PCI_CLASS_OTHERS:
 635                 return "Does not fit any class";
 636                 break;
 637         default:
 638         return  "???";
 639                 break;
 640         };
 641 }
 642 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
 643
 644 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 645 {
 646         /*
 647          * Check if pci device should be skipped in configuration
 648          */
 649         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
 650 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
 651                 /*
 652                  * Only skip configuration if "pciconfighost" is not set
 653                  */
 654                 if (getenv("pciconfighost") == NULL)
 655                         return 1;
 656 #else
 657                 return 1;
 658 #endif
 659         }
 660
 661         return 0;
 662 }
 663
 664 #ifdef CONFIG_PCI_SCAN_SHOW
 665 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
 666 {
 667         if (dev == PCI_BDF(hose->first_busno, 0, 0))
 668                 return 0;
 669
 670         return 1;
 671 }
 672 #endif /* CONFIG_PCI_SCAN_SHOW */
 673
 674 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
 675 {
 676         unsigned int sub_bus, found_multi = 0;
 677         unsigned short vendor, device, class;
 678         unsigned char header_type;
 679 #ifndef CONFIG_PCI_PNP
 680         struct pci_config_table *cfg;
 681 #endif
 682         pci_dev_t dev;
 683 #ifdef CONFIG_PCI_SCAN_SHOW
 684         static int indent = 0;
 685 #endif
 686
 687         sub_bus = bus;
 688
 689         for (dev =  PCI_BDF(bus,0,0);
 690              dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
 691                                 PCI_MAX_PCI_FUNCTIONS - 1);
 692              dev += PCI_BDF(0, 0, 1)) {
 693
 694                 if (pci_skip_dev(hose, dev))
 695                         continue;
 696
 697                 if (PCI_FUNC(dev) && !found_multi)
 698                         continue;
 699
 700                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
 701
 702                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
 703
 704                 if (vendor == 0xffff || vendor == 0x0000)
 705                         continue;
 706
 707                 if (!PCI_FUNC(dev))
 708                         found_multi = header_type & 0x80;
 709
 710                 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
 711                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 712
 713                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
 714                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 715
 716 #ifdef CONFIG_PCI_FIXUP_DEV
 717                 board_pci_fixup_dev(hose, dev, vendor, device, class);
 718 #endif
 719
 720 #ifdef CONFIG_PCI_SCAN_SHOW
 721                 indent++;
 722
 723                 /* Print leading space, including bus indentation */
 724                 printf("%*c", indent + 1, ' ');
 725
 726                 if (pci_print_dev(hose, dev)) {
 727                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
 728                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
 729                                vendor, device, pci_class_str(class >> 8));
 730                 }
 731 #endif
 732
 733 #ifdef CONFIG_PCI_PNP
 734                 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
 735                               sub_bus);
 736 #else
 737                 cfg = pci_find_config(hose, class, vendor, device,
 738                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
 739                 if (cfg) {
 740                         cfg->config_device(hose, dev, cfg);
 741                         sub_bus = max(sub_bus,
 742                                       (unsigned int)hose->current_busno);
 743                 }
 744 #endif
 745
 746 #ifdef CONFIG_PCI_SCAN_SHOW
 747                 indent--;
 748 #endif
 749
 750                 if (hose->fixup_irq)
 751                         hose->fixup_irq(hose, dev);
 752         }
 753
 754         return sub_bus;
 755 }
 756
 757 int pci_hose_scan(struct pci_controller *hose)
 758 {
 759 #if defined(CONFIG_PCI_BOOTDELAY)
 760         char *s;
 761         int i;
 762
 763         if (!gd->pcidelay_done) {
 764                 /* wait "pcidelay" ms (if defined)... */
 765                 s = getenv("pcidelay");
 766                 if (s) {
 767                         int val = simple_strtoul(s, NULL, 10);
 768                         for (i = 0; i < val; i++)
 769                                 udelay(1000);
 770                 }
 771                 gd->pcidelay_done = 1;
 772         }
 773 #endif /* CONFIG_PCI_BOOTDELAY */
 774
 775         /*
 776          * Start scan at current_busno.
 777          * PCIe will start scan at first_busno+1.
 778          */
 779         /* For legacy support, ensure current >= first */
 780         if (hose->first_busno > hose->current_busno)
 781                 hose->current_busno = hose->first_busno;
 782 #ifdef CONFIG_PCI_PNP
 783         pciauto_config_init(hose);
 784 #endif
 785         return pci_hose_scan_bus(hose, hose->current_busno);
 786 }
 787
 788 void pci_init(void)
 789 {
 790         hose_head = NULL;
 791
 792         /* now call board specific pci_init()... */
 793         pci_init_board();
 794 }
 795
 796 /* Returns the address of the requested capability structure within the
 797  * device's PCI configuration space or 0 in case the device does not
 798  * support it.
 799  * */
 800 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
 801                              int cap)
 802 {
 803         int pos;
 804         u8 hdr_type;
 805
 806         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
 807
 808         pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
 809
 810         if (pos)
 811                 pos = pci_find_cap(hose, dev, pos, cap);
 812
 813         return pos;
 814 }
 815
 816 /* Find the header pointer to the Capabilities*/
 817 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
 818                             u8 hdr_type)
 819 {
 820         u16 status;
 821
 822         pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
 823
 824         if (!(status & PCI_STATUS_CAP_LIST))
 825                 return 0;
 826
 827         switch (hdr_type) {
 828         case PCI_HEADER_TYPE_NORMAL:
 829         case PCI_HEADER_TYPE_BRIDGE:
 830                 return PCI_CAPABILITY_LIST;
 831         case PCI_HEADER_TYPE_CARDBUS:
 832                 return PCI_CB_CAPABILITY_LIST;
 833         default:
 834                 return 0;
 835         }
 836 }
 837
 838 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
 839 {
 840         int ttl = PCI_FIND_CAP_TTL;
 841         u8 id;
 842         u8 next_pos;
 843
 844         while (ttl--) {
 845                 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
 846                 if (next_pos < CAP_START_POS)
 847                         break;
 848                 next_pos &= ~3;
 849                 pos = (int) next_pos;
 850                 pci_hose_read_config_byte(hose, dev,
 851                                           pos + PCI_CAP_LIST_ID, &id);
 852                 if (id == 0xff)
 853                         break;
 854                 if (id == cap)
 855                         return pos;
 856                 pos += PCI_CAP_LIST_NEXT;
 857         }
 858         return 0;
 859 }