2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR
;
25 #define PCI_HOSE_OP(rw, size, type) \
26 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
28 int offset, type value) \
30 return hose->rw##_##size(hose, dev, offset, value); \
33 PCI_HOSE_OP(read
, byte
, u8
*)
34 PCI_HOSE_OP(read
, word
, u16
*)
35 PCI_HOSE_OP(read
, dword
, u32
*)
36 PCI_HOSE_OP(write
, byte
, u8
)
37 PCI_HOSE_OP(write
, word
, u16
)
38 PCI_HOSE_OP(write
, dword
, u32
)
40 #define PCI_OP(rw, size, type, error_code) \
41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
43 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
51 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
54 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
55 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
56 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
57 PCI_OP(write
, byte
, u8
, )
58 PCI_OP(write
, word
, u16
, )
59 PCI_OP(write
, dword
, u32
, )
61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
64 int offset, type val) \
68 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
73 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
81 int offset, type val) \
83 u32 val32, mask, ldata, shift; \
85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88 shift = ((offset & (int)off_mask) * 8); \
89 ldata = (((unsigned long)val) & val_mask) << shift; \
90 mask = val_mask << shift; \
91 val32 = (val32 & ~mask) | ldata; \
93 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
99 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
100 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
101 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
102 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
108 static struct pci_controller
* hose_head
;
110 struct pci_controller
*pci_get_hose_head(void)
118 void pci_register_hose(struct pci_controller
* hose
)
120 struct pci_controller
**phose
= &hose_head
;
123 phose
= &(*phose
)->next
;
130 struct pci_controller
*pci_bus_to_hose(int bus
)
132 struct pci_controller
*hose
;
134 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
135 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
139 printf("pci_bus_to_hose() failed\n");
143 struct pci_controller
*find_hose_by_cfg_addr(void *cfg_addr
)
145 struct pci_controller
*hose
;
147 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
148 if (hose
->cfg_addr
== cfg_addr
)
155 int pci_last_busno(void)
157 struct pci_controller
*hose
= pci_get_hose_head();
165 return hose
->last_busno
;
168 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
170 struct pci_controller
* hose
;
174 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
175 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
176 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--) {
178 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++) {
180 bdf
= pci_hose_find_devices(hose
, bus
, ids
, &index
);
189 int pci_hose_config_device(struct pci_controller
*hose
,
193 unsigned long command
)
196 unsigned int old_command
;
197 pci_addr_t bar_value
;
200 int bar
, found_mem64
;
202 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io
,
205 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, 0);
207 for (bar
= PCI_BASE_ADDRESS_0
; bar
<= PCI_BASE_ADDRESS_5
; bar
+= 4) {
208 pci_hose_write_config_dword(hose
, dev
, bar
, 0xffffffff);
209 pci_hose_read_config_dword(hose
, dev
, bar
, &bar_response
);
216 /* Check the BAR type and set our address mask */
217 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
218 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
219 /* round up region base address to a multiple of size */
220 io
= ((io
- 1) | (bar_size
- 1)) + 1;
222 /* compute new region base address */
225 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
226 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
227 u32 bar_response_upper
;
229 pci_hose_write_config_dword(hose
, dev
, bar
+ 4,
231 pci_hose_read_config_dword(hose
, dev
, bar
+ 4,
232 &bar_response_upper
);
234 bar64
= ((u64
)bar_response_upper
<< 32) | bar_response
;
236 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
239 bar_size
= (u32
)(~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1);
242 /* round up region base address to multiple of size */
243 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
245 /* compute new region base address */
246 mem
= mem
+ bar_size
;
249 /* Write it out and update our limit */
250 pci_hose_write_config_dword (hose
, dev
, bar
, (u32
)bar_value
);
254 #ifdef CONFIG_SYS_PCI_64BIT
255 pci_hose_write_config_dword(hose
, dev
, bar
,
256 (u32
)(bar_value
>> 32));
258 pci_hose_write_config_dword(hose
, dev
, bar
, 0x00000000);
263 /* Configure Cache Line Size Register */
264 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
266 /* Configure Latency Timer */
267 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
269 /* Disable interrupt line, if device says it wants to use interrupts */
270 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
272 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
,
273 PCI_INTERRUPT_LINE_DISABLE
);
276 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &old_command
);
277 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
,
278 (old_command
& 0xffff0000) | command
);
287 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
288 unsigned short class,
295 struct pci_config_table
*table
;
297 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
298 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
299 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
300 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
301 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
302 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
303 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
311 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
313 struct pci_config_table
*entry
)
315 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1],
319 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
320 pci_dev_t dev
, struct pci_config_table
*entry
)
325 * HJF: Changed this to return int. I think this is required
326 * to get the correct result when scanning bridges
328 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
330 #ifdef CONFIG_PCI_SCAN_SHOW
331 __weak
int pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
333 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0))
338 #endif /* CONFIG_PCI_SCAN_SHOW */
340 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
342 unsigned int sub_bus
, found_multi
= 0;
343 unsigned short vendor
, device
, class;
344 unsigned char header_type
;
345 #ifndef CONFIG_PCI_PNP
346 struct pci_config_table
*cfg
;
349 #ifdef CONFIG_PCI_SCAN_SHOW
350 static int indent
= 0;
355 for (dev
= PCI_BDF(bus
,0,0);
356 dev
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
357 PCI_MAX_PCI_FUNCTIONS
- 1);
358 dev
+= PCI_BDF(0, 0, 1)) {
360 if (pci_skip_dev(hose
, dev
))
363 if (PCI_FUNC(dev
) && !found_multi
)
366 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
368 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
370 if (vendor
== 0xffff || vendor
== 0x0000)
374 found_multi
= header_type
& 0x80;
376 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
377 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
379 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
380 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
382 #ifdef CONFIG_PCI_FIXUP_DEV
383 board_pci_fixup_dev(hose
, dev
, vendor
, device
, class);
386 #ifdef CONFIG_PCI_SCAN_SHOW
389 /* Print leading space, including bus indentation */
390 printf("%*c", indent
+ 1, ' ');
392 if (pci_print_dev(hose
, dev
)) {
393 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
394 PCI_BUS(dev
), PCI_DEV(dev
), 6 - indent
, PCI_FUNC(dev
),
395 vendor
, device
, pci_class_str(class >> 8));
399 #ifdef CONFIG_PCI_PNP
400 sub_bus
= max((unsigned int)pciauto_config_device(hose
, dev
),
403 cfg
= pci_find_config(hose
, class, vendor
, device
,
404 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
406 cfg
->config_device(hose
, dev
, cfg
);
407 sub_bus
= max(sub_bus
,
408 (unsigned int)hose
->current_busno
);
412 #ifdef CONFIG_PCI_SCAN_SHOW
417 hose
->fixup_irq(hose
, dev
);
423 int pci_hose_scan(struct pci_controller
*hose
)
425 #if defined(CONFIG_PCI_BOOTDELAY)
429 if (!gd
->pcidelay_done
) {
430 /* wait "pcidelay" ms (if defined)... */
431 s
= getenv("pcidelay");
433 int val
= simple_strtoul(s
, NULL
, 10);
434 for (i
= 0; i
< val
; i
++)
437 gd
->pcidelay_done
= 1;
439 #endif /* CONFIG_PCI_BOOTDELAY */
441 #ifdef CONFIG_PCI_SCAN_SHOW
446 * Start scan at current_busno.
447 * PCIe will start scan at first_busno+1.
449 /* For legacy support, ensure current >= first */
450 if (hose
->first_busno
> hose
->current_busno
)
451 hose
->current_busno
= hose
->first_busno
;
452 #ifdef CONFIG_PCI_PNP
453 pciauto_config_init(hose
);
455 return pci_hose_scan_bus(hose
, hose
->current_busno
);
462 /* now call board specific pci_init()... */
466 /* Returns the address of the requested capability structure within the
467 * device's PCI configuration space or 0 in case the device does not
470 int pci_hose_find_capability(struct pci_controller
*hose
, pci_dev_t dev
,
476 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &hdr_type
);
478 pos
= pci_hose_find_cap_start(hose
, dev
, hdr_type
& 0x7F);
481 pos
= pci_find_cap(hose
, dev
, pos
, cap
);
486 /* Find the header pointer to the Capabilities*/
487 int pci_hose_find_cap_start(struct pci_controller
*hose
, pci_dev_t dev
,
492 pci_hose_read_config_word(hose
, dev
, PCI_STATUS
, &status
);
494 if (!(status
& PCI_STATUS_CAP_LIST
))
498 case PCI_HEADER_TYPE_NORMAL
:
499 case PCI_HEADER_TYPE_BRIDGE
:
500 return PCI_CAPABILITY_LIST
;
501 case PCI_HEADER_TYPE_CARDBUS
:
502 return PCI_CB_CAPABILITY_LIST
;
508 int pci_find_cap(struct pci_controller
*hose
, pci_dev_t dev
, int pos
, int cap
)
510 int ttl
= PCI_FIND_CAP_TTL
;
515 pci_hose_read_config_byte(hose
, dev
, pos
, &next_pos
);
516 if (next_pos
< CAP_START_POS
)
519 pos
= (int) next_pos
;
520 pci_hose_read_config_byte(hose
, dev
,
521 pos
+ PCI_CAP_LIST_ID
, &id
);
526 pos
+= PCI_CAP_LIST_NEXT
;
532 * pci_find_next_ext_capability - Find an extended capability
534 * Returns the address of the next matching extended capability structure
535 * within the device's PCI configuration space or 0 if the device does
536 * not support it. Some capabilities can occur several times, e.g., the
537 * vendor-specific capability, and this provides a way to find them all.
539 int pci_find_next_ext_capability(struct pci_controller
*hose
, pci_dev_t dev
,
543 int ttl
, pos
= PCI_CFG_SPACE_SIZE
;
545 /* minimum 8 bytes per capability */
546 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
551 pci_hose_read_config_dword(hose
, dev
, pos
, &header
);
552 if (header
== 0xffffffff || header
== 0)
556 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
559 pos
= PCI_EXT_CAP_NEXT(header
);
560 if (pos
< PCI_CFG_SPACE_SIZE
)
563 pci_hose_read_config_dword(hose
, dev
, pos
, &header
);
564 if (header
== 0xffffffff || header
== 0)
572 * pci_hose_find_ext_capability - Find an extended capability
574 * Returns the address of the requested extended capability structure
575 * within the device's PCI configuration space or 0 if the device does
578 int pci_hose_find_ext_capability(struct pci_controller
*hose
, pci_dev_t dev
,
581 return pci_find_next_ext_capability(hose
, dev
, 0, cap
);