2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
14 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
15 * and change pci-uclass.c.
22 #include <asm/processor.h>
26 DECLARE_GLOBAL_DATA_PTR
;
28 #define PCI_HOSE_OP(rw, size, type) \
29 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
31 int offset, type value) \
33 return hose->rw##_##size(hose, dev, offset, value); \
36 PCI_HOSE_OP(read
, byte
, u8
*)
37 PCI_HOSE_OP(read
, word
, u16
*)
38 PCI_HOSE_OP(read
, dword
, u32
*)
39 PCI_HOSE_OP(write
, byte
, u8
)
40 PCI_HOSE_OP(write
, word
, u16
)
41 PCI_HOSE_OP(write
, dword
, u32
)
43 #define PCI_OP(rw, size, type, error_code) \
44 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
46 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
54 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
57 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
58 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
59 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
60 PCI_OP(write
, byte
, u8
, )
61 PCI_OP(write
, word
, u16
, )
62 PCI_OP(write
, dword
, u32
, )
64 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
65 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
67 int offset, type val) \
71 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
76 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
81 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
82 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
84 int offset, type val) \
86 u32 val32, mask, ldata, shift; \
88 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
91 shift = ((offset & (int)off_mask) * 8); \
92 ldata = (((unsigned long)val) & val_mask) << shift; \
93 mask = val_mask << shift; \
94 val32 = (val32 & ~mask) | ldata; \
96 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
102 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
103 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
104 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
105 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
111 static struct pci_controller
* hose_head
;
113 struct pci_controller
*pci_get_hose_head(void)
121 void pci_register_hose(struct pci_controller
* hose
)
123 struct pci_controller
**phose
= &hose_head
;
126 phose
= &(*phose
)->next
;
133 struct pci_controller
*pci_bus_to_hose(int bus
)
135 struct pci_controller
*hose
;
137 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
138 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
142 printf("pci_bus_to_hose() failed\n");
146 struct pci_controller
*find_hose_by_cfg_addr(void *cfg_addr
)
148 struct pci_controller
*hose
;
150 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
151 if (hose
->cfg_addr
== cfg_addr
)
158 int pci_last_busno(void)
160 struct pci_controller
*hose
= pci_get_hose_head();
168 return hose
->last_busno
;
171 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
173 struct pci_controller
* hose
;
177 for (hose
= pci_get_hose_head(); hose
; hose
= hose
->next
) {
178 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
179 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--) {
181 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++) {
183 bdf
= pci_hose_find_devices(hose
, bus
, ids
, &index
);
192 int pci_hose_config_device(struct pci_controller
*hose
,
196 unsigned long command
)
199 unsigned int old_command
;
200 pci_addr_t bar_value
;
203 int bar
, found_mem64
;
205 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io
,
208 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, 0);
210 for (bar
= PCI_BASE_ADDRESS_0
; bar
<= PCI_BASE_ADDRESS_5
; bar
+= 4) {
211 pci_hose_write_config_dword(hose
, dev
, bar
, 0xffffffff);
212 pci_hose_read_config_dword(hose
, dev
, bar
, &bar_response
);
219 /* Check the BAR type and set our address mask */
220 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
221 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
222 /* round up region base address to a multiple of size */
223 io
= ((io
- 1) | (bar_size
- 1)) + 1;
225 /* compute new region base address */
228 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
229 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
230 u32 bar_response_upper
;
232 pci_hose_write_config_dword(hose
, dev
, bar
+ 4,
234 pci_hose_read_config_dword(hose
, dev
, bar
+ 4,
235 &bar_response_upper
);
237 bar64
= ((u64
)bar_response_upper
<< 32) | bar_response
;
239 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
242 bar_size
= (u32
)(~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1);
245 /* round up region base address to multiple of size */
246 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
248 /* compute new region base address */
249 mem
= mem
+ bar_size
;
252 /* Write it out and update our limit */
253 pci_hose_write_config_dword (hose
, dev
, bar
, (u32
)bar_value
);
257 #ifdef CONFIG_SYS_PCI_64BIT
258 pci_hose_write_config_dword(hose
, dev
, bar
,
259 (u32
)(bar_value
>> 32));
261 pci_hose_write_config_dword(hose
, dev
, bar
, 0x00000000);
266 /* Configure Cache Line Size Register */
267 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
269 /* Configure Latency Timer */
270 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
272 /* Disable interrupt line, if device says it wants to use interrupts */
273 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
275 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
,
276 PCI_INTERRUPT_LINE_DISABLE
);
279 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &old_command
);
280 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
,
281 (old_command
& 0xffff0000) | command
);
290 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
291 unsigned short class,
298 struct pci_config_table
*table
;
300 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
301 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
302 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
303 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
304 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
305 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
306 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
314 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
316 struct pci_config_table
*entry
)
318 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1],
322 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
323 pci_dev_t dev
, struct pci_config_table
*entry
)
328 * HJF: Changed this to return int. I think this is required
329 * to get the correct result when scanning bridges
331 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
333 #ifdef CONFIG_PCI_SCAN_SHOW
334 __weak
int pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
336 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0))
341 #endif /* CONFIG_PCI_SCAN_SHOW */
343 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
345 unsigned int sub_bus
, found_multi
= 0;
346 unsigned short vendor
, device
, class;
347 unsigned char header_type
;
348 #ifndef CONFIG_PCI_PNP
349 struct pci_config_table
*cfg
;
352 #ifdef CONFIG_PCI_SCAN_SHOW
353 static int indent
= 0;
358 for (dev
= PCI_BDF(bus
,0,0);
359 dev
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
360 PCI_MAX_PCI_FUNCTIONS
- 1);
361 dev
+= PCI_BDF(0, 0, 1)) {
363 if (pci_skip_dev(hose
, dev
))
366 if (PCI_FUNC(dev
) && !found_multi
)
369 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
371 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
373 if (vendor
== 0xffff || vendor
== 0x0000)
377 found_multi
= header_type
& 0x80;
379 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
380 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
382 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
383 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
385 #ifdef CONFIG_PCI_FIXUP_DEV
386 board_pci_fixup_dev(hose
, dev
, vendor
, device
, class);
389 #ifdef CONFIG_PCI_SCAN_SHOW
392 /* Print leading space, including bus indentation */
393 printf("%*c", indent
+ 1, ' ');
395 if (pci_print_dev(hose
, dev
)) {
396 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
397 PCI_BUS(dev
), PCI_DEV(dev
), 6 - indent
, PCI_FUNC(dev
),
398 vendor
, device
, pci_class_str(class >> 8));
402 #ifdef CONFIG_PCI_PNP
403 sub_bus
= max((unsigned int)pciauto_config_device(hose
, dev
),
406 cfg
= pci_find_config(hose
, class, vendor
, device
,
407 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
409 cfg
->config_device(hose
, dev
, cfg
);
410 sub_bus
= max(sub_bus
,
411 (unsigned int)hose
->current_busno
);
415 #ifdef CONFIG_PCI_SCAN_SHOW
420 hose
->fixup_irq(hose
, dev
);
426 int pci_hose_scan(struct pci_controller
*hose
)
428 #if defined(CONFIG_PCI_BOOTDELAY)
432 if (!gd
->pcidelay_done
) {
433 /* wait "pcidelay" ms (if defined)... */
434 s
= getenv("pcidelay");
436 int val
= simple_strtoul(s
, NULL
, 10);
437 for (i
= 0; i
< val
; i
++)
440 gd
->pcidelay_done
= 1;
442 #endif /* CONFIG_PCI_BOOTDELAY */
444 #ifdef CONFIG_PCI_SCAN_SHOW
449 * Start scan at current_busno.
450 * PCIe will start scan at first_busno+1.
452 /* For legacy support, ensure current >= first */
453 if (hose
->first_busno
> hose
->current_busno
)
454 hose
->current_busno
= hose
->first_busno
;
455 #ifdef CONFIG_PCI_PNP
456 pciauto_config_init(hose
);
458 return pci_hose_scan_bus(hose
, hose
->current_busno
);
465 /* now call board specific pci_init()... */
469 /* Returns the address of the requested capability structure within the
470 * device's PCI configuration space or 0 in case the device does not
473 int pci_hose_find_capability(struct pci_controller
*hose
, pci_dev_t dev
,
479 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &hdr_type
);
481 pos
= pci_hose_find_cap_start(hose
, dev
, hdr_type
& 0x7F);
484 pos
= pci_find_cap(hose
, dev
, pos
, cap
);
489 /* Find the header pointer to the Capabilities*/
490 int pci_hose_find_cap_start(struct pci_controller
*hose
, pci_dev_t dev
,
495 pci_hose_read_config_word(hose
, dev
, PCI_STATUS
, &status
);
497 if (!(status
& PCI_STATUS_CAP_LIST
))
501 case PCI_HEADER_TYPE_NORMAL
:
502 case PCI_HEADER_TYPE_BRIDGE
:
503 return PCI_CAPABILITY_LIST
;
504 case PCI_HEADER_TYPE_CARDBUS
:
505 return PCI_CB_CAPABILITY_LIST
;
511 int pci_find_cap(struct pci_controller
*hose
, pci_dev_t dev
, int pos
, int cap
)
513 int ttl
= PCI_FIND_CAP_TTL
;
518 pci_hose_read_config_byte(hose
, dev
, pos
, &next_pos
);
519 if (next_pos
< CAP_START_POS
)
522 pos
= (int) next_pos
;
523 pci_hose_read_config_byte(hose
, dev
,
524 pos
+ PCI_CAP_LIST_ID
, &id
);
529 pos
+= PCI_CAP_LIST_NEXT
;
535 * pci_find_next_ext_capability - Find an extended capability
537 * Returns the address of the next matching extended capability structure
538 * within the device's PCI configuration space or 0 if the device does
539 * not support it. Some capabilities can occur several times, e.g., the
540 * vendor-specific capability, and this provides a way to find them all.
542 int pci_find_next_ext_capability(struct pci_controller
*hose
, pci_dev_t dev
,
546 int ttl
, pos
= PCI_CFG_SPACE_SIZE
;
548 /* minimum 8 bytes per capability */
549 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
554 pci_hose_read_config_dword(hose
, dev
, pos
, &header
);
555 if (header
== 0xffffffff || header
== 0)
559 if (PCI_EXT_CAP_ID(header
) == cap
&& pos
!= start
)
562 pos
= PCI_EXT_CAP_NEXT(header
);
563 if (pos
< PCI_CFG_SPACE_SIZE
)
566 pci_hose_read_config_dword(hose
, dev
, pos
, &header
);
567 if (header
== 0xffffffff || header
== 0)
575 * pci_hose_find_ext_capability - Find an extended capability
577 * Returns the address of the requested extended capability structure
578 * within the device's PCI configuration space or 0 if the device does
581 int pci_hose_find_ext_capability(struct pci_controller
*hose
, pci_dev_t dev
,
584 return pci_find_next_ext_capability(hose
, dev
, 0, cap
);