2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/processor.h>
38 #define PCI_HOSE_OP(rw, size, type) \
39 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
41 int offset, type value) \
43 return hose->rw##_##size(hose, dev, offset, value); \
46 PCI_HOSE_OP(read
, byte
, u8
*)
47 PCI_HOSE_OP(read
, word
, u16
*)
48 PCI_HOSE_OP(read
, dword
, u32
*)
49 PCI_HOSE_OP(write
, byte
, u8
)
50 PCI_HOSE_OP(write
, word
, u16
)
51 PCI_HOSE_OP(write
, dword
, u32
)
53 #define PCI_OP(rw, size, type, error_code) \
54 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
56 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
64 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
67 PCI_OP(read
, byte
, u8
*, *value
= 0xff)
68 PCI_OP(read
, word
, u16
*, *value
= 0xffff)
69 PCI_OP(read
, dword
, u32
*, *value
= 0xffffffff)
70 PCI_OP(write
, byte
, u8
, )
71 PCI_OP(write
, word
, u16
, )
72 PCI_OP(write
, dword
, u32
, )
74 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
75 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
77 int offset, type val) \
81 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
86 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
91 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
92 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
94 int offset, type val) \
96 u32 val32, mask, ldata, shift; \
98 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
101 shift = ((offset & (int)off_mask) * 8); \
102 ldata = (((unsigned long)val) & val_mask) << shift; \
103 mask = val_mask << shift; \
104 val32 = (val32 & ~mask) | ldata; \
106 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
112 PCI_READ_VIA_DWORD_OP(byte
, u8
*, 0x03)
113 PCI_READ_VIA_DWORD_OP(word
, u16
*, 0x02)
114 PCI_WRITE_VIA_DWORD_OP(byte
, u8
, 0x03, 0x000000ff)
115 PCI_WRITE_VIA_DWORD_OP(word
, u16
, 0x02, 0x0000ffff)
117 /* Get a virtual address associated with a BAR region */
118 void *pci_map_bar(pci_dev_t pdev
, int bar
, int flags
)
120 pci_addr_t pci_bus_addr
;
123 /* read BAR address */
124 pci_read_config_dword(pdev
, bar
, &bar_response
);
125 pci_bus_addr
= (pci_addr_t
)(bar_response
& ~0xf);
128 * Pass "0" as the length argument to pci_bus_to_virt. The arg
129 * isn't actualy used on any platform because u-boot assumes a static
130 * linear mapping. In the future, this could read the BAR size
131 * and pass that as the size if needed.
133 return pci_bus_to_virt(pdev
, pci_bus_addr
, flags
, 0, MAP_NOCACHE
);
140 static struct pci_controller
* hose_head
;
142 void pci_register_hose(struct pci_controller
* hose
)
144 struct pci_controller
**phose
= &hose_head
;
147 phose
= &(*phose
)->next
;
154 struct pci_controller
*pci_bus_to_hose(int bus
)
156 struct pci_controller
*hose
;
158 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
159 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
163 printf("pci_bus_to_hose() failed\n");
167 struct pci_controller
*find_hose_by_cfg_addr(void *cfg_addr
)
169 struct pci_controller
*hose
;
171 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
172 if (hose
->cfg_addr
== cfg_addr
)
179 int pci_last_busno(void)
181 struct pci_controller
*hose
= hose_head
;
189 return hose
->last_busno
;
192 pci_dev_t
pci_find_devices(struct pci_device_id
*ids
, int index
)
194 struct pci_controller
* hose
;
198 int i
, bus
, found_multi
= 0;
200 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
201 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
202 for (bus
= hose
->last_busno
; bus
>= hose
->first_busno
; bus
--)
204 for (bus
= hose
->first_busno
; bus
<= hose
->last_busno
; bus
++)
206 for (bdf
= PCI_BDF(bus
, 0, 0);
207 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
208 bdf
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
209 PCI_MAX_PCI_FUNCTIONS
- 1);
211 bdf
< PCI_BDF(bus
+ 1, 0, 0);
213 bdf
+= PCI_BDF(0, 0, 1)) {
214 if (!PCI_FUNC(bdf
)) {
215 pci_read_config_byte(bdf
,
219 found_multi
= header_type
& 0x80;
225 pci_read_config_word(bdf
,
228 pci_read_config_word(bdf
,
232 for (i
= 0; ids
[i
].vendor
!= 0; i
++) {
233 if (vendor
== ids
[i
].vendor
&&
234 device
== ids
[i
].device
) {
247 pci_dev_t
pci_find_device(unsigned int vendor
, unsigned int device
, int index
)
249 static struct pci_device_id ids
[2] = {{}, {0, 0}};
251 ids
[0].vendor
= vendor
;
252 ids
[0].device
= device
;
254 return pci_find_devices(ids
, index
);
261 int __pci_hose_phys_to_bus(struct pci_controller
*hose
,
262 phys_addr_t phys_addr
,
264 unsigned long skip_mask
,
267 struct pci_region
*res
;
271 for (i
= 0; i
< hose
->region_count
; i
++) {
272 res
= &hose
->regions
[i
];
274 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
277 if (res
->flags
& skip_mask
)
280 bus_addr
= phys_addr
- res
->phys_start
+ res
->bus_start
;
282 if (bus_addr
>= res
->bus_start
&&
283 bus_addr
< res
->bus_start
+ res
->size
) {
292 pci_addr_t
pci_hose_phys_to_bus (struct pci_controller
*hose
,
293 phys_addr_t phys_addr
,
296 pci_addr_t bus_addr
= 0;
300 puts("pci_hose_phys_to_bus: invalid hose\n");
305 * if PCI_REGION_MEM is set we do a two pass search with preference
306 * on matches that don't have PCI_REGION_SYS_MEMORY set
308 if ((flags
& PCI_REGION_MEM
) == PCI_REGION_MEM
) {
309 ret
= __pci_hose_phys_to_bus(hose
, phys_addr
,
310 flags
, PCI_REGION_SYS_MEMORY
, &bus_addr
);
315 ret
= __pci_hose_phys_to_bus(hose
, phys_addr
, flags
, 0, &bus_addr
);
318 puts("pci_hose_phys_to_bus: invalid physical address\n");
323 int __pci_hose_bus_to_phys(struct pci_controller
*hose
,
326 unsigned long skip_mask
,
329 struct pci_region
*res
;
332 for (i
= 0; i
< hose
->region_count
; i
++) {
333 res
= &hose
->regions
[i
];
335 if (((res
->flags
^ flags
) & PCI_REGION_TYPE
) != 0)
338 if (res
->flags
& skip_mask
)
341 if (bus_addr
>= res
->bus_start
&&
342 bus_addr
< res
->bus_start
+ res
->size
) {
343 *pa
= (bus_addr
- res
->bus_start
+ res
->phys_start
);
351 phys_addr_t
pci_hose_bus_to_phys(struct pci_controller
* hose
,
355 phys_addr_t phys_addr
= 0;
359 puts("pci_hose_bus_to_phys: invalid hose\n");
364 * if PCI_REGION_MEM is set we do a two pass search with preference
365 * on matches that don't have PCI_REGION_SYS_MEMORY set
367 if ((flags
& PCI_REGION_MEM
) == PCI_REGION_MEM
) {
368 ret
= __pci_hose_bus_to_phys(hose
, bus_addr
,
369 flags
, PCI_REGION_SYS_MEMORY
, &phys_addr
);
374 ret
= __pci_hose_bus_to_phys(hose
, bus_addr
, flags
, 0, &phys_addr
);
377 puts("pci_hose_bus_to_phys: invalid physical address\n");
386 int pci_hose_config_device(struct pci_controller
*hose
,
390 unsigned long command
)
393 unsigned int old_command
;
394 pci_addr_t bar_value
;
397 int bar
, found_mem64
;
399 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io
,
402 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
, 0);
404 for (bar
= PCI_BASE_ADDRESS_0
; bar
<= PCI_BASE_ADDRESS_5
; bar
+= 4) {
405 pci_hose_write_config_dword(hose
, dev
, bar
, 0xffffffff);
406 pci_hose_read_config_dword(hose
, dev
, bar
, &bar_response
);
413 /* Check the BAR type and set our address mask */
414 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
415 bar_size
= ~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
) + 1;
416 /* round up region base address to a multiple of size */
417 io
= ((io
- 1) | (bar_size
- 1)) + 1;
419 /* compute new region base address */
422 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
423 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
424 u32 bar_response_upper
;
426 pci_hose_write_config_dword(hose
, dev
, bar
+ 4,
428 pci_hose_read_config_dword(hose
, dev
, bar
+ 4,
429 &bar_response_upper
);
431 bar64
= ((u64
)bar_response_upper
<< 32) | bar_response
;
433 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
) + 1;
436 bar_size
= (u32
)(~(bar_response
& PCI_BASE_ADDRESS_MEM_MASK
) + 1);
439 /* round up region base address to multiple of size */
440 mem
= ((mem
- 1) | (bar_size
- 1)) + 1;
442 /* compute new region base address */
443 mem
= mem
+ bar_size
;
446 /* Write it out and update our limit */
447 pci_hose_write_config_dword (hose
, dev
, bar
, (u32
)bar_value
);
451 #ifdef CONFIG_SYS_PCI_64BIT
452 pci_hose_write_config_dword(hose
, dev
, bar
,
453 (u32
)(bar_value
>> 32));
455 pci_hose_write_config_dword(hose
, dev
, bar
, 0x00000000);
460 /* Configure Cache Line Size Register */
461 pci_hose_write_config_byte(hose
, dev
, PCI_CACHE_LINE_SIZE
, 0x08);
463 /* Configure Latency Timer */
464 pci_hose_write_config_byte(hose
, dev
, PCI_LATENCY_TIMER
, 0x80);
466 /* Disable interrupt line, if device says it wants to use interrupts */
467 pci_hose_read_config_byte(hose
, dev
, PCI_INTERRUPT_PIN
, &pin
);
469 pci_hose_write_config_byte(hose
, dev
, PCI_INTERRUPT_LINE
, 0xff);
472 pci_hose_read_config_dword(hose
, dev
, PCI_COMMAND
, &old_command
);
473 pci_hose_write_config_dword(hose
, dev
, PCI_COMMAND
,
474 (old_command
& 0xffff0000) | command
);
483 struct pci_config_table
*pci_find_config(struct pci_controller
*hose
,
484 unsigned short class,
491 struct pci_config_table
*table
;
493 for (table
= hose
->config_table
; table
&& table
->vendor
; table
++) {
494 if ((table
->vendor
== PCI_ANY_ID
|| table
->vendor
== vendor
) &&
495 (table
->device
== PCI_ANY_ID
|| table
->device
== device
) &&
496 (table
->class == PCI_ANY_ID
|| table
->class == class) &&
497 (table
->bus
== PCI_ANY_ID
|| table
->bus
== bus
) &&
498 (table
->dev
== PCI_ANY_ID
|| table
->dev
== dev
) &&
499 (table
->func
== PCI_ANY_ID
|| table
->func
== func
)) {
507 void pci_cfgfunc_config_device(struct pci_controller
*hose
,
509 struct pci_config_table
*entry
)
511 pci_hose_config_device(hose
, dev
, entry
->priv
[0], entry
->priv
[1],
515 void pci_cfgfunc_do_nothing(struct pci_controller
*hose
,
516 pci_dev_t dev
, struct pci_config_table
*entry
)
521 * HJF: Changed this to return int. I think this is required
522 * to get the correct result when scanning bridges
524 extern int pciauto_config_device(struct pci_controller
*hose
, pci_dev_t dev
);
526 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
527 const char * pci_class_str(u8
class)
530 case PCI_CLASS_NOT_DEFINED
:
531 return "Build before PCI Rev2.0";
533 case PCI_BASE_CLASS_STORAGE
:
534 return "Mass storage controller";
536 case PCI_BASE_CLASS_NETWORK
:
537 return "Network controller";
539 case PCI_BASE_CLASS_DISPLAY
:
540 return "Display controller";
542 case PCI_BASE_CLASS_MULTIMEDIA
:
543 return "Multimedia device";
545 case PCI_BASE_CLASS_MEMORY
:
546 return "Memory controller";
548 case PCI_BASE_CLASS_BRIDGE
:
549 return "Bridge device";
551 case PCI_BASE_CLASS_COMMUNICATION
:
552 return "Simple comm. controller";
554 case PCI_BASE_CLASS_SYSTEM
:
555 return "Base system peripheral";
557 case PCI_BASE_CLASS_INPUT
:
558 return "Input device";
560 case PCI_BASE_CLASS_DOCKING
:
561 return "Docking station";
563 case PCI_BASE_CLASS_PROCESSOR
:
566 case PCI_BASE_CLASS_SERIAL
:
567 return "Serial bus controller";
569 case PCI_BASE_CLASS_INTELLIGENT
:
570 return "Intelligent controller";
572 case PCI_BASE_CLASS_SATELLITE
:
573 return "Satellite controller";
575 case PCI_BASE_CLASS_CRYPT
:
576 return "Cryptographic device";
578 case PCI_BASE_CLASS_SIGNAL_PROCESSING
:
581 case PCI_CLASS_OTHERS
:
582 return "Does not fit any class";
589 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
591 int __pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
594 * Check if pci device should be skipped in configuration
596 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0)) {
597 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
599 * Only skip configuration if "pciconfighost" is not set
601 if (getenv("pciconfighost") == NULL
)
610 int pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
611 __attribute__((weak
, alias("__pci_skip_dev")));
613 #ifdef CONFIG_PCI_SCAN_SHOW
614 int __pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
616 if (dev
== PCI_BDF(hose
->first_busno
, 0, 0))
621 int pci_print_dev(struct pci_controller
*hose
, pci_dev_t dev
)
622 __attribute__((weak
, alias("__pci_print_dev")));
623 #endif /* CONFIG_PCI_SCAN_SHOW */
625 int pci_hose_scan_bus(struct pci_controller
*hose
, int bus
)
627 unsigned int sub_bus
, found_multi
= 0;
628 unsigned short vendor
, device
, class;
629 unsigned char header_type
;
630 #ifndef CONFIG_PCI_PNP
631 struct pci_config_table
*cfg
;
634 #ifdef CONFIG_PCI_SCAN_SHOW
635 static int indent
= 0;
640 for (dev
= PCI_BDF(bus
,0,0);
641 dev
< PCI_BDF(bus
, PCI_MAX_PCI_DEVICES
- 1,
642 PCI_MAX_PCI_FUNCTIONS
- 1);
643 dev
+= PCI_BDF(0, 0, 1)) {
645 if (pci_skip_dev(hose
, dev
))
648 if (PCI_FUNC(dev
) && !found_multi
)
651 pci_hose_read_config_byte(hose
, dev
, PCI_HEADER_TYPE
, &header_type
);
653 pci_hose_read_config_word(hose
, dev
, PCI_VENDOR_ID
, &vendor
);
655 if (vendor
== 0xffff || vendor
== 0x0000)
659 found_multi
= header_type
& 0x80;
661 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
662 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
664 pci_hose_read_config_word(hose
, dev
, PCI_DEVICE_ID
, &device
);
665 pci_hose_read_config_word(hose
, dev
, PCI_CLASS_DEVICE
, &class);
667 #ifdef CONFIG_PCI_SCAN_SHOW
670 /* Print leading space, including bus indentation */
671 printf("%*c", indent
+ 1, ' ');
673 if (pci_print_dev(hose
, dev
)) {
674 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
675 PCI_BUS(dev
), PCI_DEV(dev
), 6 - indent
, PCI_FUNC(dev
),
676 vendor
, device
, pci_class_str(class >> 8));
680 #ifdef CONFIG_PCI_PNP
681 sub_bus
= max(pciauto_config_device(hose
, dev
), sub_bus
);
683 cfg
= pci_find_config(hose
, class, vendor
, device
,
684 PCI_BUS(dev
), PCI_DEV(dev
), PCI_FUNC(dev
));
686 cfg
->config_device(hose
, dev
, cfg
);
687 sub_bus
= max(sub_bus
, hose
->current_busno
);
691 #ifdef CONFIG_PCI_SCAN_SHOW
696 hose
->fixup_irq(hose
, dev
);
702 int pci_hose_scan(struct pci_controller
*hose
)
704 #if defined(CONFIG_PCI_BOOTDELAY)
705 static int pcidelay_done
;
709 if (!pcidelay_done
) {
710 /* wait "pcidelay" ms (if defined)... */
711 s
= getenv("pcidelay");
713 int val
= simple_strtoul(s
, NULL
, 10);
714 for (i
= 0; i
< val
; i
++)
719 #endif /* CONFIG_PCI_BOOTDELAY */
722 * Start scan at current_busno.
723 * PCIe will start scan at first_busno+1.
725 /* For legacy support, ensure current >= first */
726 if (hose
->first_busno
> hose
->current_busno
)
727 hose
->current_busno
= hose
->first_busno
;
728 #ifdef CONFIG_PCI_PNP
729 pciauto_config_init(hose
);
731 return pci_hose_scan_bus(hose
, hose
->current_busno
);
738 /* now call board specific pci_init()... */