2 * PCI autoconfiguration library
4 * Author: Matt Porter <mporter@mvista.com>
6 * Copyright 2000 MontaVista Software Inc.
8 * SPDX-License-Identifier: GPL-2.0+
16 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
17 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
18 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
21 void dm_pciauto_setup_device(struct udevice
*dev
, int bars_num
,
22 struct pci_region
*mem
,
23 struct pci_region
*prefetch
, struct pci_region
*io
,
33 struct pci_region
*bar_res
= NULL
;
37 dm_pci_read_config16(dev
, PCI_COMMAND
, &cmdstat
);
38 cmdstat
= (cmdstat
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) |
41 for (bar
= PCI_BASE_ADDRESS_0
;
42 bar
< PCI_BASE_ADDRESS_0
+ (bars_num
* 4); bar
+= 4) {
43 /* Tickle the BAR and get the response */
45 dm_pci_write_config32(dev
, bar
, 0xffffffff);
46 dm_pci_read_config32(dev
, bar
, &bar_response
);
48 /* If BAR is not implemented go to the next BAR */
54 /* Check the BAR type and set our address mask */
55 if (bar_response
& PCI_BASE_ADDRESS_SPACE
) {
56 bar_size
= ((~(bar_response
& PCI_BASE_ADDRESS_IO_MASK
))
61 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
62 bar_nr
, (unsigned long long)bar_size
);
64 if ((bar_response
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
) ==
65 PCI_BASE_ADDRESS_MEM_TYPE_64
) {
66 u32 bar_response_upper
;
70 dm_pci_write_config32(dev
, bar
+ 4,
73 dm_pci_read_config32(dev
, bar
+ 4,
76 bar64
= ((u64
)bar_response_upper
<< 32) |
79 bar_size
= ~(bar64
& PCI_BASE_ADDRESS_MEM_MASK
)
84 bar_size
= (u32
)(~(bar_response
&
85 PCI_BASE_ADDRESS_MEM_MASK
) + 1);
88 if (prefetch
&& (bar_response
&
89 PCI_BASE_ADDRESS_MEM_PREFETCH
)) {
96 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
97 bar_nr
, bar_res
== prefetch
? "Prf" : "Mem",
98 (unsigned long long)bar_size
);
101 if (!enum_only
&& pciauto_region_allocate(bar_res
, bar_size
,
103 /* Write it out and update our limit */
104 dm_pci_write_config32(dev
, bar
, (u32
)bar_value
);
108 #ifdef CONFIG_SYS_PCI_64BIT
109 dm_pci_write_config32(dev
, bar
,
110 (u32
)(bar_value
>> 32));
113 * If we are a 64-bit decoder then increment to
114 * the upper 32 bits of the bar and force it to
115 * locate in the lower 4GB of memory.
117 dm_pci_write_config32(dev
, bar
, 0x00000000);
122 cmdstat
|= (bar_response
& PCI_BASE_ADDRESS_SPACE
) ?
123 PCI_COMMAND_IO
: PCI_COMMAND_MEMORY
;
131 /* Configure the expansion ROM address */
132 dm_pci_read_config8(dev
, PCI_HEADER_TYPE
, &header_type
);
134 if (header_type
!= PCI_HEADER_TYPE_CARDBUS
) {
135 rom_addr
= (header_type
== PCI_HEADER_TYPE_NORMAL
) ?
136 PCI_ROM_ADDRESS
: PCI_ROM_ADDRESS1
;
137 dm_pci_write_config32(dev
, rom_addr
, 0xfffffffe);
138 dm_pci_read_config32(dev
, rom_addr
, &bar_response
);
140 bar_size
= -(bar_response
& ~1);
141 debug("PCI Autoconfig: ROM, size=%#x, ",
142 (unsigned int)bar_size
);
143 if (pciauto_region_allocate(mem
, bar_size
,
145 dm_pci_write_config32(dev
, rom_addr
,
148 cmdstat
|= PCI_COMMAND_MEMORY
;
154 /* PCI_COMMAND_IO must be set for VGA device */
155 dm_pci_read_config16(dev
, PCI_CLASS_DEVICE
, &class);
156 if (class == PCI_CLASS_DISPLAY_VGA
)
157 cmdstat
|= PCI_COMMAND_IO
;
159 dm_pci_write_config16(dev
, PCI_COMMAND
, cmdstat
);
160 dm_pci_write_config8(dev
, PCI_CACHE_LINE_SIZE
,
161 CONFIG_SYS_PCI_CACHE_LINE_SIZE
);
162 dm_pci_write_config8(dev
, PCI_LATENCY_TIMER
, 0x80);
165 void dm_pciauto_prescan_setup_bridge(struct udevice
*dev
, int sub_bus
)
167 struct pci_region
*pci_mem
;
168 struct pci_region
*pci_prefetch
;
169 struct pci_region
*pci_io
;
170 u16 cmdstat
, prefechable_64
;
171 struct udevice
*ctlr
= pci_get_controller(dev
);
172 struct pci_controller
*ctlr_hose
= dev_get_uclass_priv(ctlr
);
174 pci_mem
= ctlr_hose
->pci_mem
;
175 pci_prefetch
= ctlr_hose
->pci_prefetch
;
176 pci_io
= ctlr_hose
->pci_io
;
178 dm_pci_read_config16(dev
, PCI_COMMAND
, &cmdstat
);
179 dm_pci_read_config16(dev
, PCI_PREF_MEMORY_BASE
, &prefechable_64
);
180 prefechable_64
&= PCI_PREF_RANGE_TYPE_MASK
;
182 /* Configure bus number registers */
183 dm_pci_write_config8(dev
, PCI_PRIMARY_BUS
,
184 PCI_BUS(dm_pci_get_bdf(dev
)));
185 dm_pci_write_config8(dev
, PCI_SECONDARY_BUS
, sub_bus
);
186 dm_pci_write_config8(dev
, PCI_SUBORDINATE_BUS
, 0xff);
189 /* Round memory allocator to 1MB boundary */
190 pciauto_region_align(pci_mem
, 0x100000);
193 * Set up memory and I/O filter limits, assume 32-bit
196 dm_pci_write_config16(dev
, PCI_MEMORY_BASE
,
197 (pci_mem
->bus_lower
& 0xfff00000) >> 16);
199 cmdstat
|= PCI_COMMAND_MEMORY
;
203 /* Round memory allocator to 1MB boundary */
204 pciauto_region_align(pci_prefetch
, 0x100000);
207 * Set up memory and I/O filter limits, assume 32-bit
210 dm_pci_write_config16(dev
, PCI_PREF_MEMORY_BASE
,
211 (pci_prefetch
->bus_lower
& 0xfff00000) >> 16);
212 if (prefechable_64
== PCI_PREF_RANGE_TYPE_64
)
213 #ifdef CONFIG_SYS_PCI_64BIT
214 dm_pci_write_config32(dev
, PCI_PREF_BASE_UPPER32
,
215 pci_prefetch
->bus_lower
>> 32);
217 dm_pci_write_config32(dev
, PCI_PREF_BASE_UPPER32
, 0x0);
220 cmdstat
|= PCI_COMMAND_MEMORY
;
222 /* We don't support prefetchable memory for now, so disable */
223 dm_pci_write_config16(dev
, PCI_PREF_MEMORY_BASE
, 0x1000);
224 dm_pci_write_config16(dev
, PCI_PREF_MEMORY_LIMIT
, 0x0);
225 if (prefechable_64
== PCI_PREF_RANGE_TYPE_64
) {
226 dm_pci_write_config16(dev
, PCI_PREF_BASE_UPPER32
, 0x0);
227 dm_pci_write_config16(dev
, PCI_PREF_LIMIT_UPPER32
, 0x0);
232 /* Round I/O allocator to 4KB boundary */
233 pciauto_region_align(pci_io
, 0x1000);
235 dm_pci_write_config8(dev
, PCI_IO_BASE
,
236 (pci_io
->bus_lower
& 0x0000f000) >> 8);
237 dm_pci_write_config16(dev
, PCI_IO_BASE_UPPER16
,
238 (pci_io
->bus_lower
& 0xffff0000) >> 16);
240 cmdstat
|= PCI_COMMAND_IO
;
243 /* Enable memory and I/O accesses, enable bus master */
244 dm_pci_write_config16(dev
, PCI_COMMAND
, cmdstat
| PCI_COMMAND_MASTER
);
247 void dm_pciauto_postscan_setup_bridge(struct udevice
*dev
, int sub_bus
)
249 struct pci_region
*pci_mem
;
250 struct pci_region
*pci_prefetch
;
251 struct pci_region
*pci_io
;
252 struct udevice
*ctlr
= pci_get_controller(dev
);
253 struct pci_controller
*ctlr_hose
= dev_get_uclass_priv(ctlr
);
255 pci_mem
= ctlr_hose
->pci_mem
;
256 pci_prefetch
= ctlr_hose
->pci_prefetch
;
257 pci_io
= ctlr_hose
->pci_io
;
259 /* Configure bus number registers */
260 dm_pci_write_config8(dev
, PCI_SUBORDINATE_BUS
, sub_bus
);
263 /* Round memory allocator to 1MB boundary */
264 pciauto_region_align(pci_mem
, 0x100000);
266 dm_pci_write_config16(dev
, PCI_MEMORY_LIMIT
,
267 (pci_mem
->bus_lower
- 1) >> 16);
273 dm_pci_read_config16(dev
, PCI_PREF_MEMORY_LIMIT
,
275 prefechable_64
&= PCI_PREF_RANGE_TYPE_MASK
;
277 /* Round memory allocator to 1MB boundary */
278 pciauto_region_align(pci_prefetch
, 0x100000);
280 dm_pci_write_config16(dev
, PCI_PREF_MEMORY_LIMIT
,
281 (pci_prefetch
->bus_lower
- 1) >> 16);
282 if (prefechable_64
== PCI_PREF_RANGE_TYPE_64
)
283 #ifdef CONFIG_SYS_PCI_64BIT
284 dm_pci_write_config32(dev
, PCI_PREF_LIMIT_UPPER32
,
285 (pci_prefetch
->bus_lower
- 1) >> 32);
287 dm_pci_write_config32(dev
, PCI_PREF_LIMIT_UPPER32
, 0x0);
292 /* Round I/O allocator to 4KB boundary */
293 pciauto_region_align(pci_io
, 0x1000);
295 dm_pci_write_config8(dev
, PCI_IO_LIMIT
,
296 ((pci_io
->bus_lower
- 1) & 0x0000f000) >> 8);
297 dm_pci_write_config16(dev
, PCI_IO_LIMIT_UPPER16
,
298 ((pci_io
->bus_lower
- 1) & 0xffff0000) >> 16);
303 * HJF: Changed this to return int. I think this is required
304 * to get the correct result when scanning bridges
306 int dm_pciauto_config_device(struct udevice
*dev
)
308 struct pci_region
*pci_mem
;
309 struct pci_region
*pci_prefetch
;
310 struct pci_region
*pci_io
;
311 unsigned int sub_bus
= PCI_BUS(dm_pci_get_bdf(dev
));
312 unsigned short class;
313 bool enum_only
= false;
314 struct udevice
*ctlr
= pci_get_controller(dev
);
315 struct pci_controller
*ctlr_hose
= dev_get_uclass_priv(ctlr
);
318 #ifdef CONFIG_PCI_ENUM_ONLY
322 pci_mem
= ctlr_hose
->pci_mem
;
323 pci_prefetch
= ctlr_hose
->pci_prefetch
;
324 pci_io
= ctlr_hose
->pci_io
;
326 dm_pci_read_config16(dev
, PCI_CLASS_DEVICE
, &class);
329 case PCI_CLASS_BRIDGE_PCI
:
330 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
331 PCI_DEV(dm_pci_get_bdf(dev
)));
333 dm_pciauto_setup_device(dev
, 2, pci_mem
, pci_prefetch
, pci_io
,
336 n
= dm_pci_hose_probe_bus(dev
);
339 sub_bus
= (unsigned int)n
;
342 case PCI_CLASS_BRIDGE_CARDBUS
:
344 * just do a minimal setup of the bridge,
345 * let the OS take care of the rest
347 dm_pciauto_setup_device(dev
, 0, pci_mem
, pci_prefetch
, pci_io
,
350 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
351 PCI_DEV(dm_pci_get_bdf(dev
)));
355 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
356 case PCI_CLASS_BRIDGE_OTHER
:
357 debug("PCI Autoconfig: Skipping bridge device %d\n",
358 PCI_DEV(dm_pci_get_bdf(dev
)));
361 #if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
362 case PCI_CLASS_BRIDGE_OTHER
:
364 * The host/PCI bridge 1 seems broken in 8349 - it presents
365 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
366 * device claiming resources io/mem/irq.. we only allow for
367 * the PIMMR window to be allocated (BAR0 - 1MB size)
369 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
370 dm_pciauto_setup_device(dev
, 0, hose
->pci_mem
,
371 hose
->pci_prefetch
, hose
->pci_io
,
376 case PCI_CLASS_PROCESSOR_POWERPC
: /* an agent or end-point */
377 debug("PCI AutoConfig: Found PowerPC device\n");
381 dm_pciauto_setup_device(dev
, 6, pci_mem
, pci_prefetch
, pci_io
,