1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
5 * Based on the Linux implementation.
6 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
7 * Authors: Carsten Langgaard <carstenl@mips.com>
8 * Maciej W. Rozycki <macro@mips.com>
14 #include <pci_gt64120.h>
18 #define PCI_ACCESS_READ 0
19 #define PCI_ACCESS_WRITE 1
29 struct gt64120_pci_controller
{
30 struct pci_controller hose
;
31 struct gt64120_regs
*regs
;
34 static inline struct gt64120_pci_controller
*
35 hose_to_gt64120(struct pci_controller
*hose
)
37 return container_of(hose
, struct gt64120_pci_controller
, hose
);
40 #define GT_INTRCAUSE_ABORT_BITS \
41 (GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
43 static int gt_config_access(struct gt64120_pci_controller
*gt
,
44 unsigned char access_type
, pci_dev_t bdf
,
47 unsigned int bus
= PCI_BUS(bdf
);
48 unsigned int dev
= PCI_DEV(bdf
);
49 unsigned int devfn
= PCI_DEV(bdf
) << 3 | PCI_FUNC(bdf
);
54 if (bus
== 0 && dev
>= 31) {
55 /* Because of a bug in the galileo (for slot 31). */
59 if (access_type
== PCI_ACCESS_WRITE
)
60 debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
61 PCI_BUS(bdf
), PCI_DEV(bdf
), PCI_FUNC(bdf
), where
, *data
);
63 /* Clear cause register bits */
64 writel(~GT_INTRCAUSE_ABORT_BITS
, >
->regs
->intrcause
);
66 addr
= GT_PCI0_CFGADDR_CONFIGEN_BIT
;
67 addr
|= bus
<< GT_PCI0_CFGADDR_BUSNUM_SHF
;
68 addr
|= devfn
<< GT_PCI0_CFGADDR_FUNCTNUM_SHF
;
69 addr
|= (where
/ 4) << GT_PCI0_CFGADDR_REGNUM_SHF
;
72 writel(addr
, >
->regs
->pci0_cfgaddr
);
74 if (access_type
== PCI_ACCESS_WRITE
) {
75 if (bus
== 0 && dev
== 0) {
77 * The Galileo system controller is acting
78 * differently than other devices.
82 val
= cpu_to_le32(*data
);
85 writel(val
, >
->regs
->pci0_cfgdata
);
87 val
= readl(>
->regs
->pci0_cfgdata
);
89 if (bus
== 0 && dev
== 0) {
91 * The Galileo system controller is acting
92 * differently than other devices.
96 *data
= le32_to_cpu(val
);
100 /* Check for master or target abort */
101 intr
= readl(>
->regs
->intrcause
);
102 if (intr
& GT_INTRCAUSE_ABORT_BITS
) {
103 /* Error occurred, clear abort bits */
104 writel(~GT_INTRCAUSE_ABORT_BITS
, >
->regs
->intrcause
);
108 if (access_type
== PCI_ACCESS_READ
)
109 debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
110 PCI_BUS(bdf
), PCI_DEV(bdf
), PCI_FUNC(bdf
), where
, *data
);
115 static int gt_read_config_dword(struct pci_controller
*hose
, pci_dev_t dev
,
116 int where
, u32
*value
)
118 struct gt64120_pci_controller
*gt
= hose_to_gt64120(hose
);
121 return gt_config_access(gt
, PCI_ACCESS_READ
, dev
, where
, value
);
124 static int gt_write_config_dword(struct pci_controller
*hose
, pci_dev_t dev
,
125 int where
, u32 value
)
127 struct gt64120_pci_controller
*gt
= hose_to_gt64120(hose
);
130 return gt_config_access(gt
, PCI_ACCESS_WRITE
, dev
, where
, &data
);
133 void gt64120_pci_init(void *regs
, unsigned long sys_bus
, unsigned long sys_phys
,
134 unsigned long sys_size
, unsigned long mem_bus
,
135 unsigned long mem_phys
, unsigned long mem_size
,
136 unsigned long io_bus
, unsigned long io_phys
,
137 unsigned long io_size
)
139 static struct gt64120_pci_controller global_gt
;
140 struct gt64120_pci_controller
*gt
;
141 struct pci_controller
*hose
;
148 hose
->first_busno
= 0;
149 hose
->last_busno
= 0;
151 /* System memory space */
152 pci_set_region(&hose
->regions
[0], sys_bus
, sys_phys
, sys_size
,
153 PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
155 /* PCI memory space */
156 pci_set_region(&hose
->regions
[1], mem_bus
, mem_phys
, mem_size
,
160 pci_set_region(&hose
->regions
[2], io_bus
, io_phys
, io_size
,
163 hose
->region_count
= 3;
166 pci_hose_read_config_byte_via_dword
,
167 pci_hose_read_config_word_via_dword
,
168 gt_read_config_dword
,
169 pci_hose_write_config_byte_via_dword
,
170 pci_hose_write_config_word_via_dword
,
171 gt_write_config_dword
);
173 pci_register_hose(hose
);
174 hose
->last_busno
= pci_hose_scan(hose
);