3 * (C) Copyright 2004 eslab.whut.edu.cn
4 * Yue Hu(huyue_whut@yahoo.com.cn), Ligong Xue(lgxue@hotmail.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
30 #include <asm/arch/ixp425.h>
31 #include <asm/arch/ixp425pci.h>
33 static void non_prefetch_read (unsigned int addr
, unsigned int cmd
,
35 static void non_prefetch_write (unsigned int addr
, unsigned int cmd
,
37 static void configure_pins (void);
38 static void sys_pci_gpio_clock_config (void);
39 static void pci_bus_scan (void);
40 static int pci_device_exists (unsigned int deviceNo
);
41 static void sys_pci_bar_info_get (unsigned int devnum
, unsigned int bus
,
42 unsigned int dev
, unsigned int func
);
43 static void sys_pci_device_bars_write (void);
44 static void calc_bars (PciBar
* Bars
[], unsigned int nBars
,
45 unsigned int startAddr
);
47 #define PCI_MEMORY_BUS 0x00000000
48 #define PCI_MEMORY_PHY 0x48000000
49 #define PCI_MEMORY_SIZE 0x04000000
51 #define PCI_MEM_BUS 0x40000000
52 #define PCI_MEM_PHY 0x00000000
53 #define PCI_MEM_SIZE 0x04000000
55 #define PCI_IO_BUS 0x40000000
56 #define PCI_IO_PHY 0x50000000
57 #define PCI_IO_SIZE 0x10000000
59 struct pci_controller hose
;
61 unsigned int nDevices
;
64 PciBar
*memBars
[IXP425_PCI_MAX_BAR
];
65 PciBar
*ioBars
[IXP425_PCI_MAX_BAR
];
66 PciDevice devices
[IXP425_PCI_MAX_FUNC_ON_BUS
];
68 int pci_read_config_dword (pci_dev_t dev
, int where
, unsigned int *val
)
73 /*address bits 31:28 specify the device 10:8 specify the function */
74 /*Set the address to be read */
75 addr
= BIT ((31 - dev
)) | (where
& ~3);
76 non_prefetch_read (addr
, NP_CMD_CONFIGREAD
, &retval
);
83 int pci_read_config_word (pci_dev_t dev
, int where
, unsigned short *val
)
88 unsigned int byteEnables
;
91 /*byte enables are 4 bits active low, the position of each
92 bit maps to the byte that it enables */
94 (~(BIT (n
) | BIT ((n
+ 1)))) &
95 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK
;
96 byteEnables
= byteEnables
<< PCI_NP_CBE_BESL
;
97 /*address bits 31:28 specify the device 10:8 specify the function */
98 /*Set the address to be read */
99 addr
= BIT ((31 - dev
)) | (where
& ~3);
100 non_prefetch_read (addr
, byteEnables
| NP_CMD_CONFIGREAD
, &retval
);
102 /*Pick out the word we are interested in */
103 *val
= (retval
>> (8 * n
));
108 int pci_read_config_byte (pci_dev_t dev
, int where
, unsigned char *val
)
112 unsigned int byteEnables
;
116 /*byte enables are 4 bits, active low, the position of each
117 bit maps to the byte that it enables */
118 byteEnables
= (~BIT (n
)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK
;
119 byteEnables
= byteEnables
<< PCI_NP_CBE_BESL
;
121 /*address bits 31:28 specify the device, 10:8 specify the function */
122 /*Set the address to be read */
123 addr
= BIT ((31 - dev
)) | (where
& ~3);
124 non_prefetch_read (addr
, byteEnables
| NP_CMD_CONFIGREAD
, &retval
);
125 /*Pick out the byte we are interested in */
126 *val
= (retval
>> (8 * n
));
131 int pci_write_config_byte (pci_dev_t dev
, int where
, unsigned char val
)
134 unsigned int byteEnables
;
139 /*byte enables are 4 bits active low, the position of each
140 bit maps to the byte that it enables */
141 byteEnables
= (~BIT (n
)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK
;
142 byteEnables
= byteEnables
<< PCI_NP_CBE_BESL
;
143 ldata
= val
<< (8 * n
);
144 /*address bits 31:28 specify the device 10:8 specify the function */
145 /*Set the address to be written */
146 addr
= BIT ((31 - dev
)) | (where
& ~3);
147 non_prefetch_write (addr
, byteEnables
| NP_CMD_CONFIGWRITE
, ldata
);
152 int pci_write_config_word (pci_dev_t dev
, int where
, unsigned short val
)
155 unsigned int byteEnables
;
160 /*byte enables are 4 bits active low, the position of each
161 bit maps to the byte that it enables */
163 (~(BIT (n
) | BIT ((n
+ 1)))) &
164 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK
;
165 byteEnables
= byteEnables
<< PCI_NP_CBE_BESL
;
166 ldata
= val
<< (8 * n
);
167 /*address bits 31:28 specify the device 10:8 specify the function */
168 /*Set the address to be written */
169 addr
= BIT (31 - dev
) | (where
& ~3);
170 non_prefetch_write (addr
, byteEnables
| NP_CMD_CONFIGWRITE
, ldata
);
175 int pci_write_config_dword (pci_dev_t dev
, int where
, unsigned int val
)
179 /*address bits 31:28 specify the device 10:8 specify the function */
180 /*Set the address to be written */
181 addr
= BIT (31 - dev
) | (where
& ~3);
182 non_prefetch_write (addr
, NP_CMD_CONFIGWRITE
, val
);
187 void non_prefetch_read (unsigned int addr
,
188 unsigned int cmd
, unsigned int *data
)
190 REG_WRITE (PCI_CSR_BASE
, PCI_NP_AD_OFFSET
, addr
);
192 /*set up and execute the read */
193 REG_WRITE (PCI_CSR_BASE
, PCI_NP_CBE_OFFSET
, cmd
);
195 /*The result of the read is now in np_rdata */
196 REG_READ (PCI_CSR_BASE
, PCI_NP_RDATA_OFFSET
, *data
);
201 void non_prefetch_write (unsigned int addr
,
202 unsigned int cmd
, unsigned int data
)
205 REG_WRITE (PCI_CSR_BASE
, PCI_NP_AD_OFFSET
, addr
);
206 /*set up the write */
207 REG_WRITE (PCI_CSR_BASE
, PCI_NP_CBE_OFFSET
, cmd
);
208 /*Execute the write by writing to NP_WDATA */
209 REG_WRITE (PCI_CSR_BASE
, PCI_NP_WDATA_OFFSET
, data
);
215 * PCI controller config registers are accessed through these functions
216 * i.e. these allow us to set up our own BARs etc.
218 void crp_read (unsigned int offset
, unsigned int *data
)
220 REG_WRITE (PCI_CSR_BASE
, PCI_CRP_AD_CBE_OFFSET
, offset
);
221 REG_READ (PCI_CSR_BASE
, PCI_CRP_RDATA_OFFSET
, *data
);
224 void crp_write (unsigned int offset
, unsigned int data
)
226 /*The CRP address register bit 16 indicates that we want to do a write */
227 REG_WRITE (PCI_CSR_BASE
, PCI_CRP_AD_CBE_OFFSET
,
228 PCI_CRP_WRITE
| offset
);
229 REG_WRITE (PCI_CSR_BASE
, PCI_CRP_WDATA_OFFSET
, data
);
232 /*struct pci_controller *hose*/
233 void pci_ixp_init (struct pci_controller
*hose
)
237 hose
->first_busno
= 0;
238 hose
->last_busno
= 0x00;
240 /* System memory space */
241 pci_set_region (hose
->regions
+ 0,
243 PCI_MEMORY_PHY
, PCI_MEMORY_SIZE
, PCI_REGION_MEMORY
);
245 /* PCI memory space */
246 pci_set_region (hose
->regions
+ 1,
248 PCI_MEM_PHY
, PCI_MEM_SIZE
, PCI_REGION_MEM
);
250 pci_set_region (hose
->regions
+ 2,
251 PCI_IO_BUS
, PCI_IO_PHY
, PCI_IO_SIZE
, PCI_REGION_IO
);
253 hose
->region_count
= 3;
255 pci_register_hose (hose
);
258 ==========================================================
260 ==========================================================
262 REG_READ (PCI_CSR_BASE
, PCI_CSR_OFFSET
, regval
);
264 REG_WRITE (PCI_CSR_BASE
, PCI_CSR_OFFSET
, regval
);
268 READ_GPIO_REG (IXP425_GPIO_GPOUTR
, regval
);
269 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR
, regval
& (~(1 << 13)));
271 sys_pci_gpio_clock_config ();
272 REG_WRITE (PCI_CSR_BASE
, PCI_INTEN_OFFSET
, 0);
274 READ_GPIO_REG (IXP425_GPIO_GPOUTR
, regval
);
275 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR
, regval
| (1 << 13));
277 crp_write (PCI_CFG_BASE_ADDRESS_0
, IXP425_PCI_BAR_0_DEFAULT
);
278 crp_write (PCI_CFG_BASE_ADDRESS_1
, IXP425_PCI_BAR_1_DEFAULT
);
279 crp_write (PCI_CFG_BASE_ADDRESS_2
, IXP425_PCI_BAR_2_DEFAULT
);
280 crp_write (PCI_CFG_BASE_ADDRESS_3
, IXP425_PCI_BAR_3_DEFAULT
);
281 crp_write (PCI_CFG_BASE_ADDRESS_4
, IXP425_PCI_BAR_4_DEFAULT
);
282 crp_write (PCI_CFG_BASE_ADDRESS_5
, IXP425_PCI_BAR_5_DEFAULT
);
283 /*Setup PCI-AHB and AHB-PCI address mappings */
284 REG_WRITE (PCI_CSR_BASE
, PCI_AHBMEMBASE_OFFSET
,
285 IXP425_PCI_AHBMEMBASE_DEFAULT
);
287 REG_WRITE (PCI_CSR_BASE
, PCI_AHBIOBASE_OFFSET
,
288 IXP425_PCI_AHBIOBASE_DEFAULT
);
290 REG_WRITE (PCI_CSR_BASE
, PCI_PCIMEMBASE_OFFSET
,
291 IXP425_PCI_PCIMEMBASE_DEFAULT
);
293 crp_write (PCI_CFG_SUB_VENDOR_ID
, IXP425_PCI_SUB_VENDOR_SYSTEM
);
295 REG_READ (PCI_CSR_BASE
, PCI_CSR_OFFSET
, regval
);
296 regval
|= PCI_CSR_IC
| PCI_CSR_ABE
| PCI_CSR_PDS
;
297 REG_WRITE (PCI_CSR_BASE
, PCI_CSR_OFFSET
, regval
);
298 crp_write (PCI_CFG_COMMAND
, PCI_CFG_CMD_MAE
| PCI_CFG_CMD_BME
);
301 pci_write_config_word (0, PCI_CFG_COMMAND
, INITIAL_PCI_CMD
);
302 REG_WRITE (PCI_CSR_BASE
, PCI_ISR_OFFSET
, PCI_ISR_PSE
303 | PCI_ISR_PFE
| PCI_ISR_PPE
| PCI_ISR_AHBE
);
304 #ifdef CONFIG_PCI_SCAN_SHOW
305 printf ("Device bus dev func deviceID vendorID \n");
310 void configure_pins (void)
314 /* Disable clock on GPIO PIN 14 */
315 READ_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
316 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
& (~(1 << 8)));
317 READ_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
319 READ_GPIO_REG (IXP425_GPIO_GPOER
, regval
);
320 WRITE_GPIO_REG (IXP425_GPIO_GPOER
,
321 (((~(3 << 13)) & regval
) | (0xf << 8)));
322 READ_GPIO_REG (IXP425_GPIO_GPOER
, regval
);
324 READ_GPIO_REG (IXP425_GPIO_GPIT2R
, regval
);
325 WRITE_GPIO_REG (IXP425_GPIO_GPIT2R
,
327 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
328 READ_GPIO_REG (IXP425_GPIO_GPIT2R
, regval
);
330 READ_GPIO_REG (IXP425_GPIO_GPISR
, regval
);
331 WRITE_GPIO_REG (IXP425_GPIO_GPISR
, (regval
| (0xf << 8)));
332 READ_GPIO_REG (IXP425_GPIO_GPISR
, regval
);
335 void sys_pci_gpio_clock_config (void)
339 READ_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
341 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
342 READ_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
344 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR
, regval
);
347 void pci_bus_scan (void)
349 unsigned int bus
= 0, dev
, func
= 0;
350 unsigned short data16
;
352 unsigned char intPin
;
354 /* Assign first device to ourselves */
356 devices
[0].device
= 0;
359 crp_read (PCI_CFG_VENDOR_ID
, &data32
);
361 devices
[0].vendor_id
= data32
& IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK
;
362 devices
[0].device_id
= data32
>> 16;
363 devices
[0].error
= FALSE
;
364 devices
[0].bar
[NO_BAR
].size
= 0; /*dummy - required */
371 for (dev
= 0; dev
< IXP425_PCI_MAX_DEV
; dev
++) {
373 /*Check whether a device is present */
374 if (pci_device_exists (dev
) != TRUE
) {
376 /*Clear error bits in ISR, write 1 to clear */
377 REG_WRITE (PCI_CSR_BASE
, PCI_ISR_OFFSET
, PCI_ISR_PSE
378 | PCI_ISR_PFE
| PCI_ISR_PPE
|
383 /*A device is present, add an entry to the array */
384 devices
[nDevices
].bus
= bus
;
385 devices
[nDevices
].device
= dev
;
386 devices
[nDevices
].func
= func
;
388 pci_read_config_word (dev
, PCI_CFG_VENDOR_ID
, &data16
);
390 devices
[nDevices
].vendor_id
= data16
;
392 pci_read_config_word (dev
, PCI_CFG_DEVICE_ID
, &data16
);
393 devices
[nDevices
].device_id
= data16
;
395 /*The device is functioning correctly, set error to FALSE */
396 devices
[nDevices
].error
= FALSE
;
398 /*Figure out what BARs are on this device */
399 sys_pci_bar_info_get (nDevices
, bus
, dev
, func
);
400 /*Figure out what INTX# line the card uses */
401 pci_read_config_byte (dev
, PCI_CFG_DEV_INT_PIN
, &intPin
);
403 /*assign the appropriate irq line */
404 if (intPin
> PCI_IRQ_LINES
) {
405 devices
[nDevices
].error
= TRUE
;
406 } else if (intPin
!= 0) {
407 /*This device uses an interrupt line */
408 /*devices[nDevices].irq = ixp425PciIntTranslate[dev][intPin-1]; */
409 devices
[nDevices
].irq
= intPin
;
411 #ifdef CONFIG_PCI_SCAN_SHOW
412 printf ("%06d %03d %03d %04d %08d %08x\n", nDevices
,
413 devices
[nDevices
].vendor_id
);
419 calc_bars (memBars
, nMBars
, IXP425_PCI_BAR_MEM_BASE
);
420 sys_pci_device_bars_write ();
422 REG_WRITE (PCI_CSR_BASE
, PCI_ISR_OFFSET
, PCI_ISR_PSE
423 | PCI_ISR_PFE
| PCI_ISR_PPE
| PCI_ISR_AHBE
);
426 void sys_pci_bar_info_get (unsigned int devnum
,
428 unsigned int dev
, unsigned int func
)
434 pci_write_config_dword (devnum
,
435 PCI_CFG_BASE_ADDRESS_0
, IXP425_PCI_BAR_QUERY
);
436 pci_read_config_dword (devnum
, PCI_CFG_BASE_ADDRESS_0
, &data32
);
438 devices
[devnum
].bar
[0].address
= (data32
& 1);
444 devices
[devnum
].bar
[0].size
= size
;
446 if (nIOBars
< IXP425_PCI_MAX_BAR
) {
447 ioBars
[nIOBars
++] = &devices
[devnum
].bar
[0];
451 tmp
= data32
& ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK
;
453 devices
[devnum
].bar
[0].size
= size
;
455 if (nMBars
< IXP425_PCI_MAX_BAR
) {
456 memBars
[nMBars
++] = &devices
[devnum
].bar
[0];
458 devices
[devnum
].error
= TRUE
;
463 devices
[devnum
].bar
[1].size
= 0;
466 void sortBars (PciBar
* Bars
[], unsigned int nBars
)
475 /* Sort biggest to smallest */
476 for (i
= 0; i
< nBars
- 1; i
++) {
477 for (j
= i
+ 1; j
< nBars
; j
++) {
478 if (Bars
[j
]->size
> Bars
[i
]->size
) {
488 void calc_bars (PciBar
* Bars
[], unsigned int nBars
, unsigned int startAddr
)
496 for (i
= 0; i
< nBars
; i
++) {
497 Bars
[i
]->address
|= startAddr
;
498 startAddr
+= Bars
[i
]->size
;
502 void sys_pci_device_bars_write (void)
507 for (i
= 1; i
< nDevices
; i
++) {
508 if (devices
[i
].error
) {
512 pci_write_config_dword (devices
[i
].device
,
513 PCI_CFG_BASE_ADDRESS_0
,
514 devices
[i
].bar
[0].address
);
515 addr
= BIT (31 - devices
[i
].device
) |
516 (0 << PCI_NP_AD_FUNCSL
) |
517 (PCI_CFG_BASE_ADDRESS_0
& ~3);
518 pci_write_config_dword (devices
[i
].device
,
519 PCI_CFG_DEV_INT_LINE
, devices
[i
].irq
);
521 pci_write_config_word (devices
[i
].device
,
522 PCI_CFG_COMMAND
, INITIAL_PCI_CMD
);
528 int pci_device_exists (unsigned int deviceNo
)
530 unsigned int vendorId
;
533 pci_read_config_dword (deviceNo
, PCI_CFG_VENDOR_ID
, &vendorId
);
535 /* There are two ways to find out an empty device.
536 * 1. check Master Abort bit after the access.
537 * 2. check whether the vendor id read back is 0x0.
539 REG_READ (PCI_CSR_BASE
, PCI_ISR_OFFSET
, regval
);
540 if ((vendorId
!= 0x0) && ((regval
& PCI_ISR_PFE
) == 0)) {
543 /*no device present, make sure that the master abort bit is reset */
545 REG_WRITE (PCI_CSR_BASE
, PCI_ISR_OFFSET
, PCI_ISR_PFE
);
549 pci_dev_t
pci_find_devices (struct pci_device_id
* ids
, int devNo
)
552 unsigned int devdidvid
;
554 unsigned int vendorId
, deviceId
;
556 vendorId
= ids
->vendor
;
557 deviceId
= ids
->device
;
558 didvid
= ((deviceId
<< 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK
) |
559 (vendorId
& IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK
);
561 for (i
= devNo
+ 1; i
< nDevices
; i
++) {
563 pci_read_config_dword (devices
[i
].device
, PCI_CFG_VENDOR_ID
,
566 if (devdidvid
== didvid
) {
567 return devices
[i
].device
;