2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
10 * SPDX-License-Identifier: GPL-2.0
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
22 #include <power-domain.h>
28 #include <linux/list.h>
30 #ifndef CONFIG_TEGRA186
31 #include <asm/arch/clock.h>
32 #include <asm/arch/powergate.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
38 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
39 * should not be present. These are needed because newer Tegra SoCs support
40 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
42 * fixed to implement the standard APIs, and all drivers converted to solely
43 * use the new standard APIs, with no ifdefs.
46 DECLARE_GLOBAL_DATA_PTR
;
48 #define AFI_AXI_BAR0_SZ 0x00
49 #define AFI_AXI_BAR1_SZ 0x04
50 #define AFI_AXI_BAR2_SZ 0x08
51 #define AFI_AXI_BAR3_SZ 0x0c
52 #define AFI_AXI_BAR4_SZ 0x10
53 #define AFI_AXI_BAR5_SZ 0x14
55 #define AFI_AXI_BAR0_START 0x18
56 #define AFI_AXI_BAR1_START 0x1c
57 #define AFI_AXI_BAR2_START 0x20
58 #define AFI_AXI_BAR3_START 0x24
59 #define AFI_AXI_BAR4_START 0x28
60 #define AFI_AXI_BAR5_START 0x2c
62 #define AFI_FPCI_BAR0 0x30
63 #define AFI_FPCI_BAR1 0x34
64 #define AFI_FPCI_BAR2 0x38
65 #define AFI_FPCI_BAR3 0x3c
66 #define AFI_FPCI_BAR4 0x40
67 #define AFI_FPCI_BAR5 0x44
69 #define AFI_CACHE_BAR0_SZ 0x48
70 #define AFI_CACHE_BAR0_ST 0x4c
71 #define AFI_CACHE_BAR1_SZ 0x50
72 #define AFI_CACHE_BAR1_ST 0x54
74 #define AFI_MSI_BAR_SZ 0x60
75 #define AFI_MSI_FPCI_BAR_ST 0x64
76 #define AFI_MSI_AXI_BAR_ST 0x68
78 #define AFI_CONFIGURATION 0xac
79 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
81 #define AFI_FPCI_ERROR_MASKS 0xb0
83 #define AFI_INTR_MASK 0xb4
84 #define AFI_INTR_MASK_INT_MASK (1 << 0)
85 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
87 #define AFI_SM_INTR_ENABLE 0xc4
88 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
89 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
90 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
91 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
92 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
93 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
94 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
95 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
97 #define AFI_AFI_INTR_ENABLE 0xc8
98 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
99 #define AFI_INTR_EN_INI_DECERR (1 << 1)
100 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
102 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
103 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
105 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
106 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
108 #define AFI_PCIE_CONFIG 0x0f8
109 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
110 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
120 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
121 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
123 #define AFI_FUSE 0x104
124 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
126 #define AFI_PEX0_CTRL 0x110
127 #define AFI_PEX1_CTRL 0x118
128 #define AFI_PEX2_CTRL 0x128
129 #define AFI_PEX2_CTRL_T186 0x19c
130 #define AFI_PEX_CTRL_RST (1 << 0)
131 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
132 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
133 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
135 #define AFI_PLLE_CONTROL 0x160
136 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
137 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
139 #define AFI_PEXBIAS_CTRL_0 0x168
141 #define PADS_CTL_SEL 0x0000009C
143 #define PADS_CTL 0x000000A0
144 #define PADS_CTL_IDDQ_1L (1 << 0)
145 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
146 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
148 #define PADS_PLL_CTL_TEGRA20 0x000000B8
149 #define PADS_PLL_CTL_TEGRA30 0x000000B4
150 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
151 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
152 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
153 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
154 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
155 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
156 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
157 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
158 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
159 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
161 #define PADS_REFCLK_CFG0 0x000000C8
162 #define PADS_REFCLK_CFG1 0x000000CC
165 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
166 * entries, one entry per PCIe port. These field definitions and desired
167 * values aren't in the TRM, but do come from NVIDIA.
169 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
170 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
171 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
172 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
174 #define RP_VEND_XP 0x00000F00
175 #define RP_VEND_XP_DL_UP (1 << 30)
177 #define RP_VEND_CTL2 0x00000FA8
178 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
180 #define RP_PRIV_MISC 0x00000FE0
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
182 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
184 #define RP_LINK_CONTROL_STATUS 0x00000090
185 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
196 struct tegra_pcie_port
{
197 struct tegra_pcie
*pcie
;
199 struct fdt_resource regs
;
200 unsigned int num_lanes
;
203 struct list_head list
;
206 struct tegra_pcie_soc
{
207 unsigned int num_ports
;
208 unsigned long pads_pll_ctl
;
209 unsigned long tx_ref_sel
;
210 unsigned long afi_pex2_ctrl
;
211 u32 pads_refclk_cfg0
;
212 u32 pads_refclk_cfg1
;
213 bool has_pex_clkreq_en
;
214 bool has_pex_bias_ctrl
;
217 bool force_pca_enable
;
221 struct pci_controller hose
;
223 struct fdt_resource pads
;
224 struct fdt_resource afi
;
225 struct fdt_resource cs
;
227 struct list_head ports
;
230 const struct tegra_pcie_soc
*soc
;
232 #ifdef CONFIG_TEGRA186
235 struct reset_ctl reset_afi
;
236 struct reset_ctl reset_pex
;
237 struct reset_ctl reset_pcie_x
;
238 struct power_domain pwrdom
;
240 struct tegra_xusb_phy
*phy
;
244 static void afi_writel(struct tegra_pcie
*pcie
, unsigned long value
,
245 unsigned long offset
)
247 writel(value
, pcie
->afi
.start
+ offset
);
250 static unsigned long afi_readl(struct tegra_pcie
*pcie
, unsigned long offset
)
252 return readl(pcie
->afi
.start
+ offset
);
255 static void pads_writel(struct tegra_pcie
*pcie
, unsigned long value
,
256 unsigned long offset
)
258 writel(value
, pcie
->pads
.start
+ offset
);
261 #ifndef CONFIG_TEGRA186
262 static unsigned long pads_readl(struct tegra_pcie
*pcie
, unsigned long offset
)
264 return readl(pcie
->pads
.start
+ offset
);
268 static unsigned long rp_readl(struct tegra_pcie_port
*port
,
269 unsigned long offset
)
271 return readl(port
->regs
.start
+ offset
);
274 static void rp_writel(struct tegra_pcie_port
*port
, unsigned long value
,
275 unsigned long offset
)
277 writel(value
, port
->regs
.start
+ offset
);
280 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf
, int where
)
282 return ((where
& 0xf00) << 16) | (PCI_BUS(bdf
) << 16) |
283 (PCI_DEV(bdf
) << 11) | (PCI_FUNC(bdf
) << 8) |
287 static int tegra_pcie_conf_address(struct tegra_pcie
*pcie
, pci_dev_t bdf
,
288 int where
, unsigned long *address
)
290 unsigned int bus
= PCI_BUS(bdf
);
293 unsigned int dev
= PCI_DEV(bdf
);
294 struct tegra_pcie_port
*port
;
296 list_for_each_entry(port
, &pcie
->ports
, list
) {
297 if (port
->index
+ 1 == dev
) {
298 *address
= port
->regs
.start
+ (where
& ~3);
304 #ifdef CONFIG_TEGRA20
305 unsigned int dev
= PCI_DEV(bdf
);
310 *address
= pcie
->cs
.start
+ tegra_pcie_conf_offset(bdf
, where
);
315 static int pci_tegra_read_config(struct udevice
*bus
, pci_dev_t bdf
,
316 uint offset
, ulong
*valuep
,
317 enum pci_size_t size
)
319 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
320 unsigned long address
, value
;
323 err
= tegra_pcie_conf_address(pcie
, bdf
, offset
, &address
);
329 value
= readl(address
);
331 #ifdef CONFIG_TEGRA20
332 /* fixup root port class */
333 if (PCI_BUS(bdf
) == 0) {
334 if ((offset
& ~3) == PCI_CLASS_REVISION
) {
335 value
&= ~0x00ff0000;
336 value
|= PCI_CLASS_BRIDGE_PCI
<< 16;
342 *valuep
= pci_conv_32_to_size(value
, offset
, size
);
347 static int pci_tegra_write_config(struct udevice
*bus
, pci_dev_t bdf
,
348 uint offset
, ulong value
,
349 enum pci_size_t size
)
351 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
352 unsigned long address
;
356 err
= tegra_pcie_conf_address(pcie
, bdf
, offset
, &address
);
360 old
= readl(address
);
361 value
= pci_conv_size_to_32(old
, value
, offset
, size
);
362 writel(value
, address
);
367 static int tegra_pcie_port_parse_dt(const void *fdt
, int node
,
368 struct tegra_pcie_port
*port
)
373 addr
= fdt_getprop(fdt
, node
, "assigned-addresses", &len
);
375 error("property \"assigned-addresses\" not found");
376 return -FDT_ERR_NOTFOUND
;
379 port
->regs
.start
= fdt32_to_cpu(addr
[2]);
380 port
->regs
.end
= port
->regs
.start
+ fdt32_to_cpu(addr
[4]);
385 static int tegra_pcie_get_xbar_config(const void *fdt
, int node
, u32 lanes
,
386 enum tegra_pci_id id
, unsigned long *xbar
)
392 debug("single-mode configuration\n");
393 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE
;
397 debug("dual-mode configuration\n");
398 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
;
405 debug("4x1, 2x1 configuration\n");
406 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420
;
410 debug("2x3 configuration\n");
411 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222
;
415 debug("4x1, 1x2 configuration\n");
416 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411
;
424 debug("4x1, 1x1 configuration\n");
425 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1
;
429 debug("2x1, 1x1 configuration\n");
430 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1
;
437 debug("x4 x1 configuration\n");
438 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401
;
442 debug("x2 x1 x1 configuration\n");
443 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211
;
447 debug("x1 x1 x1 configuration\n");
448 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111
;
456 return -FDT_ERR_NOTFOUND
;
459 static int tegra_pcie_parse_port_info(const void *fdt
, int node
,
463 struct fdt_pci_addr addr
;
466 err
= fdtdec_get_int(fdt
, node
, "nvidia,num-lanes", 0);
468 error("failed to parse \"nvidia,num-lanes\" property");
474 err
= fdtdec_get_pci_addr(fdt
, node
, 0, "reg", &addr
);
476 error("failed to parse \"reg\" property");
480 *index
= PCI_DEV(addr
.phys_hi
) - 1;
485 int __weak
tegra_pcie_board_init(void)
490 static int tegra_pcie_parse_dt(const void *fdt
, int node
, enum tegra_pci_id id
,
491 struct tegra_pcie
*pcie
)
496 err
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names", "pads",
499 error("resource \"pads\" not found");
503 err
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names", "afi",
506 error("resource \"afi\" not found");
510 err
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names", "cs",
513 error("resource \"cs\" not found");
517 err
= tegra_pcie_board_init();
519 error("tegra_pcie_board_init() failed: err=%d", err
);
523 #ifndef CONFIG_TEGRA186
524 pcie
->phy
= tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE
);
526 err
= tegra_xusb_phy_prepare(pcie
->phy
);
528 error("failed to prepare PHY: %d", err
);
534 fdt_for_each_subnode(subnode
, fdt
, node
) {
535 unsigned int index
= 0, num_lanes
= 0;
536 struct tegra_pcie_port
*port
;
538 err
= tegra_pcie_parse_port_info(fdt
, subnode
, &index
,
541 error("failed to obtain root port info");
545 lanes
|= num_lanes
<< (index
<< 3);
547 if (!fdtdec_get_is_enabled(fdt
, subnode
))
550 port
= malloc(sizeof(*port
));
554 memset(port
, 0, sizeof(*port
));
555 port
->num_lanes
= num_lanes
;
558 err
= tegra_pcie_port_parse_dt(fdt
, subnode
, port
);
564 list_add_tail(&port
->list
, &pcie
->ports
);
568 err
= tegra_pcie_get_xbar_config(fdt
, node
, lanes
, id
, &pcie
->xbar
);
570 error("invalid lane configuration");
577 #ifdef CONFIG_TEGRA186
578 static int tegra_pcie_power_on(struct tegra_pcie
*pcie
)
582 ret
= power_domain_on(&pcie
->pwrdom
);
584 error("power_domain_on() failed: %d\n", ret
);
588 ret
= clk_enable(&pcie
->clk_afi
);
590 error("clk_enable(afi) failed: %d\n", ret
);
594 ret
= clk_enable(&pcie
->clk_pex
);
596 error("clk_enable(pex) failed: %d\n", ret
);
600 ret
= reset_deassert(&pcie
->reset_afi
);
602 error("reset_deassert(afi) failed: %d\n", ret
);
606 ret
= reset_deassert(&pcie
->reset_pex
);
608 error("reset_deassert(pex) failed: %d\n", ret
);
615 static int tegra_pcie_power_on(struct tegra_pcie
*pcie
)
617 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
621 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
622 reset_set_enable(PERIPH_ID_PCIEXCLK
, 1);
623 reset_set_enable(PERIPH_ID_AFI
, 1);
624 reset_set_enable(PERIPH_ID_PCIE
, 1);
626 err
= tegra_powergate_power_off(TEGRA_POWERGATE_PCIE
);
628 error("failed to power off PCIe partition: %d", err
);
632 err
= tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE
,
635 error("failed to power up PCIe partition: %d", err
);
639 /* take AFI controller out of reset */
640 reset_set_enable(PERIPH_ID_AFI
, 0);
642 /* enable AFI clock */
643 clock_enable(PERIPH_ID_AFI
);
645 if (soc
->has_cml_clk
) {
646 /* enable CML clock */
647 value
= readl(NV_PA_CLK_RST_BASE
+ 0x48c);
650 writel(value
, NV_PA_CLK_RST_BASE
+ 0x48c);
653 err
= tegra_plle_enable();
655 error("failed to enable PLLE: %d\n", err
);
662 static int tegra_pcie_pll_wait(struct tegra_pcie
*pcie
, unsigned long timeout
)
664 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
665 unsigned long start
= get_timer(0);
668 while (get_timer(start
) < timeout
) {
669 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
670 if (value
& PADS_PLL_CTL_LOCKDET
)
677 static int tegra_pcie_phy_enable(struct tegra_pcie
*pcie
)
679 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
683 /* initialize internal PHY, enable up to 16 PCIe lanes */
684 pads_writel(pcie
, 0, PADS_CTL_SEL
);
686 /* override IDDQ to 1 on all 4 lanes */
687 value
= pads_readl(pcie
, PADS_CTL
);
688 value
|= PADS_CTL_IDDQ_1L
;
689 pads_writel(pcie
, value
, PADS_CTL
);
692 * Set up PHY PLL inputs select PLLE output as refclock, set TX
693 * ref sel to div10 (not div5).
695 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
696 value
&= ~(PADS_PLL_CTL_REFCLK_MASK
| PADS_PLL_CTL_TXCLKREF_MASK
);
697 value
|= PADS_PLL_CTL_REFCLK_INTERNAL_CML
| soc
->tx_ref_sel
;
698 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
701 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
702 value
&= ~PADS_PLL_CTL_RST_B4SM
;
703 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
707 /* take PLL out of reset */
708 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
709 value
|= PADS_PLL_CTL_RST_B4SM
;
710 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
712 /* wait for the PLL to lock */
713 err
= tegra_pcie_pll_wait(pcie
, 500);
715 error("PLL failed to lock: %d", err
);
719 /* turn off IDDQ override */
720 value
= pads_readl(pcie
, PADS_CTL
);
721 value
&= ~PADS_CTL_IDDQ_1L
;
722 pads_writel(pcie
, value
, PADS_CTL
);
724 /* enable TX/RX data */
725 value
= pads_readl(pcie
, PADS_CTL
);
726 value
|= PADS_CTL_TX_DATA_EN_1L
| PADS_CTL_RX_DATA_EN_1L
;
727 pads_writel(pcie
, value
, PADS_CTL
);
733 static int tegra_pcie_enable_controller(struct tegra_pcie
*pcie
)
735 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
736 struct tegra_pcie_port
*port
;
740 #ifdef CONFIG_TEGRA186
745 value
= afi_readl(pcie
, AFI_PLLE_CONTROL
);
746 value
&= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL
;
747 value
|= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN
;
748 afi_writel(pcie
, value
, AFI_PLLE_CONTROL
);
751 if (soc
->has_pex_bias_ctrl
)
752 afi_writel(pcie
, 0, AFI_PEXBIAS_CTRL_0
);
754 value
= afi_readl(pcie
, AFI_PCIE_CONFIG
);
755 value
&= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK
;
756 value
|= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL
| pcie
->xbar
;
758 list_for_each_entry(port
, &pcie
->ports
, list
)
759 value
&= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port
->index
);
761 afi_writel(pcie
, value
, AFI_PCIE_CONFIG
);
763 value
= afi_readl(pcie
, AFI_FUSE
);
766 value
&= ~AFI_FUSE_PCIE_T0_GEN2_DIS
;
768 value
|= AFI_FUSE_PCIE_T0_GEN2_DIS
;
770 afi_writel(pcie
, value
, AFI_FUSE
);
772 #ifndef CONFIG_TEGRA186
774 err
= tegra_xusb_phy_enable(pcie
->phy
);
776 err
= tegra_pcie_phy_enable(pcie
);
779 error("failed to power on PHY: %d\n", err
);
784 /* take the PCIEXCLK logic out of reset */
785 #ifdef CONFIG_TEGRA186
786 err
= reset_deassert(&pcie
->reset_pcie_x
);
788 error("reset_deassert(pcie_x) failed: %d\n", err
);
792 reset_set_enable(PERIPH_ID_PCIEXCLK
, 0);
795 /* finally enable PCIe */
796 value
= afi_readl(pcie
, AFI_CONFIGURATION
);
797 value
|= AFI_CONFIGURATION_EN_FPCI
;
798 afi_writel(pcie
, value
, AFI_CONFIGURATION
);
800 /* disable all interrupts */
801 afi_writel(pcie
, 0, AFI_AFI_INTR_ENABLE
);
802 afi_writel(pcie
, 0, AFI_SM_INTR_ENABLE
);
803 afi_writel(pcie
, 0, AFI_INTR_MASK
);
804 afi_writel(pcie
, 0, AFI_FPCI_ERROR_MASKS
);
809 static int tegra_pcie_setup_translations(struct udevice
*bus
)
811 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
812 unsigned long fpci
, axi
, size
;
813 struct pci_region
*io
, *mem
, *pref
;
816 /* BAR 0: type 1 extended configuration space */
818 size
= fdt_resource_size(&pcie
->cs
);
819 axi
= pcie
->cs
.start
;
821 afi_writel(pcie
, axi
, AFI_AXI_BAR0_START
);
822 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR0_SZ
);
823 afi_writel(pcie
, fpci
, AFI_FPCI_BAR0
);
825 count
= pci_get_regions(bus
, &io
, &mem
, &pref
);
829 /* BAR 1: downstream I/O */
832 axi
= io
->phys_start
;
834 afi_writel(pcie
, axi
, AFI_AXI_BAR1_START
);
835 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR1_SZ
);
836 afi_writel(pcie
, fpci
, AFI_FPCI_BAR1
);
838 /* BAR 2: prefetchable memory */
839 fpci
= (((pref
->phys_start
>> 12) & 0x0fffffff) << 4) | 0x1;
841 axi
= pref
->phys_start
;
843 afi_writel(pcie
, axi
, AFI_AXI_BAR2_START
);
844 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR2_SZ
);
845 afi_writel(pcie
, fpci
, AFI_FPCI_BAR2
);
847 /* BAR 3: non-prefetchable memory */
848 fpci
= (((mem
->phys_start
>> 12) & 0x0fffffff) << 4) | 0x1;
850 axi
= mem
->phys_start
;
852 afi_writel(pcie
, axi
, AFI_AXI_BAR3_START
);
853 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR3_SZ
);
854 afi_writel(pcie
, fpci
, AFI_FPCI_BAR3
);
856 /* NULL out the remaining BARs as they are not used */
857 afi_writel(pcie
, 0, AFI_AXI_BAR4_START
);
858 afi_writel(pcie
, 0, AFI_AXI_BAR4_SZ
);
859 afi_writel(pcie
, 0, AFI_FPCI_BAR4
);
861 afi_writel(pcie
, 0, AFI_AXI_BAR5_START
);
862 afi_writel(pcie
, 0, AFI_AXI_BAR5_SZ
);
863 afi_writel(pcie
, 0, AFI_FPCI_BAR5
);
865 /* map all upstream transactions as uncached */
866 afi_writel(pcie
, NV_PA_SDRAM_BASE
, AFI_CACHE_BAR0_ST
);
867 afi_writel(pcie
, 0, AFI_CACHE_BAR0_SZ
);
868 afi_writel(pcie
, 0, AFI_CACHE_BAR1_ST
);
869 afi_writel(pcie
, 0, AFI_CACHE_BAR1_SZ
);
871 /* MSI translations are setup only when needed */
872 afi_writel(pcie
, 0, AFI_MSI_FPCI_BAR_ST
);
873 afi_writel(pcie
, 0, AFI_MSI_BAR_SZ
);
874 afi_writel(pcie
, 0, AFI_MSI_AXI_BAR_ST
);
875 afi_writel(pcie
, 0, AFI_MSI_BAR_SZ
);
880 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port
*port
)
882 unsigned long ret
= 0;
884 switch (port
->index
) {
894 ret
= port
->pcie
->soc
->afi_pex2_ctrl
;
901 static void tegra_pcie_port_reset(struct tegra_pcie_port
*port
)
903 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
906 /* pulse reset signel */
907 value
= afi_readl(port
->pcie
, ctrl
);
908 value
&= ~AFI_PEX_CTRL_RST
;
909 afi_writel(port
->pcie
, value
, ctrl
);
913 value
= afi_readl(port
->pcie
, ctrl
);
914 value
|= AFI_PEX_CTRL_RST
;
915 afi_writel(port
->pcie
, value
, ctrl
);
918 static void tegra_pcie_port_enable(struct tegra_pcie_port
*port
)
920 struct tegra_pcie
*pcie
= port
->pcie
;
921 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
922 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
925 /* enable reference clock */
926 value
= afi_readl(pcie
, ctrl
);
927 value
|= AFI_PEX_CTRL_REFCLK_EN
;
929 if (pcie
->soc
->has_pex_clkreq_en
)
930 value
|= AFI_PEX_CTRL_CLKREQ_EN
;
932 value
|= AFI_PEX_CTRL_OVERRIDE_EN
;
934 afi_writel(pcie
, value
, ctrl
);
936 tegra_pcie_port_reset(port
);
938 if (soc
->force_pca_enable
) {
939 value
= rp_readl(port
, RP_VEND_CTL2
);
940 value
|= RP_VEND_CTL2_PCA_ENABLE
;
941 rp_writel(port
, value
, RP_VEND_CTL2
);
944 /* configure the reference clock driver */
945 pads_writel(pcie
, soc
->pads_refclk_cfg0
, PADS_REFCLK_CFG0
);
946 if (soc
->num_ports
> 2)
947 pads_writel(pcie
, soc
->pads_refclk_cfg1
, PADS_REFCLK_CFG1
);
950 static bool tegra_pcie_port_check_link(struct tegra_pcie_port
*port
)
952 unsigned int retries
= 3;
955 value
= rp_readl(port
, RP_PRIV_MISC
);
956 value
&= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
;
957 value
|= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
;
958 rp_writel(port
, value
, RP_PRIV_MISC
);
961 unsigned int timeout
= 200;
964 value
= rp_readl(port
, RP_VEND_XP
);
965 if (value
& RP_VEND_XP_DL_UP
)
972 debug("link %u down, retrying\n", port
->index
);
979 value
= rp_readl(port
, RP_LINK_CONTROL_STATUS
);
980 if (value
& RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
)
987 tegra_pcie_port_reset(port
);
993 static void tegra_pcie_port_disable(struct tegra_pcie_port
*port
)
995 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
998 /* assert port reset */
999 value
= afi_readl(port
->pcie
, ctrl
);
1000 value
&= ~AFI_PEX_CTRL_RST
;
1001 afi_writel(port
->pcie
, value
, ctrl
);
1003 /* disable reference clock */
1004 value
= afi_readl(port
->pcie
, ctrl
);
1005 value
&= ~AFI_PEX_CTRL_REFCLK_EN
;
1006 afi_writel(port
->pcie
, value
, ctrl
);
1009 static void tegra_pcie_port_free(struct tegra_pcie_port
*port
)
1011 list_del(&port
->list
);
1015 static int tegra_pcie_enable(struct tegra_pcie
*pcie
)
1017 struct tegra_pcie_port
*port
, *tmp
;
1019 list_for_each_entry_safe(port
, tmp
, &pcie
->ports
, list
) {
1020 debug("probing port %u, using %u lanes\n", port
->index
,
1023 tegra_pcie_port_enable(port
);
1025 if (tegra_pcie_port_check_link(port
))
1028 debug("link %u down, ignoring\n", port
->index
);
1030 tegra_pcie_port_disable(port
);
1031 tegra_pcie_port_free(port
);
1037 static const struct tegra_pcie_soc pci_tegra_soc
[] = {
1040 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA20
,
1041 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_DIV10
,
1042 .pads_refclk_cfg0
= 0xfa5cfa5c,
1043 .has_pex_clkreq_en
= false,
1044 .has_pex_bias_ctrl
= false,
1045 .has_cml_clk
= false,
1050 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1051 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1052 .afi_pex2_ctrl
= AFI_PEX2_CTRL
,
1053 .pads_refclk_cfg0
= 0xfa5cfa5c,
1054 .pads_refclk_cfg1
= 0xfa5cfa5c,
1055 .has_pex_clkreq_en
= true,
1056 .has_pex_bias_ctrl
= true,
1057 .has_cml_clk
= true,
1062 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1063 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1064 .pads_refclk_cfg0
= 0x44ac44ac,
1065 .has_pex_clkreq_en
= true,
1066 .has_pex_bias_ctrl
= true,
1067 .has_cml_clk
= true,
1072 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1073 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1074 .pads_refclk_cfg0
= 0x90b890b8,
1075 .has_pex_clkreq_en
= true,
1076 .has_pex_bias_ctrl
= true,
1077 .has_cml_clk
= true,
1079 .force_pca_enable
= true,
1083 .afi_pex2_ctrl
= AFI_PEX2_CTRL_T186
,
1084 .pads_refclk_cfg0
= 0x80b880b8,
1085 .pads_refclk_cfg1
= 0x000480b8,
1086 .has_pex_clkreq_en
= true,
1087 .has_pex_bias_ctrl
= true,
1092 static int pci_tegra_ofdata_to_platdata(struct udevice
*dev
)
1094 struct tegra_pcie
*pcie
= dev_get_priv(dev
);
1095 enum tegra_pci_id id
;
1097 id
= dev_get_driver_data(dev
);
1098 pcie
->soc
= &pci_tegra_soc
[id
];
1100 INIT_LIST_HEAD(&pcie
->ports
);
1102 if (tegra_pcie_parse_dt(gd
->fdt_blob
, dev_of_offset(dev
), id
, pcie
))
1108 static int pci_tegra_probe(struct udevice
*dev
)
1110 struct tegra_pcie
*pcie
= dev_get_priv(dev
);
1113 #ifdef CONFIG_TEGRA186
1114 err
= clk_get_by_name(dev
, "afi", &pcie
->clk_afi
);
1116 debug("clk_get_by_name(afi) failed: %d\n", err
);
1120 err
= clk_get_by_name(dev
, "pex", &pcie
->clk_pex
);
1122 debug("clk_get_by_name(pex) failed: %d\n", err
);
1126 err
= reset_get_by_name(dev
, "afi", &pcie
->reset_afi
);
1128 debug("reset_get_by_name(afi) failed: %d\n", err
);
1132 err
= reset_get_by_name(dev
, "pex", &pcie
->reset_pex
);
1134 debug("reset_get_by_name(pex) failed: %d\n", err
);
1138 err
= reset_get_by_name(dev
, "pcie_x", &pcie
->reset_pcie_x
);
1140 debug("reset_get_by_name(pcie_x) failed: %d\n", err
);
1144 err
= power_domain_get(dev
, &pcie
->pwrdom
);
1146 debug("power_domain_get() failed: %d\n", err
);
1151 err
= tegra_pcie_power_on(pcie
);
1153 error("failed to power on");
1157 err
= tegra_pcie_enable_controller(pcie
);
1159 error("failed to enable controller");
1163 err
= tegra_pcie_setup_translations(dev
);
1165 error("failed to decode ranges");
1169 err
= tegra_pcie_enable(pcie
);
1171 error("failed to enable PCIe");
1178 static const struct dm_pci_ops pci_tegra_ops
= {
1179 .read_config
= pci_tegra_read_config
,
1180 .write_config
= pci_tegra_write_config
,
1183 static const struct udevice_id pci_tegra_ids
[] = {
1184 { .compatible
= "nvidia,tegra20-pcie", .data
= TEGRA20_PCIE
},
1185 { .compatible
= "nvidia,tegra30-pcie", .data
= TEGRA30_PCIE
},
1186 { .compatible
= "nvidia,tegra124-pcie", .data
= TEGRA124_PCIE
},
1187 { .compatible
= "nvidia,tegra210-pcie", .data
= TEGRA210_PCIE
},
1188 { .compatible
= "nvidia,tegra186-pcie", .data
= TEGRA186_PCIE
},
1192 U_BOOT_DRIVER(pci_tegra
) = {
1193 .name
= "pci_tegra",
1195 .of_match
= pci_tegra_ids
,
1196 .ops
= &pci_tegra_ops
,
1197 .ofdata_to_platdata
= pci_tegra_ofdata_to_platdata
,
1198 .probe
= pci_tegra_probe
,
1199 .priv_auto_alloc_size
= sizeof(struct tegra_pcie
),