2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
10 * SPDX-License-Identifier: GPL-2.0
13 #define pr_fmt(fmt) "tegra-pcie: " fmt
21 #include <power-domain.h>
27 #include <linux/ioport.h>
28 #include <linux/list.h>
30 #ifndef CONFIG_TEGRA186
31 #include <asm/arch/clock.h>
32 #include <asm/arch/powergate.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
38 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
39 * should not be present. These are needed because newer Tegra SoCs support
40 * only the standard clock/reset APIs, whereas older Tegra SoCs support only
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
42 * fixed to implement the standard APIs, and all drivers converted to solely
43 * use the new standard APIs, with no ifdefs.
46 DECLARE_GLOBAL_DATA_PTR
;
48 #define AFI_AXI_BAR0_SZ 0x00
49 #define AFI_AXI_BAR1_SZ 0x04
50 #define AFI_AXI_BAR2_SZ 0x08
51 #define AFI_AXI_BAR3_SZ 0x0c
52 #define AFI_AXI_BAR4_SZ 0x10
53 #define AFI_AXI_BAR5_SZ 0x14
55 #define AFI_AXI_BAR0_START 0x18
56 #define AFI_AXI_BAR1_START 0x1c
57 #define AFI_AXI_BAR2_START 0x20
58 #define AFI_AXI_BAR3_START 0x24
59 #define AFI_AXI_BAR4_START 0x28
60 #define AFI_AXI_BAR5_START 0x2c
62 #define AFI_FPCI_BAR0 0x30
63 #define AFI_FPCI_BAR1 0x34
64 #define AFI_FPCI_BAR2 0x38
65 #define AFI_FPCI_BAR3 0x3c
66 #define AFI_FPCI_BAR4 0x40
67 #define AFI_FPCI_BAR5 0x44
69 #define AFI_CACHE_BAR0_SZ 0x48
70 #define AFI_CACHE_BAR0_ST 0x4c
71 #define AFI_CACHE_BAR1_SZ 0x50
72 #define AFI_CACHE_BAR1_ST 0x54
74 #define AFI_MSI_BAR_SZ 0x60
75 #define AFI_MSI_FPCI_BAR_ST 0x64
76 #define AFI_MSI_AXI_BAR_ST 0x68
78 #define AFI_CONFIGURATION 0xac
79 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
81 #define AFI_FPCI_ERROR_MASKS 0xb0
83 #define AFI_INTR_MASK 0xb4
84 #define AFI_INTR_MASK_INT_MASK (1 << 0)
85 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
87 #define AFI_SM_INTR_ENABLE 0xc4
88 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
89 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
90 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
91 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
92 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
93 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
94 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
95 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
97 #define AFI_AFI_INTR_ENABLE 0xc8
98 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
99 #define AFI_INTR_EN_INI_DECERR (1 << 1)
100 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
101 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
102 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
103 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
104 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
105 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
106 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
108 #define AFI_PCIE_CONFIG 0x0f8
109 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
110 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
111 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
112 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
113 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
114 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
115 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
116 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
117 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
118 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
119 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
120 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
121 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
123 #define AFI_FUSE 0x104
124 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
126 #define AFI_PEX0_CTRL 0x110
127 #define AFI_PEX1_CTRL 0x118
128 #define AFI_PEX2_CTRL 0x128
129 #define AFI_PEX2_CTRL_T186 0x19c
130 #define AFI_PEX_CTRL_RST (1 << 0)
131 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
132 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
133 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
135 #define AFI_PLLE_CONTROL 0x160
136 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
137 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
139 #define AFI_PEXBIAS_CTRL_0 0x168
141 #define PADS_CTL_SEL 0x0000009C
143 #define PADS_CTL 0x000000A0
144 #define PADS_CTL_IDDQ_1L (1 << 0)
145 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
146 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
148 #define PADS_PLL_CTL_TEGRA20 0x000000B8
149 #define PADS_PLL_CTL_TEGRA30 0x000000B4
150 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
151 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
152 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
153 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
154 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
155 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
156 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
157 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
158 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
159 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
161 #define PADS_REFCLK_CFG0 0x000000C8
162 #define PADS_REFCLK_CFG1 0x000000CC
165 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
166 * entries, one entry per PCIe port. These field definitions and desired
167 * values aren't in the TRM, but do come from NVIDIA.
169 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
170 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
171 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
172 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
174 #define RP_VEND_XP 0x00000F00
175 #define RP_VEND_XP_DL_UP (1 << 30)
177 #define RP_VEND_CTL2 0x00000FA8
178 #define RP_VEND_CTL2_PCA_ENABLE (1 << 7)
180 #define RP_PRIV_MISC 0x00000FE0
181 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
182 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
184 #define RP_LINK_CONTROL_STATUS 0x00000090
185 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
186 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
196 struct tegra_pcie_port
{
197 struct tegra_pcie
*pcie
;
199 struct fdt_resource regs
;
200 unsigned int num_lanes
;
203 struct list_head list
;
206 struct tegra_pcie_soc
{
207 unsigned int num_ports
;
208 unsigned long pads_pll_ctl
;
209 unsigned long tx_ref_sel
;
210 unsigned long afi_pex2_ctrl
;
211 u32 pads_refclk_cfg0
;
212 u32 pads_refclk_cfg1
;
213 bool has_pex_clkreq_en
;
214 bool has_pex_bias_ctrl
;
217 bool force_pca_enable
;
221 struct resource pads
;
225 struct list_head ports
;
228 const struct tegra_pcie_soc
*soc
;
230 #ifdef CONFIG_TEGRA186
233 struct reset_ctl reset_afi
;
234 struct reset_ctl reset_pex
;
235 struct reset_ctl reset_pcie_x
;
236 struct power_domain pwrdom
;
238 struct tegra_xusb_phy
*phy
;
242 static void afi_writel(struct tegra_pcie
*pcie
, unsigned long value
,
243 unsigned long offset
)
245 writel(value
, pcie
->afi
.start
+ offset
);
248 static unsigned long afi_readl(struct tegra_pcie
*pcie
, unsigned long offset
)
250 return readl(pcie
->afi
.start
+ offset
);
253 static void pads_writel(struct tegra_pcie
*pcie
, unsigned long value
,
254 unsigned long offset
)
256 writel(value
, pcie
->pads
.start
+ offset
);
259 #ifndef CONFIG_TEGRA186
260 static unsigned long pads_readl(struct tegra_pcie
*pcie
, unsigned long offset
)
262 return readl(pcie
->pads
.start
+ offset
);
266 static unsigned long rp_readl(struct tegra_pcie_port
*port
,
267 unsigned long offset
)
269 return readl(port
->regs
.start
+ offset
);
272 static void rp_writel(struct tegra_pcie_port
*port
, unsigned long value
,
273 unsigned long offset
)
275 writel(value
, port
->regs
.start
+ offset
);
278 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf
, int where
)
280 return ((where
& 0xf00) << 16) | (PCI_BUS(bdf
) << 16) |
281 (PCI_DEV(bdf
) << 11) | (PCI_FUNC(bdf
) << 8) |
285 static int tegra_pcie_conf_address(struct tegra_pcie
*pcie
, pci_dev_t bdf
,
286 int where
, unsigned long *address
)
288 unsigned int bus
= PCI_BUS(bdf
);
291 unsigned int dev
= PCI_DEV(bdf
);
292 struct tegra_pcie_port
*port
;
294 list_for_each_entry(port
, &pcie
->ports
, list
) {
295 if (port
->index
+ 1 == dev
) {
296 *address
= port
->regs
.start
+ (where
& ~3);
302 #ifdef CONFIG_TEGRA20
303 unsigned int dev
= PCI_DEV(bdf
);
308 *address
= pcie
->cs
.start
+ tegra_pcie_conf_offset(bdf
, where
);
313 static int pci_tegra_read_config(struct udevice
*bus
, pci_dev_t bdf
,
314 uint offset
, ulong
*valuep
,
315 enum pci_size_t size
)
317 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
318 unsigned long address
, value
;
321 err
= tegra_pcie_conf_address(pcie
, bdf
, offset
, &address
);
327 value
= readl(address
);
329 #ifdef CONFIG_TEGRA20
330 /* fixup root port class */
331 if (PCI_BUS(bdf
) == 0) {
332 if ((offset
& ~3) == PCI_CLASS_REVISION
) {
333 value
&= ~0x00ff0000;
334 value
|= PCI_CLASS_BRIDGE_PCI
<< 16;
340 *valuep
= pci_conv_32_to_size(value
, offset
, size
);
345 static int pci_tegra_write_config(struct udevice
*bus
, pci_dev_t bdf
,
346 uint offset
, ulong value
,
347 enum pci_size_t size
)
349 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
350 unsigned long address
;
354 err
= tegra_pcie_conf_address(pcie
, bdf
, offset
, &address
);
358 old
= readl(address
);
359 value
= pci_conv_size_to_32(old
, value
, offset
, size
);
360 writel(value
, address
);
365 static int tegra_pcie_port_parse_dt(ofnode node
, struct tegra_pcie_port
*port
)
370 addr
= ofnode_get_property(node
, "assigned-addresses", &len
);
372 pr_err("property \"assigned-addresses\" not found");
373 return -FDT_ERR_NOTFOUND
;
376 port
->regs
.start
= fdt32_to_cpu(addr
[2]);
377 port
->regs
.end
= port
->regs
.start
+ fdt32_to_cpu(addr
[4]);
382 static int tegra_pcie_get_xbar_config(ofnode node
, u32 lanes
,
383 enum tegra_pci_id id
, unsigned long *xbar
)
389 debug("single-mode configuration\n");
390 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE
;
394 debug("dual-mode configuration\n");
395 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL
;
402 debug("4x1, 2x1 configuration\n");
403 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420
;
407 debug("2x3 configuration\n");
408 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222
;
412 debug("4x1, 1x2 configuration\n");
413 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411
;
421 debug("4x1, 1x1 configuration\n");
422 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1
;
426 debug("2x1, 1x1 configuration\n");
427 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1
;
434 debug("x4 x1 configuration\n");
435 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401
;
439 debug("x2 x1 x1 configuration\n");
440 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211
;
444 debug("x1 x1 x1 configuration\n");
445 *xbar
= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111
;
453 return -FDT_ERR_NOTFOUND
;
456 static int tegra_pcie_parse_port_info(ofnode node
, uint
*index
, uint
*lanes
)
458 struct fdt_pci_addr addr
;
461 err
= ofnode_read_u32_default(node
, "nvidia,num-lanes", -1);
463 pr_err("failed to parse \"nvidia,num-lanes\" property");
469 err
= ofnode_read_pci_addr(node
, 0, "reg", &addr
);
471 pr_err("failed to parse \"reg\" property");
475 *index
= PCI_DEV(addr
.phys_hi
) - 1;
480 int __weak
tegra_pcie_board_init(void)
485 static int tegra_pcie_parse_dt(struct udevice
*dev
, enum tegra_pci_id id
,
486 struct tegra_pcie
*pcie
)
492 err
= dev_read_resource(dev
, 0, &pcie
->pads
);
494 pr_err("resource \"pads\" not found");
498 err
= dev_read_resource(dev
, 1, &pcie
->afi
);
500 pr_err("resource \"afi\" not found");
504 err
= dev_read_resource(dev
, 2, &pcie
->cs
);
506 pr_err("resource \"cs\" not found");
510 err
= tegra_pcie_board_init();
512 pr_err("tegra_pcie_board_init() failed: err=%d", err
);
516 #ifndef CONFIG_TEGRA186
517 pcie
->phy
= tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE
);
519 err
= tegra_xusb_phy_prepare(pcie
->phy
);
521 pr_err("failed to prepare PHY: %d", err
);
527 dev_for_each_subnode(subnode
, dev
) {
528 unsigned int index
= 0, num_lanes
= 0;
529 struct tegra_pcie_port
*port
;
531 err
= tegra_pcie_parse_port_info(subnode
, &index
, &num_lanes
);
533 pr_err("failed to obtain root port info");
537 lanes
|= num_lanes
<< (index
<< 3);
539 if (!ofnode_is_available(subnode
))
542 port
= malloc(sizeof(*port
));
546 memset(port
, 0, sizeof(*port
));
547 port
->num_lanes
= num_lanes
;
550 err
= tegra_pcie_port_parse_dt(subnode
, port
);
556 list_add_tail(&port
->list
, &pcie
->ports
);
560 err
= tegra_pcie_get_xbar_config(dev_ofnode(dev
), lanes
, id
,
563 pr_err("invalid lane configuration");
570 #ifdef CONFIG_TEGRA186
571 static int tegra_pcie_power_on(struct tegra_pcie
*pcie
)
575 ret
= power_domain_on(&pcie
->pwrdom
);
577 pr_err("power_domain_on() failed: %d\n", ret
);
581 ret
= clk_enable(&pcie
->clk_afi
);
583 pr_err("clk_enable(afi) failed: %d\n", ret
);
587 ret
= clk_enable(&pcie
->clk_pex
);
589 pr_err("clk_enable(pex) failed: %d\n", ret
);
593 ret
= reset_deassert(&pcie
->reset_afi
);
595 pr_err("reset_deassert(afi) failed: %d\n", ret
);
599 ret
= reset_deassert(&pcie
->reset_pex
);
601 pr_err("reset_deassert(pex) failed: %d\n", ret
);
608 static int tegra_pcie_power_on(struct tegra_pcie
*pcie
)
610 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
614 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
615 reset_set_enable(PERIPH_ID_PCIEXCLK
, 1);
616 reset_set_enable(PERIPH_ID_AFI
, 1);
617 reset_set_enable(PERIPH_ID_PCIE
, 1);
619 err
= tegra_powergate_power_off(TEGRA_POWERGATE_PCIE
);
621 pr_err("failed to power off PCIe partition: %d", err
);
625 err
= tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE
,
628 pr_err("failed to power up PCIe partition: %d", err
);
632 /* take AFI controller out of reset */
633 reset_set_enable(PERIPH_ID_AFI
, 0);
635 /* enable AFI clock */
636 clock_enable(PERIPH_ID_AFI
);
638 if (soc
->has_cml_clk
) {
639 /* enable CML clock */
640 value
= readl(NV_PA_CLK_RST_BASE
+ 0x48c);
643 writel(value
, NV_PA_CLK_RST_BASE
+ 0x48c);
646 err
= tegra_plle_enable();
648 pr_err("failed to enable PLLE: %d\n", err
);
655 static int tegra_pcie_pll_wait(struct tegra_pcie
*pcie
, unsigned long timeout
)
657 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
658 unsigned long start
= get_timer(0);
661 while (get_timer(start
) < timeout
) {
662 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
663 if (value
& PADS_PLL_CTL_LOCKDET
)
670 static int tegra_pcie_phy_enable(struct tegra_pcie
*pcie
)
672 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
676 /* initialize internal PHY, enable up to 16 PCIe lanes */
677 pads_writel(pcie
, 0, PADS_CTL_SEL
);
679 /* override IDDQ to 1 on all 4 lanes */
680 value
= pads_readl(pcie
, PADS_CTL
);
681 value
|= PADS_CTL_IDDQ_1L
;
682 pads_writel(pcie
, value
, PADS_CTL
);
685 * Set up PHY PLL inputs select PLLE output as refclock, set TX
686 * ref sel to div10 (not div5).
688 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
689 value
&= ~(PADS_PLL_CTL_REFCLK_MASK
| PADS_PLL_CTL_TXCLKREF_MASK
);
690 value
|= PADS_PLL_CTL_REFCLK_INTERNAL_CML
| soc
->tx_ref_sel
;
691 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
694 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
695 value
&= ~PADS_PLL_CTL_RST_B4SM
;
696 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
700 /* take PLL out of reset */
701 value
= pads_readl(pcie
, soc
->pads_pll_ctl
);
702 value
|= PADS_PLL_CTL_RST_B4SM
;
703 pads_writel(pcie
, value
, soc
->pads_pll_ctl
);
705 /* wait for the PLL to lock */
706 err
= tegra_pcie_pll_wait(pcie
, 500);
708 pr_err("PLL failed to lock: %d", err
);
712 /* turn off IDDQ override */
713 value
= pads_readl(pcie
, PADS_CTL
);
714 value
&= ~PADS_CTL_IDDQ_1L
;
715 pads_writel(pcie
, value
, PADS_CTL
);
717 /* enable TX/RX data */
718 value
= pads_readl(pcie
, PADS_CTL
);
719 value
|= PADS_CTL_TX_DATA_EN_1L
| PADS_CTL_RX_DATA_EN_1L
;
720 pads_writel(pcie
, value
, PADS_CTL
);
726 static int tegra_pcie_enable_controller(struct tegra_pcie
*pcie
)
728 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
729 struct tegra_pcie_port
*port
;
733 #ifdef CONFIG_TEGRA186
738 value
= afi_readl(pcie
, AFI_PLLE_CONTROL
);
739 value
&= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL
;
740 value
|= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN
;
741 afi_writel(pcie
, value
, AFI_PLLE_CONTROL
);
744 if (soc
->has_pex_bias_ctrl
)
745 afi_writel(pcie
, 0, AFI_PEXBIAS_CTRL_0
);
747 value
= afi_readl(pcie
, AFI_PCIE_CONFIG
);
748 value
&= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK
;
749 value
|= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL
| pcie
->xbar
;
751 list_for_each_entry(port
, &pcie
->ports
, list
)
752 value
&= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port
->index
);
754 afi_writel(pcie
, value
, AFI_PCIE_CONFIG
);
756 value
= afi_readl(pcie
, AFI_FUSE
);
759 value
&= ~AFI_FUSE_PCIE_T0_GEN2_DIS
;
761 value
|= AFI_FUSE_PCIE_T0_GEN2_DIS
;
763 afi_writel(pcie
, value
, AFI_FUSE
);
765 #ifndef CONFIG_TEGRA186
767 err
= tegra_xusb_phy_enable(pcie
->phy
);
769 err
= tegra_pcie_phy_enable(pcie
);
772 pr_err("failed to power on PHY: %d\n", err
);
777 /* take the PCIEXCLK logic out of reset */
778 #ifdef CONFIG_TEGRA186
779 err
= reset_deassert(&pcie
->reset_pcie_x
);
781 pr_err("reset_deassert(pcie_x) failed: %d\n", err
);
785 reset_set_enable(PERIPH_ID_PCIEXCLK
, 0);
788 /* finally enable PCIe */
789 value
= afi_readl(pcie
, AFI_CONFIGURATION
);
790 value
|= AFI_CONFIGURATION_EN_FPCI
;
791 afi_writel(pcie
, value
, AFI_CONFIGURATION
);
793 /* disable all interrupts */
794 afi_writel(pcie
, 0, AFI_AFI_INTR_ENABLE
);
795 afi_writel(pcie
, 0, AFI_SM_INTR_ENABLE
);
796 afi_writel(pcie
, 0, AFI_INTR_MASK
);
797 afi_writel(pcie
, 0, AFI_FPCI_ERROR_MASKS
);
802 static int tegra_pcie_setup_translations(struct udevice
*bus
)
804 struct tegra_pcie
*pcie
= dev_get_priv(bus
);
805 unsigned long fpci
, axi
, size
;
806 struct pci_region
*io
, *mem
, *pref
;
809 /* BAR 0: type 1 extended configuration space */
811 size
= resource_size(&pcie
->cs
);
812 axi
= pcie
->cs
.start
;
814 afi_writel(pcie
, axi
, AFI_AXI_BAR0_START
);
815 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR0_SZ
);
816 afi_writel(pcie
, fpci
, AFI_FPCI_BAR0
);
818 count
= pci_get_regions(bus
, &io
, &mem
, &pref
);
822 /* BAR 1: downstream I/O */
825 axi
= io
->phys_start
;
827 afi_writel(pcie
, axi
, AFI_AXI_BAR1_START
);
828 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR1_SZ
);
829 afi_writel(pcie
, fpci
, AFI_FPCI_BAR1
);
831 /* BAR 2: prefetchable memory */
832 fpci
= (((pref
->phys_start
>> 12) & 0x0fffffff) << 4) | 0x1;
834 axi
= pref
->phys_start
;
836 afi_writel(pcie
, axi
, AFI_AXI_BAR2_START
);
837 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR2_SZ
);
838 afi_writel(pcie
, fpci
, AFI_FPCI_BAR2
);
840 /* BAR 3: non-prefetchable memory */
841 fpci
= (((mem
->phys_start
>> 12) & 0x0fffffff) << 4) | 0x1;
843 axi
= mem
->phys_start
;
845 afi_writel(pcie
, axi
, AFI_AXI_BAR3_START
);
846 afi_writel(pcie
, size
>> 12, AFI_AXI_BAR3_SZ
);
847 afi_writel(pcie
, fpci
, AFI_FPCI_BAR3
);
849 /* NULL out the remaining BARs as they are not used */
850 afi_writel(pcie
, 0, AFI_AXI_BAR4_START
);
851 afi_writel(pcie
, 0, AFI_AXI_BAR4_SZ
);
852 afi_writel(pcie
, 0, AFI_FPCI_BAR4
);
854 afi_writel(pcie
, 0, AFI_AXI_BAR5_START
);
855 afi_writel(pcie
, 0, AFI_AXI_BAR5_SZ
);
856 afi_writel(pcie
, 0, AFI_FPCI_BAR5
);
858 /* map all upstream transactions as uncached */
859 afi_writel(pcie
, NV_PA_SDRAM_BASE
, AFI_CACHE_BAR0_ST
);
860 afi_writel(pcie
, 0, AFI_CACHE_BAR0_SZ
);
861 afi_writel(pcie
, 0, AFI_CACHE_BAR1_ST
);
862 afi_writel(pcie
, 0, AFI_CACHE_BAR1_SZ
);
864 /* MSI translations are setup only when needed */
865 afi_writel(pcie
, 0, AFI_MSI_FPCI_BAR_ST
);
866 afi_writel(pcie
, 0, AFI_MSI_BAR_SZ
);
867 afi_writel(pcie
, 0, AFI_MSI_AXI_BAR_ST
);
868 afi_writel(pcie
, 0, AFI_MSI_BAR_SZ
);
873 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port
*port
)
875 unsigned long ret
= 0;
877 switch (port
->index
) {
887 ret
= port
->pcie
->soc
->afi_pex2_ctrl
;
894 static void tegra_pcie_port_reset(struct tegra_pcie_port
*port
)
896 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
899 /* pulse reset signel */
900 value
= afi_readl(port
->pcie
, ctrl
);
901 value
&= ~AFI_PEX_CTRL_RST
;
902 afi_writel(port
->pcie
, value
, ctrl
);
906 value
= afi_readl(port
->pcie
, ctrl
);
907 value
|= AFI_PEX_CTRL_RST
;
908 afi_writel(port
->pcie
, value
, ctrl
);
911 static void tegra_pcie_port_enable(struct tegra_pcie_port
*port
)
913 struct tegra_pcie
*pcie
= port
->pcie
;
914 const struct tegra_pcie_soc
*soc
= pcie
->soc
;
915 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
918 /* enable reference clock */
919 value
= afi_readl(pcie
, ctrl
);
920 value
|= AFI_PEX_CTRL_REFCLK_EN
;
922 if (pcie
->soc
->has_pex_clkreq_en
)
923 value
|= AFI_PEX_CTRL_CLKREQ_EN
;
925 value
|= AFI_PEX_CTRL_OVERRIDE_EN
;
927 afi_writel(pcie
, value
, ctrl
);
929 tegra_pcie_port_reset(port
);
931 if (soc
->force_pca_enable
) {
932 value
= rp_readl(port
, RP_VEND_CTL2
);
933 value
|= RP_VEND_CTL2_PCA_ENABLE
;
934 rp_writel(port
, value
, RP_VEND_CTL2
);
937 /* configure the reference clock driver */
938 pads_writel(pcie
, soc
->pads_refclk_cfg0
, PADS_REFCLK_CFG0
);
939 if (soc
->num_ports
> 2)
940 pads_writel(pcie
, soc
->pads_refclk_cfg1
, PADS_REFCLK_CFG1
);
943 static bool tegra_pcie_port_check_link(struct tegra_pcie_port
*port
)
945 unsigned int retries
= 3;
948 value
= rp_readl(port
, RP_PRIV_MISC
);
949 value
&= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT
;
950 value
|= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT
;
951 rp_writel(port
, value
, RP_PRIV_MISC
);
954 unsigned int timeout
= 200;
957 value
= rp_readl(port
, RP_VEND_XP
);
958 if (value
& RP_VEND_XP_DL_UP
)
965 debug("link %u down, retrying\n", port
->index
);
972 value
= rp_readl(port
, RP_LINK_CONTROL_STATUS
);
973 if (value
& RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE
)
980 tegra_pcie_port_reset(port
);
986 static void tegra_pcie_port_disable(struct tegra_pcie_port
*port
)
988 unsigned long ctrl
= tegra_pcie_port_get_pex_ctrl(port
);
991 /* assert port reset */
992 value
= afi_readl(port
->pcie
, ctrl
);
993 value
&= ~AFI_PEX_CTRL_RST
;
994 afi_writel(port
->pcie
, value
, ctrl
);
996 /* disable reference clock */
997 value
= afi_readl(port
->pcie
, ctrl
);
998 value
&= ~AFI_PEX_CTRL_REFCLK_EN
;
999 afi_writel(port
->pcie
, value
, ctrl
);
1002 static void tegra_pcie_port_free(struct tegra_pcie_port
*port
)
1004 list_del(&port
->list
);
1008 static int tegra_pcie_enable(struct tegra_pcie
*pcie
)
1010 struct tegra_pcie_port
*port
, *tmp
;
1012 list_for_each_entry_safe(port
, tmp
, &pcie
->ports
, list
) {
1013 debug("probing port %u, using %u lanes\n", port
->index
,
1016 tegra_pcie_port_enable(port
);
1018 if (tegra_pcie_port_check_link(port
))
1021 debug("link %u down, ignoring\n", port
->index
);
1023 tegra_pcie_port_disable(port
);
1024 tegra_pcie_port_free(port
);
1030 static const struct tegra_pcie_soc pci_tegra_soc
[] = {
1033 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA20
,
1034 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_DIV10
,
1035 .pads_refclk_cfg0
= 0xfa5cfa5c,
1036 .has_pex_clkreq_en
= false,
1037 .has_pex_bias_ctrl
= false,
1038 .has_cml_clk
= false,
1043 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1044 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1045 .afi_pex2_ctrl
= AFI_PEX2_CTRL
,
1046 .pads_refclk_cfg0
= 0xfa5cfa5c,
1047 .pads_refclk_cfg1
= 0xfa5cfa5c,
1048 .has_pex_clkreq_en
= true,
1049 .has_pex_bias_ctrl
= true,
1050 .has_cml_clk
= true,
1055 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1056 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1057 .pads_refclk_cfg0
= 0x44ac44ac,
1058 .has_pex_clkreq_en
= true,
1059 .has_pex_bias_ctrl
= true,
1060 .has_cml_clk
= true,
1065 .pads_pll_ctl
= PADS_PLL_CTL_TEGRA30
,
1066 .tx_ref_sel
= PADS_PLL_CTL_TXCLKREF_BUF_EN
,
1067 .pads_refclk_cfg0
= 0x90b890b8,
1068 .has_pex_clkreq_en
= true,
1069 .has_pex_bias_ctrl
= true,
1070 .has_cml_clk
= true,
1072 .force_pca_enable
= true,
1076 .afi_pex2_ctrl
= AFI_PEX2_CTRL_T186
,
1077 .pads_refclk_cfg0
= 0x80b880b8,
1078 .pads_refclk_cfg1
= 0x000480b8,
1079 .has_pex_clkreq_en
= true,
1080 .has_pex_bias_ctrl
= true,
1085 static int pci_tegra_ofdata_to_platdata(struct udevice
*dev
)
1087 struct tegra_pcie
*pcie
= dev_get_priv(dev
);
1088 enum tegra_pci_id id
;
1090 id
= dev_get_driver_data(dev
);
1091 pcie
->soc
= &pci_tegra_soc
[id
];
1093 INIT_LIST_HEAD(&pcie
->ports
);
1095 if (tegra_pcie_parse_dt(dev
, id
, pcie
))
1101 static int pci_tegra_probe(struct udevice
*dev
)
1103 struct tegra_pcie
*pcie
= dev_get_priv(dev
);
1106 #ifdef CONFIG_TEGRA186
1107 err
= clk_get_by_name(dev
, "afi", &pcie
->clk_afi
);
1109 debug("clk_get_by_name(afi) failed: %d\n", err
);
1113 err
= clk_get_by_name(dev
, "pex", &pcie
->clk_pex
);
1115 debug("clk_get_by_name(pex) failed: %d\n", err
);
1119 err
= reset_get_by_name(dev
, "afi", &pcie
->reset_afi
);
1121 debug("reset_get_by_name(afi) failed: %d\n", err
);
1125 err
= reset_get_by_name(dev
, "pex", &pcie
->reset_pex
);
1127 debug("reset_get_by_name(pex) failed: %d\n", err
);
1131 err
= reset_get_by_name(dev
, "pcie_x", &pcie
->reset_pcie_x
);
1133 debug("reset_get_by_name(pcie_x) failed: %d\n", err
);
1137 err
= power_domain_get(dev
, &pcie
->pwrdom
);
1139 debug("power_domain_get() failed: %d\n", err
);
1144 err
= tegra_pcie_power_on(pcie
);
1146 pr_err("failed to power on");
1150 err
= tegra_pcie_enable_controller(pcie
);
1152 pr_err("failed to enable controller");
1156 err
= tegra_pcie_setup_translations(dev
);
1158 pr_err("failed to decode ranges");
1162 err
= tegra_pcie_enable(pcie
);
1164 pr_err("failed to enable PCIe");
1171 static const struct dm_pci_ops pci_tegra_ops
= {
1172 .read_config
= pci_tegra_read_config
,
1173 .write_config
= pci_tegra_write_config
,
1176 static const struct udevice_id pci_tegra_ids
[] = {
1177 { .compatible
= "nvidia,tegra20-pcie", .data
= TEGRA20_PCIE
},
1178 { .compatible
= "nvidia,tegra30-pcie", .data
= TEGRA30_PCIE
},
1179 { .compatible
= "nvidia,tegra124-pcie", .data
= TEGRA124_PCIE
},
1180 { .compatible
= "nvidia,tegra210-pcie", .data
= TEGRA210_PCIE
},
1181 { .compatible
= "nvidia,tegra186-pcie", .data
= TEGRA186_PCIE
},
1185 U_BOOT_DRIVER(pci_tegra
) = {
1186 .name
= "pci_tegra",
1188 .of_match
= pci_tegra_ids
,
1189 .ops
= &pci_tegra_ops
,
1190 .ofdata_to_platdata
= pci_tegra_ofdata_to_platdata
,
1191 .probe
= pci_tegra_probe
,
1192 .priv_auto_alloc_size
= sizeof(struct tegra_pcie
),