2 * Freescale i.MX6 PCI Express Root-Complex driver
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 * Based on upstream Linux kernel driver:
7 * pci-imx6.c: Sean Cross <xobs@kosagi.com>
8 * pcie-designware.c: Jingoo Han <jg1.han@samsung.com>
10 * SPDX-License-Identifier: GPL-2.0
15 #include <asm/arch/clock.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/crm_regs.h>
20 #include <linux/sizes.h>
22 #include <asm/arch/sys_proto.h>
24 #define PCI_ACCESS_READ 0
25 #define PCI_ACCESS_WRITE 1
28 #define MX6_DBI_ADDR 0x08ffc000
29 #define MX6_IO_ADDR 0x08000000
30 #define MX6_MEM_ADDR 0x08100000
31 #define MX6_ROOT_ADDR 0x08f00000
33 #define MX6_DBI_ADDR 0x01ffc000
34 #define MX6_IO_ADDR 0x01000000
35 #define MX6_MEM_ADDR 0x01100000
36 #define MX6_ROOT_ADDR 0x01f00000
38 #define MX6_DBI_SIZE 0x4000
39 #define MX6_IO_SIZE 0x100000
40 #define MX6_MEM_SIZE 0xe00000
41 #define MX6_ROOT_SIZE 0xfc000
43 /* PCIe Port Logic registers (memory-mapped) */
44 #define PL_OFFSET 0x700
45 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
46 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
47 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
48 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
49 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
50 #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4)
51 #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29)
53 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
54 #define PCIE_PHY_CTRL_DATA_LOC 0
55 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
56 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
57 #define PCIE_PHY_CTRL_WR_LOC 18
58 #define PCIE_PHY_CTRL_RD_LOC 19
60 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
61 #define PCIE_PHY_STAT_DATA_LOC 0
62 #define PCIE_PHY_STAT_ACK_LOC 16
64 /* PHY registers (not memory-mapped) */
65 #define PCIE_PHY_RX_ASIC_OUT 0x100D
67 #define PHY_RX_OVRD_IN_LO 0x1005
68 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
69 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
71 #define PCIE_PHY_PUP_REQ (1 << 7)
74 #define PCIE_ATU_VIEWPORT 0x900
75 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
76 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
77 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
78 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
79 #define PCIE_ATU_CR1 0x904
80 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
81 #define PCIE_ATU_TYPE_IO (0x2 << 0)
82 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
83 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
84 #define PCIE_ATU_CR2 0x908
85 #define PCIE_ATU_ENABLE (0x1 << 31)
86 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
87 #define PCIE_ATU_LOWER_BASE 0x90C
88 #define PCIE_ATU_UPPER_BASE 0x910
89 #define PCIE_ATU_LIMIT 0x914
90 #define PCIE_ATU_LOWER_TARGET 0x918
91 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
92 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
93 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
94 #define PCIE_ATU_UPPER_TARGET 0x91C
97 * PHY access functions
99 static int pcie_phy_poll_ack(void __iomem
*dbi_base
, int exp_val
)
102 u32 max_iterations
= 10;
103 u32 wait_counter
= 0;
106 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
107 val
= (val
>> PCIE_PHY_STAT_ACK_LOC
) & 0x1;
114 } while (wait_counter
< max_iterations
);
119 static int pcie_phy_wait_ack(void __iomem
*dbi_base
, int addr
)
124 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
125 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
127 val
|= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC
);
128 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
130 ret
= pcie_phy_poll_ack(dbi_base
, 1);
134 val
= addr
<< PCIE_PHY_CTRL_DATA_LOC
;
135 writel(val
, dbi_base
+ PCIE_PHY_CTRL
);
137 ret
= pcie_phy_poll_ack(dbi_base
, 0);
144 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
145 static int pcie_phy_read(void __iomem
*dbi_base
, int addr
, int *data
)
150 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
154 /* assert Read signal */
155 phy_ctl
= 0x1 << PCIE_PHY_CTRL_RD_LOC
;
156 writel(phy_ctl
, dbi_base
+ PCIE_PHY_CTRL
);
158 ret
= pcie_phy_poll_ack(dbi_base
, 1);
162 val
= readl(dbi_base
+ PCIE_PHY_STAT
);
163 *data
= val
& 0xffff;
165 /* deassert Read signal */
166 writel(0x00, dbi_base
+ PCIE_PHY_CTRL
);
168 ret
= pcie_phy_poll_ack(dbi_base
, 0);
175 static int pcie_phy_write(void __iomem
*dbi_base
, int addr
, int data
)
182 ret
= pcie_phy_wait_ack(dbi_base
, addr
);
186 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
187 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
190 var
|= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC
);
191 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
193 ret
= pcie_phy_poll_ack(dbi_base
, 1);
197 /* deassert cap data */
198 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
199 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
201 /* wait for ack de-assertion */
202 ret
= pcie_phy_poll_ack(dbi_base
, 0);
206 /* assert wr signal */
207 var
= 0x1 << PCIE_PHY_CTRL_WR_LOC
;
208 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
211 ret
= pcie_phy_poll_ack(dbi_base
, 1);
215 /* deassert wr signal */
216 var
= data
<< PCIE_PHY_CTRL_DATA_LOC
;
217 writel(var
, dbi_base
+ PCIE_PHY_CTRL
);
219 /* wait for ack de-assertion */
220 ret
= pcie_phy_poll_ack(dbi_base
, 0);
224 writel(0x0, dbi_base
+ PCIE_PHY_CTRL
);
229 static int imx6_pcie_link_up(void)
234 /* link is debug bit 36, debug register 1 starts at bit 32 */
235 rc
= readl(MX6_DBI_ADDR
+ PCIE_PHY_DEBUG_R1
);
236 if ((rc
& PCIE_PHY_DEBUG_R1_LINK_UP
) &&
237 !(rc
& PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING
))
241 * From L0, initiate MAC entry to gen2 if EP/RC supports gen2.
242 * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2).
243 * If (MAC/LTSSM.state == Recovery.RcvrLock)
244 * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition
247 pcie_phy_read((void *)MX6_DBI_ADDR
, PCIE_PHY_RX_ASIC_OUT
, &rx_valid
);
248 ltssm
= readl(MX6_DBI_ADDR
+ PCIE_PHY_DEBUG_R0
) & 0x3F;
256 printf("transition to gen2 is stuck, reset PHY!\n");
258 pcie_phy_read((void *)MX6_DBI_ADDR
, PHY_RX_OVRD_IN_LO
, &temp
);
259 temp
|= (PHY_RX_OVRD_IN_LO_RX_DATA_EN
| PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
260 pcie_phy_write((void *)MX6_DBI_ADDR
, PHY_RX_OVRD_IN_LO
, temp
);
264 pcie_phy_read((void *)MX6_DBI_ADDR
, PHY_RX_OVRD_IN_LO
, &temp
);
265 temp
&= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN
| PHY_RX_OVRD_IN_LO_RX_PLL_EN
);
266 pcie_phy_write((void *)MX6_DBI_ADDR
, PHY_RX_OVRD_IN_LO
, temp
);
274 static int imx_pcie_regions_setup(void)
277 * i.MX6 defines 16MB in the AXI address map for PCIe.
279 * That address space excepted the pcie registers is
280 * split and defined into different regions by iATU,
281 * with sizes and offsets as follows:
283 * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO
284 * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM
285 * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers
288 /* CMD reg:I/O space, MEM space, and Bus Master Enable */
289 setbits_le32(MX6_DBI_ADDR
| PCI_COMMAND
,
290 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
292 /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */
293 setbits_le32(MX6_DBI_ADDR
+ PCI_CLASS_REVISION
,
294 PCI_CLASS_BRIDGE_PCI
<< 16);
296 /* Region #0 is used for Outbound CFG space access. */
297 writel(0, MX6_DBI_ADDR
+ PCIE_ATU_VIEWPORT
);
299 writel(MX6_ROOT_ADDR
, MX6_DBI_ADDR
+ PCIE_ATU_LOWER_BASE
);
300 writel(0, MX6_DBI_ADDR
+ PCIE_ATU_UPPER_BASE
);
301 writel(MX6_ROOT_ADDR
+ MX6_ROOT_SIZE
, MX6_DBI_ADDR
+ PCIE_ATU_LIMIT
);
303 writel(0, MX6_DBI_ADDR
+ PCIE_ATU_LOWER_TARGET
);
304 writel(0, MX6_DBI_ADDR
+ PCIE_ATU_UPPER_TARGET
);
305 writel(PCIE_ATU_TYPE_CFG0
, MX6_DBI_ADDR
+ PCIE_ATU_CR1
);
306 writel(PCIE_ATU_ENABLE
, MX6_DBI_ADDR
+ PCIE_ATU_CR2
);
312 * PCI Express accessors
314 static uint32_t get_bus_address(pci_dev_t d
, int where
)
318 /* Reconfigure Region #0 */
319 writel(0, MX6_DBI_ADDR
+ PCIE_ATU_VIEWPORT
);
322 writel(PCIE_ATU_TYPE_CFG0
, MX6_DBI_ADDR
+ PCIE_ATU_CR1
);
324 writel(PCIE_ATU_TYPE_CFG1
, MX6_DBI_ADDR
+ PCIE_ATU_CR1
);
326 if (PCI_BUS(d
) == 0) {
327 va_address
= MX6_DBI_ADDR
;
329 writel(d
<< 8, MX6_DBI_ADDR
+ PCIE_ATU_LOWER_TARGET
);
330 va_address
= MX6_IO_ADDR
+ SZ_16M
- SZ_1M
;
333 va_address
+= (where
& ~0x3);
338 static int imx_pcie_addr_valid(pci_dev_t d
)
340 if ((PCI_BUS(d
) == 0) && (PCI_DEV(d
) > 1))
342 if ((PCI_BUS(d
) == 1) && (PCI_DEV(d
) > 0))
348 * Replace the original ARM DABT handler with a simple jump-back one.
350 * The problem here is that if we have a PCIe bridge attached to this PCIe
351 * controller, but no PCIe device is connected to the bridges' downstream
352 * port, the attempt to read/write from/to the config space will produce
353 * a DABT. This is a behavior of the controller and can not be disabled
356 * To work around the problem, we backup the current DABT handler address
357 * and replace it with our own DABT handler, which only bounces right back
360 static void imx_pcie_fix_dabt_handler(bool set
)
362 extern uint32_t *_data_abort
;
363 uint32_t *data_abort_addr
= (uint32_t *)&_data_abort
;
365 static const uint32_t data_abort_bounce_handler
= 0xe25ef004;
366 uint32_t data_abort_bounce_addr
= (uint32_t)&data_abort_bounce_handler
;
368 static uint32_t data_abort_backup
;
371 data_abort_backup
= *data_abort_addr
;
372 *data_abort_addr
= data_abort_bounce_addr
;
374 *data_abort_addr
= data_abort_backup
;
378 static int imx_pcie_read_config(struct pci_controller
*hose
, pci_dev_t d
,
384 ret
= imx_pcie_addr_valid(d
);
390 va_address
= get_bus_address(d
, where
);
393 * Read the PCIe config space. We must replace the DABT handler
394 * here in case we got data abort from the PCIe controller, see
395 * imx_pcie_fix_dabt_handler() description. Note that writing the
396 * "val" with valid value is also imperative here as in case we
397 * did got DABT, the val would contain random value.
399 imx_pcie_fix_dabt_handler(true);
400 writel(0xffffffff, val
);
401 *val
= readl(va_address
);
402 imx_pcie_fix_dabt_handler(false);
407 static int imx_pcie_write_config(struct pci_controller
*hose
, pci_dev_t d
,
410 uint32_t va_address
= 0;
413 ret
= imx_pcie_addr_valid(d
);
417 va_address
= get_bus_address(d
, where
);
420 * Write the PCIe config space. We must replace the DABT handler
421 * here in case we got data abort from the PCIe controller, see
422 * imx_pcie_fix_dabt_handler() description.
424 imx_pcie_fix_dabt_handler(true);
425 writel(val
, va_address
);
426 imx_pcie_fix_dabt_handler(false);
434 static int imx6_pcie_assert_core_reset(void)
436 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
439 setbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_PCIE_SW_RST
);
441 #if defined(CONFIG_MX6SX)
442 struct gpc
*gpc_regs
= (struct gpc
*)GPC_BASE_ADDR
;
444 /* SSP_EN is not used on MX6SX anymore */
445 setbits_le32(&iomuxc_regs
->gpr
[12], IOMUXC_GPR12_TEST_POWERDOWN
);
446 /* Force PCIe PHY reset */
447 setbits_le32(&iomuxc_regs
->gpr
[5], IOMUXC_GPR5_PCIE_BTNRST
);
448 /* Power up PCIe PHY */
449 setbits_le32(&gpc_regs
->cntr
, PCIE_PHY_PUP_REQ
);
452 * If the bootloader already enabled the link we need some special
453 * handling to get the core back into a state where it is safe to
454 * touch it for configuration. As there is no dedicated reset signal
455 * wired up for MX6QDL, we need to manually force LTSSM into "detect"
456 * state before completely disabling LTSSM, which is a prerequisite
457 * for core configuration.
459 * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
460 * indication that the bootloader activated the link.
463 u32 val
, gpr1
, gpr12
;
465 gpr1
= readl(&iomuxc_regs
->gpr
[1]);
466 gpr12
= readl(&iomuxc_regs
->gpr
[12]);
467 if ((gpr1
& IOMUXC_GPR1_PCIE_REF_CLK_EN
) &&
468 (gpr12
& IOMUXC_GPR12_PCIE_CTL_2
)) {
469 val
= readl(MX6_DBI_ADDR
+ PCIE_PL_PFLR
);
470 val
&= ~PCIE_PL_PFLR_LINK_STATE_MASK
;
471 val
|= PCIE_PL_PFLR_FORCE_LINK
;
473 imx_pcie_fix_dabt_handler(true);
474 writel(val
, MX6_DBI_ADDR
+ PCIE_PL_PFLR
);
475 imx_pcie_fix_dabt_handler(false);
477 gpr12
&= ~IOMUXC_GPR12_PCIE_CTL_2
;
478 writel(val
, &iomuxc_regs
->gpr
[12]);
481 setbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_TEST_POWERDOWN
);
482 clrbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_REF_SSP_EN
);
488 static int imx6_pcie_init_phy(void)
490 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
492 clrbits_le32(&iomuxc_regs
->gpr
[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE
);
494 clrsetbits_le32(&iomuxc_regs
->gpr
[12],
495 IOMUXC_GPR12_DEVICE_TYPE_MASK
,
496 IOMUXC_GPR12_DEVICE_TYPE_RC
);
497 clrsetbits_le32(&iomuxc_regs
->gpr
[12],
498 IOMUXC_GPR12_LOS_LEVEL_MASK
,
499 IOMUXC_GPR12_LOS_LEVEL_9
);
502 clrsetbits_le32(&iomuxc_regs
->gpr
[12],
503 IOMUXC_GPR12_RX_EQ_MASK
,
504 IOMUXC_GPR12_RX_EQ_2
);
507 writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET
) |
508 (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET
) |
509 (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET
) |
510 (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET
) |
511 (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET
),
512 &iomuxc_regs
->gpr
[8]);
517 __weak
int imx6_pcie_toggle_power(void)
519 #ifdef CONFIG_PCIE_IMX_POWER_GPIO
520 gpio_direction_output(CONFIG_PCIE_IMX_POWER_GPIO
, 0);
522 gpio_set_value(CONFIG_PCIE_IMX_POWER_GPIO
, 1);
528 __weak
int imx6_pcie_toggle_reset(void)
531 * See 'PCI EXPRESS BASE SPECIFICATION, REV 3.0, SECTION 6.6.1'
532 * for detailed understanding of the PCIe CR reset logic.
534 * The PCIe #PERST reset line _MUST_ be connected, otherwise your
535 * design does not conform to the specification. You must wait at
536 * least 20 ms after de-asserting the #PERST so the EP device can
537 * do self-initialisation.
539 * In case your #PERST pin is connected to a plain GPIO pin of the
540 * CPU, you can define CONFIG_PCIE_IMX_PERST_GPIO in your board's
541 * configuration file and the condition below will handle the rest
542 * of the reset toggling.
544 * In case your #PERST toggling logic is more complex, for example
545 * connected via CPLD or somesuch, you can override this function
546 * in your board file and implement reset logic as needed. You must
547 * not forget to wait at least 20 ms after de-asserting #PERST in
548 * this case either though.
550 * In case your #PERST line of the PCIe EP device is not connected
551 * at all, your design is broken and you should fix your design,
552 * otherwise you will observe problems like for example the link
553 * not coming up after rebooting the system back from running Linux
554 * that uses the PCIe as well OR the PCIe link might not come up in
555 * Linux at all in the first place since it's in some non-reset
556 * state due to being previously used in U-Boot.
558 #ifdef CONFIG_PCIE_IMX_PERST_GPIO
559 gpio_direction_output(CONFIG_PCIE_IMX_PERST_GPIO
, 0);
561 gpio_set_value(CONFIG_PCIE_IMX_PERST_GPIO
, 1);
564 puts("WARNING: Make sure the PCIe #PERST line is connected!\n");
569 static int imx6_pcie_deassert_core_reset(void)
571 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
573 imx6_pcie_toggle_power();
578 clrbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_PCIE_SW_RST
);
581 * Wait for the clock to settle a bit, when the clock are sourced
582 * from the CPU, we need about 30 ms to settle.
586 #if defined(CONFIG_MX6SX)
587 /* SSP_EN is not used on MX6SX anymore */
588 clrbits_le32(&iomuxc_regs
->gpr
[12], IOMUXC_GPR12_TEST_POWERDOWN
);
589 /* Clear PCIe PHY reset bit */
590 clrbits_le32(&iomuxc_regs
->gpr
[5], IOMUXC_GPR5_PCIE_BTNRST
);
593 clrbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_TEST_POWERDOWN
);
594 setbits_le32(&iomuxc_regs
->gpr
[1], IOMUXC_GPR1_REF_SSP_EN
);
597 imx6_pcie_toggle_reset();
602 static int imx_pcie_link_up(void)
604 struct iomuxc
*iomuxc_regs
= (struct iomuxc
*)IOMUXC_BASE_ADDR
;
608 imx6_pcie_assert_core_reset();
609 imx6_pcie_init_phy();
610 imx6_pcie_deassert_core_reset();
612 imx_pcie_regions_setup();
615 * FIXME: Force the PCIe RC to Gen1 operation
616 * The RC must be forced into Gen1 mode before bringing the link
617 * up, otherwise no downstream devices are detected. After the
618 * link is up, a managed Gen1->Gen2 transition can be initiated.
620 tmp
= readl(MX6_DBI_ADDR
+ 0x7c);
623 writel(tmp
, MX6_DBI_ADDR
+ 0x7c);
625 /* LTSSM enable, starting link. */
626 setbits_le32(&iomuxc_regs
->gpr
[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE
);
628 while (!imx6_pcie_link_up()) {
632 #ifdef CONFIG_PCI_SCAN_SHOW
633 puts("PCI: pcie phy link never came up\n");
635 debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
636 readl(MX6_DBI_ADDR
+ PCIE_PHY_DEBUG_R0
),
637 readl(MX6_DBI_ADDR
+ PCIE_PHY_DEBUG_R1
));
645 void imx_pcie_init(void)
647 /* Static instance of the controller. */
648 static struct pci_controller pcc
;
649 struct pci_controller
*hose
= &pcc
;
652 memset(&pcc
, 0, sizeof(pcc
));
655 pci_set_region(&hose
->regions
[0],
656 MX6_IO_ADDR
, MX6_IO_ADDR
,
657 MX6_IO_SIZE
, PCI_REGION_IO
);
659 /* PCI memory space */
660 pci_set_region(&hose
->regions
[1],
661 MX6_MEM_ADDR
, MX6_MEM_ADDR
,
662 MX6_MEM_SIZE
, PCI_REGION_MEM
);
664 /* System memory space */
665 pci_set_region(&hose
->regions
[2],
666 MMDC0_ARB_BASE_ADDR
, MMDC0_ARB_BASE_ADDR
,
667 0xefffffff, PCI_REGION_MEM
| PCI_REGION_SYS_MEMORY
);
669 hose
->region_count
= 3;
672 pci_hose_read_config_byte_via_dword
,
673 pci_hose_read_config_word_via_dword
,
674 imx_pcie_read_config
,
675 pci_hose_write_config_byte_via_dword
,
676 pci_hose_write_config_word_via_dword
,
677 imx_pcie_write_config
);
679 /* Start the controller. */
680 ret
= imx_pcie_link_up();
683 pci_register_hose(hose
);
684 hose
->last_busno
= pci_hose_scan(hose
);
688 void imx_pcie_remove(void)
690 imx6_pcie_assert_core_reset();
693 /* Probe function. */
694 void pci_init_board(void)