2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fsl_serdes.h>
14 #ifndef CONFIG_LS102XA
15 #include <asm/arch/fdt.h>
16 #include <asm/arch/soc.h>
19 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
20 #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
23 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
24 #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
27 #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
28 #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
31 #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
32 #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
36 #define PCIE_ATU_VIEWPORT 0x900
37 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
38 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
39 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
40 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
41 #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
42 #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
43 #define PCIE_ATU_CR1 0x904
44 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
45 #define PCIE_ATU_TYPE_IO (0x2 << 0)
46 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
47 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
48 #define PCIE_ATU_CR2 0x908
49 #define PCIE_ATU_ENABLE (0x1 << 31)
50 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
51 #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
52 #define PCIE_ATU_LOWER_BASE 0x90C
53 #define PCIE_ATU_UPPER_BASE 0x910
54 #define PCIE_ATU_LIMIT 0x914
55 #define PCIE_ATU_LOWER_TARGET 0x918
56 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
57 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
58 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
59 #define PCIE_ATU_UPPER_TARGET 0x91C
61 #define PCIE_DBI_RO_WR_EN 0x8bc
63 #define PCIE_LINK_CAP 0x7c
64 #define PCIE_LINK_SPEED_MASK 0xf
65 #define PCIE_LINK_STA 0x82
67 #define LTSSM_STATE_MASK 0x3f
68 #define LTSSM_PCIE_L0 0x11 /* L0 state */
70 #define PCIE_DBI_SIZE 0x100000 /* 1M */
72 #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
73 #define PCIE_LCTRL0_VF(vf) ((vf) << 22)
74 #define PCIE_LCTRL0_PF(pf) ((pf) << 16)
75 #define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
76 #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
77 PCIE_LCTRL0_VF(vf) | \
78 ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
79 PCIE_LCTRL0_CFG2_ENABLE)
81 #define PCIE_NO_SRIOV_BAR_BASE 0x1000
84 #define PCIE_VF_NUM 64
86 #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
87 #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
88 #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
89 #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
94 void __iomem
*va_cfg0
;
95 void __iomem
*va_cfg1
;
96 struct pci_controller hose
;
115 #define SET_LS_PCIE_INFO(x, num) \
117 x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
118 x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
119 x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
120 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
121 x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
122 x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
123 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
124 x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
125 x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
126 x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
127 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
128 x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
129 x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
130 x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
131 CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
132 x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
136 #ifdef CONFIG_LS102XA
137 #include <asm/arch/immap_ls102xa.h>
139 /* PEX1/2 Misc Ports Status Register */
140 #define LTSSM_STATE_SHIFT 20
142 static int ls_pcie_link_state(struct ls_pcie
*pcie
)
145 struct ccsr_scfg
*scfg
= (struct ccsr_scfg
*)CONFIG_SYS_FSL_SCFG_ADDR
;
147 state
= in_be32(&scfg
->pexmscportsr
[pcie
->idx
]);
148 state
= (state
>> LTSSM_STATE_SHIFT
) & LTSSM_STATE_MASK
;
149 if (state
< LTSSM_PCIE_L0
) {
150 debug("....PCIe link error. LTSSM=0x%02x.\n", state
);
157 static int ls_pcie_link_state(struct ls_pcie
*pcie
)
161 state
= pex_lut_in32(pcie
->dbi
+ PCIE_LUT_BASE
+ PCIE_LUT_DBG
) &
163 if (state
< LTSSM_PCIE_L0
) {
164 debug("....PCIe link error. LTSSM=0x%02x.\n", state
);
172 static int ls_pcie_link_up(struct ls_pcie
*pcie
)
177 state
= ls_pcie_link_state(pcie
);
181 /* Try to download speed to gen1 */
182 cap
= readl(pcie
->dbi
+ PCIE_LINK_CAP
);
183 writel((cap
& (~PCIE_LINK_SPEED_MASK
)) | 1, pcie
->dbi
+ PCIE_LINK_CAP
);
185 * Notice: the following delay has critical impact on link training
186 * if too short (<30ms) the link doesn't get up.
189 state
= ls_pcie_link_state(pcie
);
193 writel(cap
, pcie
->dbi
+ PCIE_LINK_CAP
);
198 static void ls_pcie_cfg0_set_busdev(struct ls_pcie
*pcie
, u32 busdev
)
200 writel(PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
201 pcie
->dbi
+ PCIE_ATU_VIEWPORT
);
202 writel(busdev
, pcie
->dbi
+ PCIE_ATU_LOWER_TARGET
);
205 static void ls_pcie_cfg1_set_busdev(struct ls_pcie
*pcie
, u32 busdev
)
207 writel(PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
208 pcie
->dbi
+ PCIE_ATU_VIEWPORT
);
209 writel(busdev
, pcie
->dbi
+ PCIE_ATU_LOWER_TARGET
);
212 static void ls_pcie_iatu_outbound_set(struct ls_pcie
*pcie
, int idx
, int type
,
213 u64 phys
, u64 bus_addr
, pci_size_t size
)
215 writel(PCIE_ATU_REGION_OUTBOUND
| idx
, pcie
->dbi
+ PCIE_ATU_VIEWPORT
);
216 writel((u32
)phys
, pcie
->dbi
+ PCIE_ATU_LOWER_BASE
);
217 writel(phys
>> 32, pcie
->dbi
+ PCIE_ATU_UPPER_BASE
);
218 writel(phys
+ size
- 1, pcie
->dbi
+ PCIE_ATU_LIMIT
);
219 writel((u32
)bus_addr
, pcie
->dbi
+ PCIE_ATU_LOWER_TARGET
);
220 writel(bus_addr
>> 32, pcie
->dbi
+ PCIE_ATU_UPPER_TARGET
);
221 writel(type
, pcie
->dbi
+ PCIE_ATU_CR1
);
222 writel(PCIE_ATU_ENABLE
, pcie
->dbi
+ PCIE_ATU_CR2
);
225 /* Use bar match mode and MEM type as default */
226 static void ls_pcie_iatu_inbound_set(struct ls_pcie
*pcie
, int idx
,
229 writel(PCIE_ATU_REGION_INBOUND
| idx
, pcie
->dbi
+ PCIE_ATU_VIEWPORT
);
230 writel((u32
)phys
, pcie
->dbi
+ PCIE_ATU_LOWER_TARGET
);
231 writel(phys
>> 32, pcie
->dbi
+ PCIE_ATU_UPPER_TARGET
);
232 writel(PCIE_ATU_TYPE_MEM
, pcie
->dbi
+ PCIE_ATU_CR1
);
233 writel(PCIE_ATU_ENABLE
| PCIE_ATU_BAR_MODE_ENABLE
|
234 PCIE_ATU_BAR_NUM(bar
), pcie
->dbi
+ PCIE_ATU_CR2
);
237 static void ls_pcie_setup_atu(struct ls_pcie
*pcie
, struct ls_pcie_info
*info
)
243 /* ATU 0 : OUTBOUND : CFG0 */
244 ls_pcie_iatu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX0
,
249 /* ATU 1 : OUTBOUND : CFG1 */
250 ls_pcie_iatu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX1
,
255 /* ATU 2 : OUTBOUND : MEM */
256 ls_pcie_iatu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX2
,
261 /* ATU 3 : OUTBOUND : IO */
262 ls_pcie_iatu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX3
,
269 for (i
= 0; i
<= PCIE_ATU_REGION_INDEX3
; i
++) {
270 writel(PCIE_ATU_REGION_OUTBOUND
| i
,
271 pcie
->dbi
+ PCIE_ATU_VIEWPORT
);
272 debug("iATU%d:\n", i
);
273 debug("\tLOWER PHYS 0x%08x\n",
274 readl(pcie
->dbi
+ PCIE_ATU_LOWER_BASE
));
275 debug("\tUPPER PHYS 0x%08x\n",
276 readl(pcie
->dbi
+ PCIE_ATU_UPPER_BASE
));
277 debug("\tLOWER BUS 0x%08x\n",
278 readl(pcie
->dbi
+ PCIE_ATU_LOWER_TARGET
));
279 debug("\tUPPER BUS 0x%08x\n",
280 readl(pcie
->dbi
+ PCIE_ATU_UPPER_TARGET
));
281 debug("\tLIMIT 0x%08x\n",
282 readl(pcie
->dbi
+ PCIE_ATU_LIMIT
));
283 debug("\tCR1 0x%08x\n",
284 readl(pcie
->dbi
+ PCIE_ATU_CR1
));
285 debug("\tCR2 0x%08x\n",
286 readl(pcie
->dbi
+ PCIE_ATU_CR2
));
291 int pci_skip_dev(struct pci_controller
*hose
, pci_dev_t dev
)
293 /* Do not skip controller */
297 static int ls_pcie_addr_valid(struct pci_controller
*hose
, pci_dev_t d
)
302 /* Controller does not support multi-function in RC mode */
303 if ((PCI_BUS(d
) == hose
->first_busno
) && (PCI_FUNC(d
) > 0))
309 static int ls_pcie_read_config(struct pci_controller
*hose
, pci_dev_t d
,
312 struct ls_pcie
*pcie
= hose
->priv_data
;
315 if (ls_pcie_addr_valid(hose
, d
)) {
320 if (PCI_BUS(d
) == hose
->first_busno
) {
321 addr
= pcie
->dbi
+ (where
& ~0x3);
323 busdev
= PCIE_ATU_BUS(PCI_BUS(d
)) |
324 PCIE_ATU_DEV(PCI_DEV(d
)) |
325 PCIE_ATU_FUNC(PCI_FUNC(d
));
327 if (PCI_BUS(d
) == hose
->first_busno
+ 1) {
328 ls_pcie_cfg0_set_busdev(pcie
, busdev
);
329 addr
= pcie
->va_cfg0
+ (where
& ~0x3);
331 ls_pcie_cfg1_set_busdev(pcie
, busdev
);
332 addr
= pcie
->va_cfg1
+ (where
& ~0x3);
341 static int ls_pcie_write_config(struct pci_controller
*hose
, pci_dev_t d
,
344 struct ls_pcie
*pcie
= hose
->priv_data
;
347 if (ls_pcie_addr_valid(hose
, d
))
350 if (PCI_BUS(d
) == hose
->first_busno
) {
351 addr
= pcie
->dbi
+ (where
& ~0x3);
353 busdev
= PCIE_ATU_BUS(PCI_BUS(d
)) |
354 PCIE_ATU_DEV(PCI_DEV(d
)) |
355 PCIE_ATU_FUNC(PCI_FUNC(d
));
357 if (PCI_BUS(d
) == hose
->first_busno
+ 1) {
358 ls_pcie_cfg0_set_busdev(pcie
, busdev
);
359 addr
= pcie
->va_cfg0
+ (where
& ~0x3);
361 ls_pcie_cfg1_set_busdev(pcie
, busdev
);
362 addr
= pcie
->va_cfg1
+ (where
& ~0x3);
371 static void ls_pcie_setup_ctrl(struct ls_pcie
*pcie
,
372 struct ls_pcie_info
*info
)
374 struct pci_controller
*hose
= &pcie
->hose
;
375 pci_dev_t dev
= PCI_BDF(hose
->first_busno
, 0, 0);
377 ls_pcie_setup_atu(pcie
, info
);
379 pci_hose_write_config_dword(hose
, dev
, PCI_BASE_ADDRESS_0
, 0);
381 /* program correct class for RC */
382 writel(1, pcie
->dbi
+ PCIE_DBI_RO_WR_EN
);
383 pci_hose_write_config_word(hose
, dev
, PCI_CLASS_DEVICE
,
384 PCI_CLASS_BRIDGE_PCI
);
385 #ifndef CONFIG_LS102XA
386 writel(0, pcie
->dbi
+ PCIE_DBI_RO_WR_EN
);
390 static void ls_pcie_ep_setup_atu(struct ls_pcie
*pcie
,
391 struct ls_pcie_info
*info
)
393 u64 phys
= CONFIG_SYS_PCI_EP_MEMORY_BASE
;
395 /* ATU 0 : INBOUND : map BAR0 */
396 ls_pcie_iatu_inbound_set(pcie
, PCIE_ATU_REGION_INDEX0
, 0, phys
);
397 /* ATU 1 : INBOUND : map BAR1 */
398 phys
+= PCIE_BAR1_SIZE
;
399 ls_pcie_iatu_inbound_set(pcie
, PCIE_ATU_REGION_INDEX1
, 1, phys
);
400 /* ATU 2 : INBOUND : map BAR2 */
401 phys
+= PCIE_BAR2_SIZE
;
402 ls_pcie_iatu_inbound_set(pcie
, PCIE_ATU_REGION_INDEX2
, 2, phys
);
403 /* ATU 3 : INBOUND : map BAR4 */
404 phys
= CONFIG_SYS_PCI_EP_MEMORY_BASE
+ PCIE_BAR4_SIZE
;
405 ls_pcie_iatu_inbound_set(pcie
, PCIE_ATU_REGION_INDEX3
, 4, phys
);
407 /* ATU 0 : OUTBOUND : map 4G MEM */
408 ls_pcie_iatu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX0
,
412 4 * 1024 * 1024 * 1024ULL);
415 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
416 static void ls_pcie_ep_setup_bar(void *bar_base
, int bar
, u32 size
)
423 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_0
);
426 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_1
);
429 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_2
);
430 writel(0, bar_base
+ PCI_BASE_ADDRESS_3
);
433 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_4
);
434 writel(0, bar_base
+ PCI_BASE_ADDRESS_5
);
441 static void ls_pcie_ep_setup_bars(void *bar_base
)
443 /* BAR0 - 32bit - 4K configuration */
444 ls_pcie_ep_setup_bar(bar_base
, 0, PCIE_BAR0_SIZE
);
445 /* BAR1 - 32bit - 8K MSIX*/
446 ls_pcie_ep_setup_bar(bar_base
, 1, PCIE_BAR1_SIZE
);
447 /* BAR2 - 64bit - 4K MEM desciptor */
448 ls_pcie_ep_setup_bar(bar_base
, 2, PCIE_BAR2_SIZE
);
449 /* BAR4 - 64bit - 1M MEM*/
450 ls_pcie_ep_setup_bar(bar_base
, 4, PCIE_BAR4_SIZE
);
453 static void ls_pcie_setup_ep(struct ls_pcie
*pcie
, struct ls_pcie_info
*info
)
455 struct pci_controller
*hose
= &pcie
->hose
;
456 pci_dev_t dev
= PCI_BDF(hose
->first_busno
, 0, 0);
459 sriov
= pci_hose_find_ext_capability(hose
, dev
, PCI_EXT_CAP_ID_SRIOV
);
463 for (pf
= 0; pf
< PCIE_PF_NUM
; pf
++) {
464 for (vf
= 0; vf
<= PCIE_VF_NUM
; vf
++) {
465 #ifndef CONFIG_LS102XA
466 writel(PCIE_LCTRL0_VAL(pf
, vf
),
467 pcie
->dbi
+ PCIE_LUT_BASE
+
470 ls_pcie_ep_setup_bars(pcie
->dbi
);
471 ls_pcie_ep_setup_atu(pcie
, info
);
476 #ifndef CONFIG_LS102XA
477 writel(0, pcie
->dbi
+ PCIE_LUT_BASE
+ PCIE_LUT_LCTRL0
);
480 ls_pcie_ep_setup_bars(pcie
->dbi
+ PCIE_NO_SRIOV_BAR_BASE
);
481 ls_pcie_ep_setup_atu(pcie
, info
);
485 int ls_pcie_init_ctrl(int busno
, enum srds_prtcl dev
, struct ls_pcie_info
*info
)
487 struct ls_pcie
*pcie
;
488 struct pci_controller
*hose
;
489 int num
= dev
- PCIE1
;
490 pci_dev_t pdev
= PCI_BDF(busno
, 0, 0);
491 int i
, linkup
, ep_mode
;
495 if (!is_serdes_configured(dev
)) {
496 printf("PCIe%d: disabled\n", num
+ 1);
500 pcie
= malloc(sizeof(*pcie
));
503 memset(pcie
, 0, sizeof(*pcie
));
506 hose
->priv_data
= pcie
;
507 hose
->first_busno
= busno
;
509 pcie
->dbi
= map_physmem(info
->regs
, PCIE_DBI_SIZE
, MAP_NOCACHE
);
510 pcie
->va_cfg0
= map_physmem(info
->cfg0_phys
,
513 pcie
->va_cfg1
= map_physmem(info
->cfg1_phys
,
517 /* outbound memory */
518 pci_set_region(&hose
->regions
[0],
519 (pci_size_t
)info
->mem_bus
,
520 (phys_size_t
)info
->mem_phys
,
521 (pci_size_t
)info
->mem_size
,
525 pci_set_region(&hose
->regions
[1],
526 (pci_size_t
)info
->io_bus
,
527 (phys_size_t
)info
->io_phys
,
528 (pci_size_t
)info
->io_size
,
531 /* System memory space */
532 pci_set_region(&hose
->regions
[2],
533 CONFIG_SYS_PCI_MEMORY_BUS
,
534 CONFIG_SYS_PCI_MEMORY_PHYS
,
535 CONFIG_SYS_PCI_MEMORY_SIZE
,
536 PCI_REGION_SYS_MEMORY
);
538 hose
->region_count
= 3;
540 for (i
= 0; i
< hose
->region_count
; i
++)
541 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
543 (u64
)hose
->regions
[i
].phys_start
,
544 (u64
)hose
->regions
[i
].bus_start
,
545 (u64
)hose
->regions
[i
].size
,
546 hose
->regions
[i
].flags
);
549 pci_hose_read_config_byte_via_dword
,
550 pci_hose_read_config_word_via_dword
,
552 pci_hose_write_config_byte_via_dword
,
553 pci_hose_write_config_word_via_dword
,
554 ls_pcie_write_config
);
556 pci_hose_read_config_byte(hose
, pdev
, PCI_HEADER_TYPE
, &header_type
);
557 ep_mode
= (header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
;
558 printf("PCIe%u: %s ", info
->pci_num
,
559 ep_mode
? "Endpoint" : "Root Complex");
562 ls_pcie_setup_ep(pcie
, info
);
564 ls_pcie_setup_ctrl(pcie
, info
);
566 linkup
= ls_pcie_link_up(pcie
);
569 /* Let the user know there's no PCIe link */
570 printf("no link, regs @ 0x%lx\n", info
->regs
);
571 hose
->last_busno
= hose
->first_busno
;
575 /* Print the negotiated PCIe link width */
576 pci_hose_read_config_word(hose
, pdev
, PCIE_LINK_STA
, &temp16
);
577 printf("x%d gen%d, regs @ 0x%lx\n", (temp16
& 0x3f0) >> 4,
578 (temp16
& 0xf), info
->regs
);
583 pci_register_hose(hose
);
585 hose
->last_busno
= pci_hose_scan(hose
);
587 printf("PCIe%x: Bus %02x - %02x\n",
588 info
->pci_num
, hose
->first_busno
, hose
->last_busno
);
590 return hose
->last_busno
+ 1;
593 int ls_pcie_init_board(int busno
)
595 struct ls_pcie_info info
;
598 SET_LS_PCIE_INFO(info
, 1);
599 busno
= ls_pcie_init_ctrl(busno
, PCIE1
, &info
);
603 SET_LS_PCIE_INFO(info
, 2);
604 busno
= ls_pcie_init_ctrl(busno
, PCIE2
, &info
);
608 SET_LS_PCIE_INFO(info
, 3);
609 busno
= ls_pcie_init_ctrl(busno
, PCIE3
, &info
);
613 SET_LS_PCIE_INFO(info
, 4);
614 busno
= ls_pcie_init_ctrl(busno
, PCIE4
, &info
);
620 void pci_init_board(void)
622 ls_pcie_init_board(0);
625 #ifdef CONFIG_OF_BOARD_SETUP
627 #include <fdt_support.h>
629 static void ft_pcie_ls_setup(void *blob
, const char *pci_compat
,
630 unsigned long ctrl_addr
, enum srds_prtcl dev
)
634 off
= fdt_node_offset_by_compat_reg(blob
, pci_compat
,
635 (phys_addr_t
)ctrl_addr
);
639 if (!is_serdes_configured(dev
))
640 fdt_set_node_status(blob
, off
, FDT_STATUS_DISABLED
, 0);
643 void ft_pci_setup(void *blob
, bd_t
*bd
)
646 ft_pcie_ls_setup(blob
, FSL_PCIE_COMPAT
, CONFIG_SYS_PCIE1_ADDR
, PCIE1
);
650 ft_pcie_ls_setup(blob
, FSL_PCIE_COMPAT
, CONFIG_SYS_PCIE2_ADDR
, PCIE2
);
654 ft_pcie_ls_setup(blob
, FSL_PCIE_COMPAT
, CONFIG_SYS_PCIE3_ADDR
, PCIE3
);
658 ft_pcie_ls_setup(blob
, FSL_PCIE_COMPAT
, CONFIG_SYS_PCIE4_ADDR
, PCIE4
);
663 void ft_pci_setup(void *blob
, bd_t
*bd
)
668 #if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
670 void pcie_set_available_streamids(void *blob
, const char *pcie_path
,
671 u32
*stream_ids
, int count
)
676 nodeoffset
= fdt_path_offset(blob
, pcie_path
);
677 if (nodeoffset
< 0) {
678 printf("\n%s: ERROR: unable to update PCIe node\n", __func__
);
682 /* for each stream ID, append to mmu-masters */
683 for (i
= 0; i
< count
; i
++) {
684 fdt_appendprop_u32(blob
, nodeoffset
, "available-stream-ids",
689 #define MAX_STREAM_IDS 4
690 void fdt_fixup_smmu_pcie(void *blob
)
693 u32 stream_ids
[MAX_STREAM_IDS
];
694 u32 ctlr_streamid
= 0x300;
697 /* PEX1 stream ID fixup */
698 count
= FSL_PEX1_STREAM_ID_END
- FSL_PEX1_STREAM_ID_START
+ 1;
699 alloc_stream_ids(FSL_PEX1_STREAM_ID_START
, count
, stream_ids
,
701 pcie_set_available_streamids(blob
, "/pcie@3400000", stream_ids
, count
);
702 append_mmu_masters(blob
, "/iommu@5000000", "/pcie@3400000",
707 /* PEX2 stream ID fixup */
708 count
= FSL_PEX2_STREAM_ID_END
- FSL_PEX2_STREAM_ID_START
+ 1;
709 alloc_stream_ids(FSL_PEX2_STREAM_ID_START
, count
, stream_ids
,
711 pcie_set_available_streamids(blob
, "/pcie@3500000", stream_ids
, count
);
712 append_mmu_masters(blob
, "/iommu@5000000", "/pcie@3500000",
717 /* PEX3 stream ID fixup */
718 count
= FSL_PEX3_STREAM_ID_END
- FSL_PEX3_STREAM_ID_START
+ 1;
719 alloc_stream_ids(FSL_PEX3_STREAM_ID_START
, count
, stream_ids
,
721 pcie_set_available_streamids(blob
, "/pcie@3600000", stream_ids
, count
);
722 append_mmu_masters(blob
, "/iommu@5000000", "/pcie@3600000",
727 /* PEX4 stream ID fixup */
728 count
= FSL_PEX4_STREAM_ID_END
- FSL_PEX4_STREAM_ID_START
+ 1;
729 alloc_stream_ids(FSL_PEX4_STREAM_ID_START
, count
, stream_ids
,
731 pcie_set_available_streamids(blob
, "/pcie@3700000", stream_ids
, count
);
732 append_mmu_masters(blob
, "/iommu@5000000", "/pcie@3700000",