2 * Copyright 2014-2015 Freescale Semiconductor, Inc.
3 * Layerscape PCIe driver
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fsl_serdes.h>
15 #include "pcie_layerscape.h"
17 DECLARE_GLOBAL_DATA_PTR
;
19 LIST_HEAD(ls_pcie_list
);
21 static unsigned int dbi_readl(struct ls_pcie
*pcie
, unsigned int offset
)
23 return in_le32(pcie
->dbi
+ offset
);
26 static void dbi_writel(struct ls_pcie
*pcie
, unsigned int value
,
29 out_le32(pcie
->dbi
+ offset
, value
);
32 static unsigned int ctrl_readl(struct ls_pcie
*pcie
, unsigned int offset
)
35 return in_be32(pcie
->ctrl
+ offset
);
37 return in_le32(pcie
->ctrl
+ offset
);
40 static void ctrl_writel(struct ls_pcie
*pcie
, unsigned int value
,
44 out_be32(pcie
->ctrl
+ offset
, value
);
46 out_le32(pcie
->ctrl
+ offset
, value
);
49 static int ls_pcie_ltssm(struct ls_pcie
*pcie
)
55 if (((svr
>> SVR_VAR_PER_SHIFT
) & SVR_LS102XA_MASK
) == SVR_LS102XA
) {
56 state
= ctrl_readl(pcie
, LS1021_PEXMSCPORTSR(pcie
->idx
));
57 state
= (state
>> LS1021_LTSSM_STATE_SHIFT
) & LTSSM_STATE_MASK
;
59 state
= ctrl_readl(pcie
, PCIE_PF_DBG
) & LTSSM_STATE_MASK
;
65 static int ls_pcie_link_up(struct ls_pcie
*pcie
)
69 ltssm
= ls_pcie_ltssm(pcie
);
70 if (ltssm
< LTSSM_PCIE_L0
)
76 static void ls_pcie_cfg0_set_busdev(struct ls_pcie
*pcie
, u32 busdev
)
78 dbi_writel(pcie
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX0
,
80 dbi_writel(pcie
, busdev
, PCIE_ATU_LOWER_TARGET
);
83 static void ls_pcie_cfg1_set_busdev(struct ls_pcie
*pcie
, u32 busdev
)
85 dbi_writel(pcie
, PCIE_ATU_REGION_OUTBOUND
| PCIE_ATU_REGION_INDEX1
,
87 dbi_writel(pcie
, busdev
, PCIE_ATU_LOWER_TARGET
);
90 static void ls_pcie_atu_outbound_set(struct ls_pcie
*pcie
, int idx
, int type
,
91 u64 phys
, u64 bus_addr
, pci_size_t size
)
93 dbi_writel(pcie
, PCIE_ATU_REGION_OUTBOUND
| idx
, PCIE_ATU_VIEWPORT
);
94 dbi_writel(pcie
, (u32
)phys
, PCIE_ATU_LOWER_BASE
);
95 dbi_writel(pcie
, phys
>> 32, PCIE_ATU_UPPER_BASE
);
96 dbi_writel(pcie
, (u32
)phys
+ size
- 1, PCIE_ATU_LIMIT
);
97 dbi_writel(pcie
, (u32
)bus_addr
, PCIE_ATU_LOWER_TARGET
);
98 dbi_writel(pcie
, bus_addr
>> 32, PCIE_ATU_UPPER_TARGET
);
99 dbi_writel(pcie
, type
, PCIE_ATU_CR1
);
100 dbi_writel(pcie
, PCIE_ATU_ENABLE
, PCIE_ATU_CR2
);
103 /* Use bar match mode and MEM type as default */
104 static void ls_pcie_atu_inbound_set(struct ls_pcie
*pcie
, int idx
,
107 dbi_writel(pcie
, PCIE_ATU_REGION_INBOUND
| idx
, PCIE_ATU_VIEWPORT
);
108 dbi_writel(pcie
, (u32
)phys
, PCIE_ATU_LOWER_TARGET
);
109 dbi_writel(pcie
, phys
>> 32, PCIE_ATU_UPPER_TARGET
);
110 dbi_writel(pcie
, PCIE_ATU_TYPE_MEM
, PCIE_ATU_CR1
);
111 dbi_writel(pcie
, PCIE_ATU_ENABLE
| PCIE_ATU_BAR_MODE_ENABLE
|
112 PCIE_ATU_BAR_NUM(bar
), PCIE_ATU_CR2
);
115 static void ls_pcie_dump_atu(struct ls_pcie
*pcie
)
119 for (i
= 0; i
< PCIE_ATU_REGION_NUM
; i
++) {
120 dbi_writel(pcie
, PCIE_ATU_REGION_OUTBOUND
| i
,
122 debug("iATU%d:\n", i
);
123 debug("\tLOWER PHYS 0x%08x\n",
124 dbi_readl(pcie
, PCIE_ATU_LOWER_BASE
));
125 debug("\tUPPER PHYS 0x%08x\n",
126 dbi_readl(pcie
, PCIE_ATU_UPPER_BASE
));
127 debug("\tLOWER BUS 0x%08x\n",
128 dbi_readl(pcie
, PCIE_ATU_LOWER_TARGET
));
129 debug("\tUPPER BUS 0x%08x\n",
130 dbi_readl(pcie
, PCIE_ATU_UPPER_TARGET
));
131 debug("\tLIMIT 0x%08x\n",
132 readl(pcie
->dbi
+ PCIE_ATU_LIMIT
));
133 debug("\tCR1 0x%08x\n",
134 dbi_readl(pcie
, PCIE_ATU_CR1
));
135 debug("\tCR2 0x%08x\n",
136 dbi_readl(pcie
, PCIE_ATU_CR2
));
140 static void ls_pcie_setup_atu(struct ls_pcie
*pcie
)
142 struct pci_region
*io
, *mem
, *pref
;
143 unsigned long long offset
= 0;
148 if (((svr
>> SVR_VAR_PER_SHIFT
) & SVR_LS102XA_MASK
) == SVR_LS102XA
) {
149 offset
= LS1021_PCIE_SPACE_OFFSET
+
150 LS1021_PCIE_SPACE_SIZE
* pcie
->idx
;
153 /* ATU 0 : OUTBOUND : CFG0 */
154 ls_pcie_atu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX0
,
156 pcie
->cfg_res
.start
+ offset
,
158 fdt_resource_size(&pcie
->cfg_res
) / 2);
159 /* ATU 1 : OUTBOUND : CFG1 */
160 ls_pcie_atu_outbound_set(pcie
, PCIE_ATU_REGION_INDEX1
,
162 pcie
->cfg_res
.start
+ offset
+
163 fdt_resource_size(&pcie
->cfg_res
) / 2,
165 fdt_resource_size(&pcie
->cfg_res
) / 2);
167 pci_get_regions(pcie
->bus
, &io
, &mem
, &pref
);
168 idx
= PCIE_ATU_REGION_INDEX1
+ 1;
171 /* ATU : OUTBOUND : IO */
172 ls_pcie_atu_outbound_set(pcie
, idx
++,
174 io
->phys_start
+ offset
,
179 /* ATU : OUTBOUND : MEM */
180 ls_pcie_atu_outbound_set(pcie
, idx
++,
182 mem
->phys_start
+ offset
,
187 /* ATU : OUTBOUND : pref */
188 ls_pcie_atu_outbound_set(pcie
, idx
++,
190 pref
->phys_start
+ offset
,
194 ls_pcie_dump_atu(pcie
);
197 /* Return 0 if the address is valid, -errno if not valid */
198 static int ls_pcie_addr_valid(struct ls_pcie
*pcie
, pci_dev_t bdf
)
200 struct udevice
*bus
= pcie
->bus
;
205 if (PCI_BUS(bdf
) < bus
->seq
)
208 if ((PCI_BUS(bdf
) > bus
->seq
) && (!ls_pcie_link_up(pcie
)))
211 if (PCI_BUS(bdf
) <= (bus
->seq
+ 1) && (PCI_DEV(bdf
) > 0))
217 void *ls_pcie_conf_address(struct ls_pcie
*pcie
, pci_dev_t bdf
,
220 struct udevice
*bus
= pcie
->bus
;
223 if (PCI_BUS(bdf
) == bus
->seq
)
224 return pcie
->dbi
+ offset
;
226 busdev
= PCIE_ATU_BUS(PCI_BUS(bdf
)) |
227 PCIE_ATU_DEV(PCI_DEV(bdf
)) |
228 PCIE_ATU_FUNC(PCI_FUNC(bdf
));
230 if (PCI_BUS(bdf
) == bus
->seq
+ 1) {
231 ls_pcie_cfg0_set_busdev(pcie
, busdev
);
232 return pcie
->cfg0
+ offset
;
234 ls_pcie_cfg1_set_busdev(pcie
, busdev
);
235 return pcie
->cfg1
+ offset
;
239 static int ls_pcie_read_config(struct udevice
*bus
, pci_dev_t bdf
,
240 uint offset
, ulong
*valuep
,
241 enum pci_size_t size
)
243 struct ls_pcie
*pcie
= dev_get_priv(bus
);
246 if (ls_pcie_addr_valid(pcie
, bdf
)) {
247 *valuep
= pci_get_ff(size
);
251 address
= ls_pcie_conf_address(pcie
, bdf
, offset
);
255 *valuep
= readb(address
);
258 *valuep
= readw(address
);
261 *valuep
= readl(address
);
268 static int ls_pcie_write_config(struct udevice
*bus
, pci_dev_t bdf
,
269 uint offset
, ulong value
,
270 enum pci_size_t size
)
272 struct ls_pcie
*pcie
= dev_get_priv(bus
);
275 if (ls_pcie_addr_valid(pcie
, bdf
))
278 address
= ls_pcie_conf_address(pcie
, bdf
, offset
);
282 writeb(value
, address
);
285 writew(value
, address
);
288 writel(value
, address
);
295 /* Clear multi-function bit */
296 static void ls_pcie_clear_multifunction(struct ls_pcie
*pcie
)
298 writeb(PCI_HEADER_TYPE_BRIDGE
, pcie
->dbi
+ PCI_HEADER_TYPE
);
301 /* Fix class value */
302 static void ls_pcie_fix_class(struct ls_pcie
*pcie
)
304 writew(PCI_CLASS_BRIDGE_PCI
, pcie
->dbi
+ PCI_CLASS_DEVICE
);
307 /* Drop MSG TLP except for Vendor MSG */
308 static void ls_pcie_drop_msg_tlp(struct ls_pcie
*pcie
)
312 val
= dbi_readl(pcie
, PCIE_STRFMR1
);
314 dbi_writel(pcie
, val
, PCIE_STRFMR1
);
317 /* Disable all bars in RC mode */
318 static void ls_pcie_disable_bars(struct ls_pcie
*pcie
)
322 sriov
= in_le32(pcie
->dbi
+ PCIE_SRIOV
);
325 * TODO: For PCIe controller with SRIOV, the method to disable bars
326 * is different and more complex, so will add later.
328 if (PCI_EXT_CAP_ID(sriov
) == PCI_EXT_CAP_ID_SRIOV
)
331 dbi_writel(pcie
, 0, PCIE_CS2_OFFSET
+ PCI_BASE_ADDRESS_0
);
332 dbi_writel(pcie
, 0, PCIE_CS2_OFFSET
+ PCI_BASE_ADDRESS_1
);
333 dbi_writel(pcie
, 0, PCIE_CS2_OFFSET
+ PCI_ROM_ADDRESS1
);
336 static void ls_pcie_setup_ctrl(struct ls_pcie
*pcie
)
338 ls_pcie_setup_atu(pcie
);
340 dbi_writel(pcie
, 1, PCIE_DBI_RO_WR_EN
);
341 ls_pcie_fix_class(pcie
);
342 ls_pcie_clear_multifunction(pcie
);
343 ls_pcie_drop_msg_tlp(pcie
);
344 dbi_writel(pcie
, 0, PCIE_DBI_RO_WR_EN
);
346 ls_pcie_disable_bars(pcie
);
349 static void ls_pcie_ep_setup_atu(struct ls_pcie
*pcie
)
351 u64 phys
= CONFIG_SYS_PCI_EP_MEMORY_BASE
;
353 /* ATU 0 : INBOUND : map BAR0 */
354 ls_pcie_atu_inbound_set(pcie
, 0, 0, phys
);
355 /* ATU 1 : INBOUND : map BAR1 */
356 phys
+= PCIE_BAR1_SIZE
;
357 ls_pcie_atu_inbound_set(pcie
, 1, 1, phys
);
358 /* ATU 2 : INBOUND : map BAR2 */
359 phys
+= PCIE_BAR2_SIZE
;
360 ls_pcie_atu_inbound_set(pcie
, 2, 2, phys
);
361 /* ATU 3 : INBOUND : map BAR4 */
362 phys
= CONFIG_SYS_PCI_EP_MEMORY_BASE
+ PCIE_BAR4_SIZE
;
363 ls_pcie_atu_inbound_set(pcie
, 3, 4, phys
);
365 /* ATU 0 : OUTBOUND : map MEM */
366 ls_pcie_atu_outbound_set(pcie
, 0,
370 CONFIG_SYS_PCI_MEMORY_SIZE
);
373 /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
374 static void ls_pcie_ep_setup_bar(void *bar_base
, int bar
, u32 size
)
376 /* The least inbound window is 4KiB */
382 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_0
);
385 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_1
);
388 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_2
);
389 writel(0, bar_base
+ PCI_BASE_ADDRESS_3
);
392 writel(size
- 1, bar_base
+ PCI_BASE_ADDRESS_4
);
393 writel(0, bar_base
+ PCI_BASE_ADDRESS_5
);
400 static void ls_pcie_ep_setup_bars(void *bar_base
)
402 /* BAR0 - 32bit - 4K configuration */
403 ls_pcie_ep_setup_bar(bar_base
, 0, PCIE_BAR0_SIZE
);
404 /* BAR1 - 32bit - 8K MSIX*/
405 ls_pcie_ep_setup_bar(bar_base
, 1, PCIE_BAR1_SIZE
);
406 /* BAR2 - 64bit - 4K MEM desciptor */
407 ls_pcie_ep_setup_bar(bar_base
, 2, PCIE_BAR2_SIZE
);
408 /* BAR4 - 64bit - 1M MEM*/
409 ls_pcie_ep_setup_bar(bar_base
, 4, PCIE_BAR4_SIZE
);
412 static void ls_pcie_setup_ep(struct ls_pcie
*pcie
)
416 sriov
= readl(pcie
->dbi
+ PCIE_SRIOV
);
417 if (PCI_EXT_CAP_ID(sriov
) == PCI_EXT_CAP_ID_SRIOV
) {
420 for (pf
= 0; pf
< PCIE_PF_NUM
; pf
++) {
421 for (vf
= 0; vf
<= PCIE_VF_NUM
; vf
++) {
422 ctrl_writel(pcie
, PCIE_LCTRL0_VAL(pf
, vf
),
425 ls_pcie_ep_setup_bars(pcie
->dbi
);
426 ls_pcie_ep_setup_atu(pcie
);
430 ctrl_writel(pcie
, 0, PCIE_PF_VF_CTRL
);
432 ls_pcie_ep_setup_bars(pcie
->dbi
+ PCIE_NO_SRIOV_BAR_BASE
);
433 ls_pcie_ep_setup_atu(pcie
);
437 static int ls_pcie_probe(struct udevice
*dev
)
439 struct ls_pcie
*pcie
= dev_get_priv(dev
);
440 const void *fdt
= gd
->fdt_blob
;
441 int node
= dev_of_offset(dev
);
449 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
450 "dbi", &pcie
->dbi_res
);
452 printf("ls-pcie: resource \"dbi\" not found\n");
456 pcie
->idx
= (pcie
->dbi_res
.start
- PCIE_SYS_BASE_ADDR
) / PCIE_CCSR_SIZE
;
458 list_add(&pcie
->list
, &ls_pcie_list
);
460 pcie
->enabled
= is_serdes_configured(PCIE_SRDS_PRTCL(pcie
->idx
));
461 if (!pcie
->enabled
) {
462 printf("PCIe%d: %s disabled\n", pcie
->idx
, dev
->name
);
466 pcie
->dbi
= map_physmem(pcie
->dbi_res
.start
,
467 fdt_resource_size(&pcie
->dbi_res
),
470 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
471 "lut", &pcie
->lut_res
);
473 pcie
->lut
= map_physmem(pcie
->lut_res
.start
,
474 fdt_resource_size(&pcie
->lut_res
),
477 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
478 "ctrl", &pcie
->ctrl_res
);
480 pcie
->ctrl
= map_physmem(pcie
->ctrl_res
.start
,
481 fdt_resource_size(&pcie
->ctrl_res
),
484 pcie
->ctrl
= pcie
->lut
;
487 printf("%s: NOT find CTRL\n", dev
->name
);
491 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
492 "config", &pcie
->cfg_res
);
494 printf("%s: resource \"config\" not found\n", dev
->name
);
498 pcie
->cfg0
= map_physmem(pcie
->cfg_res
.start
,
499 fdt_resource_size(&pcie
->cfg_res
),
501 pcie
->cfg1
= pcie
->cfg0
+ fdt_resource_size(&pcie
->cfg_res
) / 2;
503 pcie
->big_endian
= fdtdec_get_bool(fdt
, node
, "big-endian");
505 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n",
506 dev
->name
, (unsigned long)pcie
->dbi
, (unsigned long)pcie
->lut
,
507 (unsigned long)pcie
->ctrl
, (unsigned long)pcie
->cfg0
,
510 header_type
= readb(pcie
->dbi
+ PCI_HEADER_TYPE
);
511 ep_mode
= (header_type
& 0x7f) == PCI_HEADER_TYPE_NORMAL
;
512 printf("PCIe%u: %s %s", pcie
->idx
, dev
->name
,
513 ep_mode
? "Endpoint" : "Root Complex");
516 ls_pcie_setup_ep(pcie
);
518 ls_pcie_setup_ctrl(pcie
);
520 if (!ls_pcie_link_up(pcie
)) {
521 /* Let the user know there's no PCIe link */
522 printf(": no link\n");
526 /* Print the negotiated PCIe link width */
527 link_sta
= readw(pcie
->dbi
+ PCIE_LINK_STA
);
528 printf(": x%d gen%d\n", (link_sta
& PCIE_LINK_WIDTH_MASK
) >> 4,
529 link_sta
& PCIE_LINK_SPEED_MASK
);
534 static const struct dm_pci_ops ls_pcie_ops
= {
535 .read_config
= ls_pcie_read_config
,
536 .write_config
= ls_pcie_write_config
,
539 static const struct udevice_id ls_pcie_ids
[] = {
540 { .compatible
= "fsl,ls-pcie" },
544 U_BOOT_DRIVER(pci_layerscape
) = {
545 .name
= "pci_layerscape",
547 .of_match
= ls_pcie_ids
,
549 .probe
= ls_pcie_probe
,
550 .priv_auto_alloc_size
= sizeof(struct ls_pcie
),