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git.ipfire.org Git - thirdparty/u-boot.git/blob - drivers/pci/pcie_layerscape_fixup.c
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
10 #include <asm/arch/fsl_serdes.h>
13 #ifdef CONFIG_OF_BOARD_SETUP
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
17 #include <asm/arch/clock.h>
19 #include "pcie_layerscape.h"
21 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
23 * Return next available LUT index.
25 static int ls_pcie_next_lut_index(struct ls_pcie
*pcie
)
27 if (pcie
->next_lut_index
< PCIE_LUT_ENTRY_COUNT
)
28 return pcie
->next_lut_index
++;
30 return -ENOSPC
; /* LUT is full */
33 /* returns the next available streamid for pcie, -errno if failed */
34 static int ls_pcie_next_streamid(void)
36 static int next_stream_id
= FSL_PEX_STREAM_ID_START
;
38 if (next_stream_id
> FSL_PEX_STREAM_ID_END
)
41 return next_stream_id
++;
44 static void lut_writel(struct ls_pcie
*pcie
, unsigned int value
,
48 out_be32(pcie
->lut
+ offset
, value
);
50 out_le32(pcie
->lut
+ offset
, value
);
54 * Program a single LUT entry
56 static void ls_pcie_lut_set_mapping(struct ls_pcie
*pcie
, int index
, u32 devid
,
59 /* leave mask as all zeroes, want to match all bits */
60 lut_writel(pcie
, devid
<< 16, PCIE_LUT_UDR(index
));
61 lut_writel(pcie
, streamid
| PCIE_LUT_ENABLE
, PCIE_LUT_LDR(index
));
65 * An msi-map is a property to be added to the pci controller
66 * node. It is a table, where each entry consists of 4 fields
69 * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
70 * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
72 static void fdt_pcie_set_msi_map_entry(void *blob
, struct ls_pcie
*pcie
,
73 u32 devid
, u32 streamid
)
81 /* find pci controller node */
82 nodeoffset
= fdt_node_offset_by_compat_reg(blob
, "fsl,ls-pcie",
85 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
86 svr
= (get_svr() >> SVR_VAR_PER_SHIFT
) & 0xFFFFFE;
87 if (svr
== SVR_LS2088A
|| svr
== SVR_LS2084A
||
88 svr
== SVR_LS2048A
|| svr
== SVR_LS2044A
||
89 svr
== SVR_LS2081A
|| svr
== SVR_LS2041A
)
90 compat
= "fsl,ls2088a-pcie";
92 compat
= CONFIG_FSL_PCIE_COMPAT
;
94 nodeoffset
= fdt_node_offset_by_compat_reg(blob
,
95 compat
, pcie
->dbi_res
.start
);
101 /* get phandle to MSI controller */
102 prop
= (u32
*)fdt_getprop(blob
, nodeoffset
, "msi-parent", 0);
104 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
105 __func__
, pcie
->idx
);
108 phandle
= fdt32_to_cpu(*prop
);
110 /* set one msi-map row */
111 fdt_appendprop_u32(blob
, nodeoffset
, "msi-map", devid
);
112 fdt_appendprop_u32(blob
, nodeoffset
, "msi-map", phandle
);
113 fdt_appendprop_u32(blob
, nodeoffset
, "msi-map", streamid
);
114 fdt_appendprop_u32(blob
, nodeoffset
, "msi-map", 1);
118 * An iommu-map is a property to be added to the pci controller
119 * node. It is a table, where each entry consists of 4 fields
122 * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
123 * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
125 static void fdt_pcie_set_iommu_map_entry(void *blob
, struct ls_pcie
*pcie
,
126 u32 devid
, u32 streamid
)
135 /* find pci controller node */
136 nodeoffset
= fdt_node_offset_by_compat_reg(blob
, "fsl,ls-pcie",
137 pcie
->dbi_res
.start
);
138 if (nodeoffset
< 0) {
139 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
140 svr
= (get_svr() >> SVR_VAR_PER_SHIFT
) & 0xFFFFFE;
141 if (svr
== SVR_LS2088A
|| svr
== SVR_LS2084A
||
142 svr
== SVR_LS2048A
|| svr
== SVR_LS2044A
||
143 svr
== SVR_LS2081A
|| svr
== SVR_LS2041A
)
144 compat
= "fsl,ls2088a-pcie";
146 compat
= CONFIG_FSL_PCIE_COMPAT
;
149 nodeoffset
= fdt_node_offset_by_compat_reg(blob
,
150 compat
, pcie
->dbi_res
.start
);
156 /* get phandle to iommu controller */
157 prop
= fdt_getprop_w(blob
, nodeoffset
, "iommu-map", &lenp
);
159 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
160 __func__
, pcie
->idx
);
164 /* set iommu-map row */
165 iommu_map
[0] = cpu_to_fdt32(devid
);
166 iommu_map
[1] = *++prop
;
167 iommu_map
[2] = cpu_to_fdt32(streamid
);
168 iommu_map
[3] = cpu_to_fdt32(1);
171 fdt_setprop_inplace(blob
, nodeoffset
, "iommu-map",
174 fdt_appendprop(blob
, nodeoffset
, "iommu-map", iommu_map
, 16);
178 static void fdt_fixup_pcie(void *blob
)
180 struct udevice
*dev
, *bus
;
181 struct ls_pcie
*pcie
;
186 /* Scan all known buses */
187 for (pci_find_first_device(&dev
);
189 pci_find_next_device(&dev
)) {
190 for (bus
= dev
; device_is_on_pci_bus(bus
);)
192 pcie
= dev_get_priv(bus
);
194 streamid
= ls_pcie_next_streamid();
196 debug("ERROR: no stream ids free\n");
200 index
= ls_pcie_next_lut_index(pcie
);
202 debug("ERROR: no LUT indexes free\n");
206 /* the DT fixup must be relative to the hose first_busno */
207 bdf
= dm_pci_get_bdf(dev
) - PCI_BDF(bus
->seq
, 0, 0);
208 /* map PCI b.d.f to streamID in LUT */
209 ls_pcie_lut_set_mapping(pcie
, index
, bdf
>> 8,
211 /* update msi-map in device tree */
212 fdt_pcie_set_msi_map_entry(blob
, pcie
, bdf
>> 8,
214 /* update iommu-map in device tree */
215 fdt_pcie_set_iommu_map_entry(blob
, pcie
, bdf
>> 8,
221 static void ft_pcie_ls_setup(void *blob
, struct ls_pcie
*pcie
)
227 off
= fdt_node_offset_by_compat_reg(blob
, "fsl,ls-pcie",
228 pcie
->dbi_res
.start
);
230 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
231 svr
= (get_svr() >> SVR_VAR_PER_SHIFT
) & 0xFFFFFE;
232 if (svr
== SVR_LS2088A
|| svr
== SVR_LS2084A
||
233 svr
== SVR_LS2048A
|| svr
== SVR_LS2044A
||
234 svr
== SVR_LS2081A
|| svr
== SVR_LS2041A
)
235 compat
= "fsl,ls2088a-pcie";
237 compat
= CONFIG_FSL_PCIE_COMPAT
;
239 off
= fdt_node_offset_by_compat_reg(blob
,
240 compat
, pcie
->dbi_res
.start
);
247 fdt_set_node_status(blob
, off
, FDT_STATUS_OKAY
, 0);
249 fdt_set_node_status(blob
, off
, FDT_STATUS_DISABLED
, 0);
252 /* Fixup Kernel DT for PCIe */
253 void ft_pci_setup(void *blob
, bd_t
*bd
)
255 struct ls_pcie
*pcie
;
257 list_for_each_entry(pcie
, &ls_pcie_list
, list
)
258 ft_pcie_ls_setup(blob
, pcie
);
260 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
261 fdt_fixup_pcie(blob
);
265 #else /* !CONFIG_OF_BOARD_SETUP */
266 void ft_pci_setup(void *blob
, bd_t
*bd
)