drivers/pci/pcie_layerscape_fixup.c

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   4  * Layerscape PCIe driver
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <pci.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/io.h>
  13 #include <errno.h>
  14 #ifdef CONFIG_OF_BOARD_SETUP
  15 #include <libfdt.h>
  16 #include <fdt_support.h>
  17 #ifdef CONFIG_ARM
  18 #include <asm/arch/clock.h>
  19 #endif
  20 #include "pcie_layerscape.h"
  21
  22 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  23 /*
  24  * Return next available LUT index.
  25  */
  26 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
  27 {
  28         if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  29                 return pcie->next_lut_index++;
  30         else
  31                 return -ENOSPC;  /* LUT is full */
  32 }
  33
  34 /* returns the next available streamid for pcie, -errno if failed */
  35 static int ls_pcie_next_streamid(void)
  36 {
  37         static int next_stream_id = FSL_PEX_STREAM_ID_START;
  38
  39         if (next_stream_id > FSL_PEX_STREAM_ID_END)
  40                 return -EINVAL;
  41
  42         return next_stream_id++;
  43 }
  44
  45 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
  46                        unsigned int offset)
  47 {
  48         if (pcie->big_endian)
  49                 out_be32(pcie->lut + offset, value);
  50         else
  51                 out_le32(pcie->lut + offset, value);
  52 }
  53
  54 /*
  55  * Program a single LUT entry
  56  */
  57 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
  58                                     u32 streamid)
  59 {
  60         /* leave mask as all zeroes, want to match all bits */
  61         lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  62         lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  63 }
  64
  65 /*
  66  * An msi-map is a property to be added to the pci controller
  67  * node.  It is a table, where each entry consists of 4 fields
  68  * e.g.:
  69  *
  70  *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  71  *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  72  */
  73 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
  74                                        u32 devid, u32 streamid)
  75 {
  76         u32 *prop;
  77         u32 phandle;
  78         int nodeoffset;
  79         uint svr;
  80         char *compat = NULL;
  81
  82         /* find pci controller node */
  83         nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  84                                                    pcie->dbi_res.start);
  85         if (nodeoffset < 0) {
  86 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  87                 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  88                 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  89                     svr == SVR_LS2048A || svr == SVR_LS2044A ||
  90                     svr == SVR_LS2081A || svr == SVR_LS2041A)
  91                         compat = "fsl,ls2088a-pcie";
  92                 else
  93                         compat = CONFIG_FSL_PCIE_COMPAT;
  94                 if (compat)
  95                         nodeoffset = fdt_node_offset_by_compat_reg(blob,
  96                                         compat, pcie->dbi_res.start);
  97 #endif
  98                 if (nodeoffset < 0)
  99                         return;
 100         }
 101
 102         /* get phandle to MSI controller */
 103         prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
 104         if (prop == NULL) {
 105                 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
 106                       __func__, pcie->idx);
 107                 return;
 108         }
 109         phandle = fdt32_to_cpu(*prop);
 110
 111         /* set one msi-map row */
 112         fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
 113         fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
 114         fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
 115         fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
 116 }
 117
 118 /*
 119  * An iommu-map is a property to be added to the pci controller
 120  * node.  It is a table, where each entry consists of 4 fields
 121  * e.g.:
 122  *
 123  *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
 124  *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
 125  */
 126 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
 127                                        u32 devid, u32 streamid)
 128 {
 129         u32 *prop;
 130         u32 iommu_map[4];
 131         int nodeoffset;
 132         int lenp;
 133         uint svr;
 134         char *compat = NULL;
 135
 136         /* find pci controller node */
 137         nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 138                                                    pcie->dbi_res.start);
 139         if (nodeoffset < 0) {
 140 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 141                 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 142                 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 143                     svr == SVR_LS2048A || svr == SVR_LS2044A ||
 144                     svr == SVR_LS2081A || svr == SVR_LS2041A)
 145                         compat = "fsl,ls2088a-pcie";
 146                 else
 147                         compat = CONFIG_FSL_PCIE_COMPAT;
 148
 149                 if (compat)
 150                         nodeoffset = fdt_node_offset_by_compat_reg(blob,
 151                                                 compat, pcie->dbi_res.start);
 152 #endif
 153                 if (nodeoffset < 0)
 154                         return;
 155         }
 156
 157         /* get phandle to iommu controller */
 158         prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
 159         if (prop == NULL) {
 160                 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
 161                       __func__, pcie->idx);
 162                 return;
 163         }
 164
 165         /* set iommu-map row */
 166         iommu_map[0] = cpu_to_fdt32(devid);
 167         iommu_map[1] = *++prop;
 168         iommu_map[2] = cpu_to_fdt32(streamid);
 169         iommu_map[3] = cpu_to_fdt32(1);
 170
 171         if (devid == 0) {
 172                 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
 173                                     iommu_map, 16);
 174         } else {
 175                 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
 176         }
 177 }
 178
 179 static void fdt_fixup_pcie(void *blob)
 180 {
 181         struct udevice *dev, *bus;
 182         struct ls_pcie *pcie;
 183         int streamid;
 184         int index;
 185         pci_dev_t bdf;
 186
 187         /* Scan all known buses */
 188         for (pci_find_first_device(&dev);
 189              dev;
 190              pci_find_next_device(&dev)) {
 191                 for (bus = dev; device_is_on_pci_bus(bus);)
 192                         bus = bus->parent;
 193                 pcie = dev_get_priv(bus);
 194
 195                 streamid = ls_pcie_next_streamid();
 196                 if (streamid < 0) {
 197                         debug("ERROR: no stream ids free\n");
 198                         continue;
 199                 }
 200
 201                 index = ls_pcie_next_lut_index(pcie);
 202                 if (index < 0) {
 203                         debug("ERROR: no LUT indexes free\n");
 204                         continue;
 205                 }
 206
 207                 /* the DT fixup must be relative to the hose first_busno */
 208                 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
 209                 /* map PCI b.d.f to streamID in LUT */
 210                 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
 211                                         streamid);
 212                 /* update msi-map in device tree */
 213                 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 214                                            streamid);
 215                 /* update iommu-map in device tree */
 216                 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
 217                                              streamid);
 218         }
 219 }
 220 #endif
 221
 222 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 223 {
 224         int off;
 225         uint svr;
 226         char *compat = NULL;
 227
 228         off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 229                                             pcie->dbi_res.start);
 230         if (off < 0) {
 231 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 232                 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 233                 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 234                     svr == SVR_LS2048A || svr == SVR_LS2044A ||
 235                     svr == SVR_LS2081A || svr == SVR_LS2041A)
 236                         compat = "fsl,ls2088a-pcie";
 237                 else
 238                         compat = CONFIG_FSL_PCIE_COMPAT;
 239                 if (compat)
 240                         off = fdt_node_offset_by_compat_reg(blob,
 241                                         compat, pcie->dbi_res.start);
 242 #endif
 243                 if (off < 0)
 244                         return;
 245         }
 246
 247         if (pcie->enabled)
 248                 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 249         else
 250                 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 251 }
 252
 253 /* Fixup Kernel DT for PCIe */
 254 void ft_pci_setup(void *blob, bd_t *bd)
 255 {
 256         struct ls_pcie *pcie;
 257
 258         list_for_each_entry(pcie, &ls_pcie_list, list)
 259                 ft_pcie_ls_setup(blob, pcie);
 260
 261 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 262         fdt_fixup_pcie(blob);
 263 #endif
 264 }
 265
 266 #else /* !CONFIG_OF_BOARD_SETUP */
 267 void ft_pci_setup(void *blob, bd_t *bd)
 268 {
 269 }
 270 #endif