drivers/pci/pcie_layerscape_fixup.c

   1 /*
   2  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   3  * Layerscape PCIe driver
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <pci.h>
  10 #include <asm/arch/fsl_serdes.h>
  11 #include <asm/io.h>
  12 #include <errno.h>
  13 #ifdef CONFIG_OF_BOARD_SETUP
  14 #include <libfdt.h>
  15 #include <fdt_support.h>
  16 #include "pcie_layerscape.h"
  17
  18 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  19 /*
  20  * Return next available LUT index.
  21  */
  22 static int ls_pcie_next_lut_index(struct ls_pcie *pcie)
  23 {
  24         if (pcie->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  25                 return pcie->next_lut_index++;
  26         else
  27                 return -ENOSPC;  /* LUT is full */
  28 }
  29
  30 /* returns the next available streamid for pcie, -errno if failed */
  31 static int ls_pcie_next_streamid(void)
  32 {
  33         static int next_stream_id = FSL_PEX_STREAM_ID_START;
  34
  35         if (next_stream_id > FSL_PEX_STREAM_ID_END)
  36                 return -EINVAL;
  37
  38         return next_stream_id++;
  39 }
  40
  41 static void lut_writel(struct ls_pcie *pcie, unsigned int value,
  42                        unsigned int offset)
  43 {
  44         if (pcie->big_endian)
  45                 out_be32(pcie->lut + offset, value);
  46         else
  47                 out_le32(pcie->lut + offset, value);
  48 }
  49
  50 /*
  51  * Program a single LUT entry
  52  */
  53 static void ls_pcie_lut_set_mapping(struct ls_pcie *pcie, int index, u32 devid,
  54                                     u32 streamid)
  55 {
  56         /* leave mask as all zeroes, want to match all bits */
  57         lut_writel(pcie, devid << 16, PCIE_LUT_UDR(index));
  58         lut_writel(pcie, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  59 }
  60
  61 /*
  62  * An msi-map is a property to be added to the pci controller
  63  * node.  It is a table, where each entry consists of 4 fields
  64  * e.g.:
  65  *
  66  *      msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  67  *                 [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  68  */
  69 static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
  70                                        u32 devid, u32 streamid)
  71 {
  72         u32 *prop;
  73         u32 phandle;
  74         int nodeoffset;
  75         uint svr;
  76         char *compat = NULL;
  77
  78         /* find pci controller node */
  79         nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  80                                                    pcie->dbi_res.start);
  81         if (nodeoffset < 0) {
  82 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  83                 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  84                 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  85                     svr == SVR_LS2048A || svr == SVR_LS2044A)
  86                         compat = "fsl,ls2088a-pcie";
  87                 else
  88                         compat = CONFIG_FSL_PCIE_COMPAT;
  89                 if (compat)
  90                         nodeoffset = fdt_node_offset_by_compat_reg(blob,
  91                                         compat, pcie->dbi_res.start);
  92 #endif
  93                 if (nodeoffset < 0)
  94                         return;
  95         }
  96
  97         /* get phandle to MSI controller */
  98         prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
  99         if (prop == NULL) {
 100                 debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
 101                       __func__, pcie->idx);
 102                 return;
 103         }
 104         phandle = fdt32_to_cpu(*prop);
 105
 106         /* set one msi-map row */
 107         fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
 108         fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
 109         fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
 110         fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
 111 }
 112
 113 /*
 114  * An iommu-map is a property to be added to the pci controller
 115  * node.  It is a table, where each entry consists of 4 fields
 116  * e.g.:
 117  *
 118  *      iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
 119  *                 [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
 120  */
 121 static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
 122                                        u32 devid, u32 streamid)
 123 {
 124         u32 *prop;
 125         u32 iommu_map[4];
 126         int nodeoffset;
 127         int lenp;
 128
 129         /* find pci controller node */
 130         nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 131                                                    pcie->dbi_res.start);
 132         if (nodeoffset < 0) {
 133 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 134                 nodeoffset = fdt_node_offset_by_compat_reg(blob,
 135                                 CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
 136                 if (nodeoffset < 0)
 137                         return;
 138 #else
 139                 return;
 140 #endif
 141         }
 142
 143         /* get phandle to iommu controller */
 144         prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
 145         if (prop == NULL) {
 146                 debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
 147                       __func__, pcie->idx);
 148                 return;
 149         }
 150
 151         /* set iommu-map row */
 152         iommu_map[0] = cpu_to_fdt32(devid);
 153         iommu_map[1] = *++prop;
 154         iommu_map[2] = cpu_to_fdt32(streamid);
 155         iommu_map[3] = cpu_to_fdt32(1);
 156
 157         if (devid == 0) {
 158                 fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
 159                                     iommu_map, 16);
 160         } else {
 161                 fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
 162         }
 163 }
 164
 165 static void fdt_fixup_pcie(void *blob)
 166 {
 167         struct udevice *dev, *bus;
 168         struct ls_pcie *pcie;
 169         int streamid;
 170         int index;
 171         pci_dev_t bdf;
 172
 173         /* Scan all known buses */
 174         for (pci_find_first_device(&dev);
 175              dev;
 176              pci_find_next_device(&dev)) {
 177                 for (bus = dev; device_is_on_pci_bus(bus);)
 178                         bus = bus->parent;
 179                 pcie = dev_get_priv(bus);
 180
 181                 streamid = ls_pcie_next_streamid();
 182                 if (streamid < 0) {
 183                         debug("ERROR: no stream ids free\n");
 184                         continue;
 185                 }
 186
 187                 index = ls_pcie_next_lut_index(pcie);
 188                 if (index < 0) {
 189                         debug("ERROR: no LUT indexes free\n");
 190                         continue;
 191                 }
 192
 193                 /* the DT fixup must be relative to the hose first_busno */
 194                 bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
 195                 /* map PCI b.d.f to streamID in LUT */
 196                 ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
 197                                         streamid);
 198                 /* update msi-map in device tree */
 199                 fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 200                                            streamid);
 201                 /* update iommu-map in device tree */
 202                 fdt_pcie_set_iommu_map_entry(blob, pcie, bdf >> 8,
 203                                              streamid);
 204         }
 205 }
 206 #endif
 207
 208 static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 209 {
 210         int off;
 211         uint svr;
 212         char *compat = NULL;
 213
 214         off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 215                                             pcie->dbi_res.start);
 216         if (off < 0) {
 217 #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 218                 svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
 219                 if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
 220                     svr == SVR_LS2048A || svr == SVR_LS2044A)
 221                         compat = "fsl,ls2088a-pcie";
 222                 else
 223                         compat = CONFIG_FSL_PCIE_COMPAT;
 224                 if (compat)
 225                         off = fdt_node_offset_by_compat_reg(blob,
 226                                         compat, pcie->dbi_res.start);
 227 #endif
 228                 if (off < 0)
 229                         return;
 230         }
 231
 232         if (pcie->enabled)
 233                 fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
 234         else
 235                 fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
 236 }
 237
 238 /* Fixup Kernel DT for PCIe */
 239 void ft_pci_setup(void *blob, bd_t *bd)
 240 {
 241         struct ls_pcie *pcie;
 242
 243         list_for_each_entry(pcie, &ls_pcie_list, list)
 244                 ft_pcie_ls_setup(blob, pcie);
 245
 246 #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
 247         fdt_fixup_pcie(blob);
 248 #endif
 249 }
 250
 251 #else /* !CONFIG_OF_BOARD_SETUP */
 252 void ft_pci_setup(void *blob, bd_t *bd)
 253 {
 254 }
 255 #endif