2 * Xilinx AXI Bridge for PCI Express Driver
4 * Copyright (C) 2016 Imagination Technologies
6 * SPDX-License-Identifier: GPL-2.0
16 * struct xilinx_pcie - Xilinx PCIe controller state
17 * @cfg_base: The base address of memory mapped configuration space
23 /* Register definitions */
24 #define XILINX_PCIE_REG_PSCR 0x144
25 #define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
28 * pcie_xilinx_link_up() - Check whether the PCIe link is up
29 * @pcie: Pointer to the PCI controller state
31 * Checks whether the PCIe link for the given device is up or down.
33 * Return: true if the link is up, else false
35 static bool pcie_xilinx_link_up(struct xilinx_pcie
*pcie
)
37 uint32_t pscr
= __raw_readl(pcie
->cfg_base
+ XILINX_PCIE_REG_PSCR
);
39 return pscr
& XILINX_PCIE_REG_PSCR_LNKUP
;
43 * pcie_xilinx_config_address() - Calculate the address of a config access
44 * @udev: Pointer to the PCI bus
45 * @bdf: Identifies the PCIe device to access
46 * @offset: The offset into the device's configuration space
47 * @paddress: Pointer to the pointer to write the calculates address to
49 * Calculates the address that should be accessed to perform a PCIe
50 * configuration space access for a given device identified by the PCIe
51 * controller device @pcie and the bus, device & function numbers in @bdf. If
52 * access to the device is not valid then the function will return an error
53 * code. Otherwise the address to access will be written to the pointer pointed
56 * Return: 0 on success, else -ENODEV
58 static int pcie_xilinx_config_address(struct udevice
*udev
, pci_dev_t bdf
,
59 uint offset
, void **paddress
)
61 struct xilinx_pcie
*pcie
= dev_get_priv(udev
);
62 unsigned int bus
= PCI_BUS(bdf
);
63 unsigned int dev
= PCI_DEV(bdf
);
64 unsigned int func
= PCI_FUNC(bdf
);
67 if ((bus
> 0) && !pcie_xilinx_link_up(pcie
))
71 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are
72 * limited to a single device each.
74 if ((bus
< 2) && (dev
> 0))
77 addr
= pcie
->cfg_base
;
88 * pcie_xilinx_read_config() - Read from configuration space
89 * @bus: Pointer to the PCI bus
90 * @bdf: Identifies the PCIe device to access
91 * @offset: The offset into the device's configuration space
92 * @valuep: A pointer at which to store the read value
93 * @size: Indicates the size of access to perform
95 * Read a value of size @size from offset @offset within the configuration
96 * space of the device identified by the bus, device & function numbers in @bdf
97 * on the PCI bus @bus.
99 * Return: 0 on success, else -ENODEV or -EINVAL
101 static int pcie_xilinx_read_config(struct udevice
*bus
, pci_dev_t bdf
,
102 uint offset
, ulong
*valuep
,
103 enum pci_size_t size
)
105 return pci_generic_mmap_read_config(bus
, pcie_xilinx_config_address
,
106 bdf
, offset
, valuep
, size
);
110 * pcie_xilinx_write_config() - Write to configuration space
111 * @bus: Pointer to the PCI bus
112 * @bdf: Identifies the PCIe device to access
113 * @offset: The offset into the device's configuration space
114 * @value: The value to write
115 * @size: Indicates the size of access to perform
117 * Write the value @value of size @size from offset @offset within the
118 * configuration space of the device identified by the bus, device & function
119 * numbers in @bdf on the PCI bus @bus.
121 * Return: 0 on success, else -ENODEV or -EINVAL
123 static int pcie_xilinx_write_config(struct udevice
*bus
, pci_dev_t bdf
,
124 uint offset
, ulong value
,
125 enum pci_size_t size
)
127 return pci_generic_mmap_write_config(bus
, pcie_xilinx_config_address
,
128 bdf
, offset
, value
, size
);
132 * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
133 * @dev: A pointer to the device being operated on
135 * Translate relevant data from the device tree pertaining to device @dev into
136 * state that the driver will later make use of. This state is stored in the
137 * device's private data structure.
139 * Return: 0 on success, else -EINVAL
141 static int pcie_xilinx_ofdata_to_platdata(struct udevice
*dev
)
143 struct xilinx_pcie
*pcie
= dev_get_priv(dev
);
144 struct fdt_resource reg_res
;
145 DECLARE_GLOBAL_DATA_PTR
;
148 err
= fdt_get_resource(gd
->fdt_blob
, dev_of_offset(dev
), "reg",
151 pr_err("\"reg\" resource not found\n");
155 pcie
->cfg_base
= map_physmem(reg_res
.start
,
156 fdt_resource_size(®_res
),
162 static const struct dm_pci_ops pcie_xilinx_ops
= {
163 .read_config
= pcie_xilinx_read_config
,
164 .write_config
= pcie_xilinx_write_config
,
167 static const struct udevice_id pcie_xilinx_ids
[] = {
168 { .compatible
= "xlnx,axi-pcie-host-1.00.a" },
172 U_BOOT_DRIVER(pcie_xilinx
) = {
173 .name
= "pcie_xilinx",
175 .of_match
= pcie_xilinx_ids
,
176 .ops
= &pcie_xilinx_ops
,
177 .ofdata_to_platdata
= pcie_xilinx_ofdata_to_platdata
,
178 .priv_auto_alloc_size
= sizeof(struct xilinx_pcie
),