drivers/pci_auto.c

   1 /*
   2  * arch/ppc/kernel/pci_auto.c
   3  *
   4  * PCI autoconfiguration library
   5  *
   6  * Author: Matt Porter <mporter@mvista.com>
   7  *
   8  * Copyright 2000 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <common.h>
  17
  18 #ifdef CONFIG_PCI
  19
  20 #include <pci.h>
  21
  22 #undef DEBUG
  23 #ifdef DEBUG
  24 #define DEBUGF(x...) printf(x)
  25 #else
  26 #define DEBUGF(x...)
  27 #endif /* DEBUG */
  28
  29 #define PCIAUTO_IDE_MODE_MASK           0x05
  30
  31 /*
  32  *
  33  */
  34
  35 void pciauto_region_init(struct pci_region* res)
  36 {
  37         res->bus_lower = res->bus_start;
  38 }
  39
  40 void pciauto_region_align(struct pci_region *res, unsigned long size)
  41 {
  42         res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
  43 }
  44
  45 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar)
  46 {
  47         unsigned long addr;
  48
  49         if (!res)
  50         {
  51                 DEBUGF("No resource");
  52                 goto error;
  53         }
  54
  55         addr = ((res->bus_lower - 1) | (size - 1)) + 1;
  56
  57         if (addr - res->bus_start + size > res->size)
  58         {
  59                 DEBUGF("No room in resource");
  60                 goto error;
  61         }
  62
  63         res->bus_lower = addr + size;
  64
  65         DEBUGF("address=0x%lx", addr);
  66
  67         *bar = addr;
  68         return 0;
  69
  70  error:
  71         *bar = 0xffffffff;
  72         return -1;
  73 }
  74
  75 /*
  76  *
  77  */
  78
  79 void pciauto_setup_device(struct pci_controller *hose,
  80                           pci_dev_t dev, int bars_num,
  81                           struct pci_region *mem,
  82                           struct pci_region *io)
  83 {
  84         unsigned int bar_value, bar_response, bar_size;
  85         unsigned int cmdstat = 0;
  86         struct pci_region *bar_res;
  87         int bar, bar_nr = 0;
  88         int found_mem64 = 0;
  89
  90         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
  91         cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
  92
  93         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4)
  94         {
  95                 /* Tickle the BAR and get the response */
  96                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
  97                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
  98
  99                 /* If BAR is not implemented go to the next BAR */
 100                 if (!bar_response)
 101                         continue;
 102
 103                 found_mem64 = 0;
 104
 105                 /* Check the BAR type and set our address mask */
 106                 if (bar_response & PCI_BASE_ADDRESS_SPACE)
 107                 {
 108                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
 109                         bar_res = io;
 110
 111                         DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%x, ", bar_nr, bar_size);
 112                 }
 113                 else
 114                 {
 115                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
 116                              PCI_BASE_ADDRESS_MEM_TYPE_64)
 117                                 found_mem64 = 1;
 118
 119                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
 120                         bar_res = mem;
 121
 122                         DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%x, ", bar_nr, bar_size);
 123                 }
 124
 125                 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0)
 126                 {
 127                         /* Write it out and update our limit */
 128                         pci_hose_write_config_dword(hose, dev, bar, bar_value);
 129
 130                         /*
 131                          * If we are a 64-bit decoder then increment to the
 132                          * upper 32 bits of the bar and force it to locate
 133                          * in the lower 4GB of memory.
 134                          */
 135                         if (found_mem64)
 136                         {
 137                                 bar += 4;
 138                                 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
 139                         }
 140
 141                         cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
 142                                 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
 143                 }
 144
 145                 DEBUGF("\n");
 146
 147                 bar_nr++;
 148         }
 149
 150         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
 151         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
 152         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
 153 }
 154
 155 static void pciauto_prescan_setup_bridge(struct pci_controller *hose,
 156                                          pci_dev_t dev, int sub_bus)
 157 {
 158         struct pci_region *pci_mem = hose->pci_mem;
 159         struct pci_region *pci_io = hose->pci_io;
 160         unsigned int cmdstat;
 161
 162         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
 163
 164         /* Configure bus number registers */
 165         pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS, PCI_BUS(dev));
 166         pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS, sub_bus + 1);
 167         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
 168
 169         if (pci_mem)
 170         {
 171                 /* Round memory allocator to 1MB boundary */
 172                 pciauto_region_align(pci_mem, 0x100000);
 173
 174                 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
 175                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
 176                                         (pci_mem->bus_lower & 0xfff00000) >> 16);
 177
 178                 cmdstat |= PCI_COMMAND_MEMORY;
 179         }
 180
 181         if (pci_io)
 182         {
 183                 /* Round I/O allocator to 4KB boundary */
 184                 pciauto_region_align(pci_io, 0x1000);
 185
 186                 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
 187                                         (pci_io->bus_lower & 0x0000f000) >> 8);
 188                 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
 189                                         (pci_io->bus_lower & 0xffff0000) >> 16);
 190
 191                 cmdstat |= PCI_COMMAND_IO;
 192         }
 193
 194         /* We don't support prefetchable memory for now, so disable */
 195         pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
 196         pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x1000);
 197
 198         /* Enable memory and I/O accesses, enable bus master */
 199         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
 200 }
 201
 202 static void pciauto_postscan_setup_bridge(struct pci_controller *hose,
 203                                           pci_dev_t dev, int sub_bus)
 204 {
 205         struct pci_region *pci_mem = hose->pci_mem;
 206         struct pci_region *pci_io = hose->pci_io;
 207
 208         /* Configure bus number registers */
 209         pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, sub_bus);
 210
 211         if (pci_mem)
 212         {
 213                 /* Round memory allocator to 1MB boundary */
 214                 pciauto_region_align(pci_mem, 0x100000);
 215
 216                 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
 217                                         (pci_mem->bus_lower-1) >> 16);
 218         }
 219
 220         if (pci_io)
 221         {
 222                 /* Round I/O allocator to 4KB boundary */
 223                 pciauto_region_align(pci_io, 0x1000);
 224
 225                 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
 226                                         ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
 227                 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
 228                                         ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
 229         }
 230 }
 231
 232 /*
 233  *
 234  */
 235
 236 void pciauto_config_init(struct pci_controller *hose)
 237 {
 238         int i;
 239
 240         hose->pci_io = hose->pci_mem = NULL;
 241
 242         for (i=0; i<hose->region_count; i++)
 243         {
 244                 switch(hose->regions[i].flags)
 245                 {
 246                 case PCI_REGION_IO:
 247                         if (!hose->pci_io ||
 248                             hose->pci_io->size < hose->regions[i].size)
 249                                 hose->pci_io = hose->regions + i;
 250                         break;
 251                 case PCI_REGION_MEM:
 252                         if (!hose->pci_mem ||
 253                             hose->pci_mem->size < hose->regions[i].size)
 254                                 hose->pci_mem = hose->regions + i;
 255                         break;
 256                 }
 257         }
 258
 259
 260         if (hose->pci_mem)
 261         {
 262                 pciauto_region_init(hose->pci_mem);
 263
 264                 DEBUGF("PCI Autoconfig: Memory region: [%lx-%lx]\n",
 265                     hose->pci_mem->bus_start,
 266                     hose->pci_mem->bus_start + hose->pci_mem->size - 1);
 267         }
 268
 269         if (hose->pci_io)
 270         {
 271                 pciauto_region_init(hose->pci_io);
 272
 273                 DEBUGF("PCI Autoconfig: I/O region: [%lx-%lx]\n",
 274                     hose->pci_io->bus_start,
 275                     hose->pci_io->bus_start + hose->pci_io->size - 1);
 276         }
 277 }
 278
 279 /* HJF: Changed this to return int. I think this is required
 280  * to get the correct result when scanning bridges
 281  */
 282 int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 283 {
 284         unsigned int sub_bus = PCI_BUS(dev);
 285         unsigned short class;
 286         unsigned char prg_iface;
 287
 288         pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
 289
 290         switch(class)
 291         {
 292         case PCI_CLASS_BRIDGE_PCI:
 293                 hose->current_busno++;
 294                 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_io);
 295
 296                 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
 297                 pciauto_prescan_setup_bridge(hose, dev, sub_bus);
 298
 299                 pci_hose_scan_bus(hose, hose->current_busno);
 300
 301                 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
 302                 sub_bus = hose->current_busno;
 303                 break;
 304
 305         case PCI_CLASS_STORAGE_IDE:
 306                 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
 307                 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK))
 308                         {
 309                                 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
 310                                 return sub_bus;
 311                         }
 312
 313                 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
 314                 break;
 315
 316         case PCI_CLASS_BRIDGE_CARDBUS:
 317                 /* just do a minimal setup of the bridge, let the OS take care of the rest */
 318                 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_io);
 319
 320                 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
 321                         PCI_DEV(dev));
 322
 323                 hose->current_busno++;
 324                 break;
 325
 326 #ifdef CONFIG_MPC5200
 327         case PCI_CLASS_BRIDGE_OTHER:
 328                 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
 329                        PCI_DEV(dev));
 330                 break;
 331 #endif
 332
 333         default:
 334                 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);
 335                 break;
 336         }
 337
 338         return sub_bus;
 339 }
 340
 341 #endif /* CONFIG_PCI */