1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
11 #include <generic-phy.h>
16 #include <dm/device_compat.h>
17 #include <linux/bitops.h>
18 #include <power/regulator.h>
20 /* USBPHYC registers */
21 #define STM32_USBPHYC_PLL 0x0
22 #define STM32_USBPHYC_MISC 0x8
24 /* STM32_USBPHYC_PLL bit fields */
25 #define PLLNDIV GENMASK(6, 0)
26 #define PLLNDIV_SHIFT 0
27 #define PLLFRACIN GENMASK(25, 10)
28 #define PLLFRACIN_SHIFT 10
30 #define PLLSTRB BIT(27)
31 #define PLLSTRBYP BIT(28)
32 #define PLLFRACCTL BIT(29)
33 #define PLLDITHEN0 BIT(30)
34 #define PLLDITHEN1 BIT(31)
36 /* STM32_USBPHYC_MISC bit fields */
37 #define SWITHOST BIT(0)
41 /* max 100 us for PLL lock and 100 us for PHY init */
42 #define PLL_INIT_TIME_US 200
43 #define PLL_PWR_DOWN_TIME_US 5
44 #define PLL_FVCO 2880 /* in MHz */
45 #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
46 #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
53 struct stm32_usbphyc
{
56 struct udevice
*vdda1v1
;
57 struct udevice
*vdda1v8
;
58 struct stm32_usbphyc_phy
{
65 static void stm32_usbphyc_get_pll_params(u32 clk_rate
,
66 struct pll_params
*pll_params
)
68 unsigned long long fvco
, ndiv
, frac
;
71 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
73 * | NDIV = integer part of input bits to set the LDF
74 * | FRACT = fractional part of input bits to set the LDF
75 * => PLLNDIV = integer part of (FVCO / (INFF*2))
76 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
77 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
79 fvco
= (unsigned long long)PLL_FVCO
* 1000000; /* In Hz */
82 do_div(ndiv
, (clk_rate
* 2));
83 pll_params
->ndiv
= (u8
)ndiv
;
85 frac
= fvco
* (1 << 16);
86 do_div(frac
, (clk_rate
* 2));
87 frac
= frac
- (ndiv
* (1 << 16));
88 pll_params
->frac
= (u16
)frac
;
91 static int stm32_usbphyc_pll_init(struct stm32_usbphyc
*usbphyc
)
93 struct pll_params pll_params
;
94 u32 clk_rate
= clk_get_rate(&usbphyc
->clk
);
97 if ((clk_rate
< PLL_INFF_MIN_RATE
) || (clk_rate
> PLL_INFF_MAX_RATE
)) {
98 pr_debug("%s: input clk freq (%dHz) out of range\n",
103 stm32_usbphyc_get_pll_params(clk_rate
, &pll_params
);
105 usbphyc_pll
= PLLDITHEN1
| PLLDITHEN0
| PLLSTRBYP
;
106 usbphyc_pll
|= ((pll_params
.ndiv
<< PLLNDIV_SHIFT
) & PLLNDIV
);
108 if (pll_params
.frac
) {
109 usbphyc_pll
|= PLLFRACCTL
;
110 usbphyc_pll
|= ((pll_params
.frac
<< PLLFRACIN_SHIFT
)
114 writel(usbphyc_pll
, usbphyc
->base
+ STM32_USBPHYC_PLL
);
116 pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__
,
117 clk_rate
, pll_params
.ndiv
, pll_params
.frac
);
122 static bool stm32_usbphyc_is_init(struct stm32_usbphyc
*usbphyc
)
126 for (i
= 0; i
< MAX_PHYS
; i
++) {
127 if (usbphyc
->phys
[i
].init
)
134 static bool stm32_usbphyc_is_powered(struct stm32_usbphyc
*usbphyc
)
138 for (i
= 0; i
< MAX_PHYS
; i
++) {
139 if (usbphyc
->phys
[i
].powered
)
146 static int stm32_usbphyc_phy_init(struct phy
*phy
)
148 struct stm32_usbphyc
*usbphyc
= dev_get_priv(phy
->dev
);
149 struct stm32_usbphyc_phy
*usbphyc_phy
= usbphyc
->phys
+ phy
->id
;
150 bool pllen
= readl(usbphyc
->base
+ STM32_USBPHYC_PLL
) & PLLEN
?
154 pr_debug("%s phy ID = %lu\n", __func__
, phy
->id
);
155 /* Check if one phy port has already configured the pll */
156 if (pllen
&& stm32_usbphyc_is_init(usbphyc
))
159 if (usbphyc
->vdda1v1
) {
160 ret
= regulator_set_enable(usbphyc
->vdda1v1
, true);
165 if (usbphyc
->vdda1v8
) {
166 ret
= regulator_set_enable(usbphyc
->vdda1v8
, true);
172 clrbits_le32(usbphyc
->base
+ STM32_USBPHYC_PLL
, PLLEN
);
173 udelay(PLL_PWR_DOWN_TIME_US
);
176 ret
= stm32_usbphyc_pll_init(usbphyc
);
180 setbits_le32(usbphyc
->base
+ STM32_USBPHYC_PLL
, PLLEN
);
182 /* We must wait PLL_INIT_TIME_US before using PHY */
183 udelay(PLL_INIT_TIME_US
);
185 if (!(readl(usbphyc
->base
+ STM32_USBPHYC_PLL
) & PLLEN
))
189 usbphyc_phy
->init
= true;
194 static int stm32_usbphyc_phy_exit(struct phy
*phy
)
196 struct stm32_usbphyc
*usbphyc
= dev_get_priv(phy
->dev
);
197 struct stm32_usbphyc_phy
*usbphyc_phy
= usbphyc
->phys
+ phy
->id
;
200 pr_debug("%s phy ID = %lu\n", __func__
, phy
->id
);
201 usbphyc_phy
->init
= false;
203 /* Check if other phy port requires pllen */
204 if (stm32_usbphyc_is_init(usbphyc
))
207 clrbits_le32(usbphyc
->base
+ STM32_USBPHYC_PLL
, PLLEN
);
210 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
213 udelay(PLL_PWR_DOWN_TIME_US
);
215 if (readl(usbphyc
->base
+ STM32_USBPHYC_PLL
) & PLLEN
)
218 if (usbphyc
->vdda1v1
) {
219 ret
= regulator_set_enable(usbphyc
->vdda1v1
, false);
224 if (usbphyc
->vdda1v8
) {
225 ret
= regulator_set_enable(usbphyc
->vdda1v8
, false);
233 static int stm32_usbphyc_phy_power_on(struct phy
*phy
)
235 struct stm32_usbphyc
*usbphyc
= dev_get_priv(phy
->dev
);
236 struct stm32_usbphyc_phy
*usbphyc_phy
= usbphyc
->phys
+ phy
->id
;
239 pr_debug("%s phy ID = %lu\n", __func__
, phy
->id
);
240 if (usbphyc_phy
->vdd
) {
241 ret
= regulator_set_enable(usbphyc_phy
->vdd
, true);
246 usbphyc_phy
->powered
= true;
251 static int stm32_usbphyc_phy_power_off(struct phy
*phy
)
253 struct stm32_usbphyc
*usbphyc
= dev_get_priv(phy
->dev
);
254 struct stm32_usbphyc_phy
*usbphyc_phy
= usbphyc
->phys
+ phy
->id
;
257 pr_debug("%s phy ID = %lu\n", __func__
, phy
->id
);
258 usbphyc_phy
->powered
= false;
260 if (stm32_usbphyc_is_powered(usbphyc
))
263 if (usbphyc_phy
->vdd
) {
264 ret
= regulator_set_enable(usbphyc_phy
->vdd
, false);
272 static int stm32_usbphyc_get_regulator(struct udevice
*dev
, ofnode node
,
274 struct udevice
**regulator
)
276 struct ofnode_phandle_args regulator_phandle
;
279 ret
= ofnode_parse_phandle_with_args(node
, supply_name
,
283 dev_err(dev
, "Can't find %s property (%d)\n", supply_name
, ret
);
287 ret
= uclass_get_device_by_ofnode(UCLASS_REGULATOR
,
288 regulator_phandle
.node
,
292 dev_err(dev
, "Can't get %s regulator (%d)\n", supply_name
, ret
);
299 static int stm32_usbphyc_of_xlate(struct phy
*phy
,
300 struct ofnode_phandle_args
*args
)
302 if (args
->args_count
< 1)
305 if (args
->args
[0] >= MAX_PHYS
)
308 phy
->id
= args
->args
[0];
310 if ((phy
->id
== 0 && args
->args_count
!= 1) ||
311 (phy
->id
== 1 && args
->args_count
!= 2)) {
312 dev_err(dev
, "invalid number of cells for phy port%ld\n",
320 static const struct phy_ops stm32_usbphyc_phy_ops
= {
321 .init
= stm32_usbphyc_phy_init
,
322 .exit
= stm32_usbphyc_phy_exit
,
323 .power_on
= stm32_usbphyc_phy_power_on
,
324 .power_off
= stm32_usbphyc_phy_power_off
,
325 .of_xlate
= stm32_usbphyc_of_xlate
,
328 static int stm32_usbphyc_probe(struct udevice
*dev
)
330 struct stm32_usbphyc
*usbphyc
= dev_get_priv(dev
);
331 struct reset_ctl reset
;
335 usbphyc
->base
= dev_read_addr(dev
);
336 if (usbphyc
->base
== FDT_ADDR_T_NONE
)
340 ret
= clk_get_by_index(dev
, 0, &usbphyc
->clk
);
344 ret
= clk_enable(&usbphyc
->clk
);
349 ret
= reset_get_by_index(dev
, 0, &reset
);
351 reset_assert(&reset
);
353 reset_deassert(&reset
);
356 /* get usbphyc regulator */
357 ret
= device_get_supply_regulator(dev
, "vdda1v1-supply",
360 dev_err(dev
, "Can't get vdda1v1-supply regulator\n");
364 ret
= device_get_supply_regulator(dev
, "vdda1v8-supply",
367 dev_err(dev
, "Can't get vdda1v8-supply regulator\n");
372 * parse all PHY subnodes in order to populate regulator associated
375 node
= dev_read_first_subnode(dev
);
376 for (i
= 0; i
< MAX_PHYS
; i
++) {
377 struct stm32_usbphyc_phy
*usbphyc_phy
= usbphyc
->phys
+ i
;
379 usbphyc_phy
->init
= false;
380 usbphyc_phy
->powered
= false;
381 ret
= stm32_usbphyc_get_regulator(dev
, node
, "phy-supply",
386 node
= dev_read_next_subnode(node
);
389 /* Check if second port has to be used for host controller */
390 if (dev_read_bool(dev
, "st,port2-switch-to-host"))
391 setbits_le32(usbphyc
->base
+ STM32_USBPHYC_MISC
, SWITHOST
);
396 static const struct udevice_id stm32_usbphyc_of_match
[] = {
397 { .compatible
= "st,stm32mp1-usbphyc", },
401 U_BOOT_DRIVER(stm32_usb_phyc
) = {
402 .name
= "stm32-usbphyc",
404 .of_match
= stm32_usbphyc_of_match
,
405 .ops
= &stm32_usbphyc_phy_ops
,
406 .probe
= stm32_usbphyc_probe
,
407 .priv_auto_alloc_size
= sizeof(struct stm32_usbphyc
),