]> git.ipfire.org Git - thirdparty/linux.git/blob - drivers/phy/qualcomm/phy-qcom-qmp-combo.c
Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
[thirdparty/linux.git] / drivers / phy / qualcomm / phy-qcom-qmp-combo.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 #include <linux/usb/typec.h>
22 #include <linux/usb/typec_mux.h>
23
24 #include <drm/bridge/aux-bridge.h>
25
26 #include <dt-bindings/phy/phy-qcom-qmp.h>
27
28 #include "phy-qcom-qmp-common.h"
29
30 #include "phy-qcom-qmp.h"
31 #include "phy-qcom-qmp-pcs-misc-v3.h"
32 #include "phy-qcom-qmp-pcs-usb-v4.h"
33 #include "phy-qcom-qmp-pcs-usb-v5.h"
34 #include "phy-qcom-qmp-pcs-usb-v6.h"
35
36 #include "phy-qcom-qmp-dp-com-v3.h"
37
38 #include "phy-qcom-qmp-dp-phy.h"
39 #include "phy-qcom-qmp-dp-phy-v3.h"
40 #include "phy-qcom-qmp-dp-phy-v4.h"
41 #include "phy-qcom-qmp-dp-phy-v5.h"
42 #include "phy-qcom-qmp-dp-phy-v6.h"
43
44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
45 /* DP PHY soft reset */
46 #define SW_DPPHY_RESET BIT(0)
47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
48 #define SW_DPPHY_RESET_MUX BIT(1)
49 /* USB3 PHY soft reset */
50 #define SW_USB3PHY_RESET BIT(2)
51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
52 #define SW_USB3PHY_RESET_MUX BIT(3)
53
54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
55 #define USB3_MODE BIT(0) /* enables USB3 mode */
56 #define DP_MODE BIT(1) /* enables DP mode */
57
58 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
59 #define SW_PORTSELECT_VAL BIT(0)
60 #define SW_PORTSELECT_MUX BIT(1)
61
62 #define PHY_INIT_COMPLETE_TIMEOUT 10000
63
64 /* set of registers with offsets different per-PHY */
65 enum qphy_reg_layout {
66 /* PCS registers */
67 QPHY_SW_RESET,
68 QPHY_START_CTRL,
69 QPHY_PCS_STATUS,
70 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
71 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
72 QPHY_PCS_POWER_DOWN_CONTROL,
73
74 QPHY_COM_RESETSM_CNTRL,
75 QPHY_COM_C_READY_STATUS,
76 QPHY_COM_CMN_STATUS,
77 QPHY_COM_BIAS_EN_CLKBUFLR_EN,
78
79 QPHY_DP_PHY_STATUS,
80
81 QPHY_TX_TX_POL_INV,
82 QPHY_TX_TX_DRV_LVL,
83 QPHY_TX_TX_EMP_POST1_LVL,
84 QPHY_TX_HIGHZ_DRVR_EN,
85 QPHY_TX_TRANSCEIVER_BIAS_EN,
86
87 /* Keep last to ensure regs_layout arrays are properly initialized */
88 QPHY_LAYOUT_SIZE
89 };
90
91 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
92 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
93 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
94 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
95 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
96 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
97 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
98
99 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL,
100 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS,
101 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
102 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
103
104 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
105
106 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
107 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
108 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL,
109 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN,
110 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
111 };
112
113 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
114 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
115 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
116 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
118
119 /* In PCS_USB */
120 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
121 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
122
123 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL,
124 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS,
125 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
126 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
127
128 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
129
130 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
131 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
132 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL,
133 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN,
134 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
135 };
136
137 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
138 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
139 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
140 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
141 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
142
143 /* In PCS_USB */
144 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
145 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
146
147 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
148 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
149 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
150 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
151
152 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
153
154 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
155 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
156 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
157 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
158 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
159 };
160
161 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
162 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
163 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
164 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
165 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
166
167 /* In PCS_USB */
168 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
169 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
170
171 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
172 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
173 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
174 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
175
176 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
177
178 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
179 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
180 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL,
181 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN,
182 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
183 };
184
185 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
186 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
187 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
188 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
189 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
190 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
191 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
192 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
193 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
194 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
195 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
196 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
197 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
198 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
199 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
200 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
201 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
202 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
203 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
204 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
205 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
206 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
207 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
208 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
209 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
210 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
211 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
212 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
213 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
214 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
215 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
216 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
217 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
218 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
219 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
220 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
221 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
222 };
223
224 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
225 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
226 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
227 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
228 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
229 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
230 };
231
232 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
254 };
255
256 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
264 };
265
266 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
274 };
275
276 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
284 };
285
286 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
294 };
295
296 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
297 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
298 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
299 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
300 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
301 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
302 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
303 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
304 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
305 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
306 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
307 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
308 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
309 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
310 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
311 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
312 };
313
314 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
315 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
316 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
317 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
318 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
319 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
320 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
321 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
322 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
323 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
324 };
325
326 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
327 /* FLL settings */
328 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
329 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
330 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
331 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
332 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
333
334 /* Lock Det settings */
335 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
336 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
337 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
338 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
339
340 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
341 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
342 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
343 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
344 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
345 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
346 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
359
360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
371 };
372
373 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
374 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
375 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
376 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
377 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
378 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
380 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
384 };
385
386 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
387 /* FLL settings */
388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
393
394 /* Lock Det settings */
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
399
400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
419
420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
432
433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
435 };
436
437 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
438 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
439 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
440 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
441 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
442 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
443 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
444 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
445 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
446 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
447 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
448 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
449 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
450 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
451 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
452 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
453 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
454 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
455 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
456 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
457 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
458 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
459 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
460 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
461 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
478 };
479
480 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
481 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
482 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
483 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
484 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
485 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
486 };
487
488 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
489 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
490 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
491 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
492 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
493 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
494 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
495 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
496 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
497 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
498 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
499 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
500 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
501 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
502 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
503 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
504 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
505 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
525 };
526
527 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
528 /* Lock Det settings */
529 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
530 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
531 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
532
533 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
534 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
535 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
536 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
537 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
538 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
539 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
540 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
541 };
542
543 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
544 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
545 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
546 };
547
548 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
549 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
550 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
551 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
552 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
553 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
554 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
555 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
556 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
557 };
558
559 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
565 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
566 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
567 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
568 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
569 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
570 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
571 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
572 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
573 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
574 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
575 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
576 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
577 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
578 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
579 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
580 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
581 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
582 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
583 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
598 };
599
600 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
601 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
602 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
603 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
604 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
605 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
606 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
607 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
608 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
609 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
610 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
611 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
612 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
613 };
614
615 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
616 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
617 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
618 };
619
620 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
621 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
622 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
623 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
624 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
625 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
626 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
627 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
628 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
629 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
630 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
631 };
632
633 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
634 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
635 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
636 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
637 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
638 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
639 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
640 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
641 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
642 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
643 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
644 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
645 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
646 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
647 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
658 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
659 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
664 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
672 };
673
674 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
675 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
676 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
677 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
678 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
679 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
689 };
690
691 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
692 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
693 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
694 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
695 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
696 };
697
698 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
699 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
700 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
701 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
702 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
723 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
724 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
725 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
726 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
738 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
747 };
748
749 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
750 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
751 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
752 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
753 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
754 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
755 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
756 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
757 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
758 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
759 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
760 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
761 };
762
763 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
764 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
765 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
766 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
767 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
768 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
769 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
770 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
771 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
772 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
773 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
774 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
775 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
776 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
777 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
778 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
779 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
780 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
781 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
782 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
783 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
784 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
785 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
786 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
787 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
788 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
789 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
790 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
791 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
792 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
793 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
794 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
795 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
796 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
797 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
798
799 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
800 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
801 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
802 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
803 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
804
805 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
806 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
807 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
808 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
809 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
810 };
811
812 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
813 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
814 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
815 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
816 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
817 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
818 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),
819 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
820 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
821 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
822 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
823 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
824 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
825 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
826 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
827 };
828
829 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
830 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
831 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
832 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
833 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
834 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
835 };
836
837 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
848 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
849 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
850 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
851 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
852 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
853 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
854 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
855 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
856 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
857 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
858 };
859
860 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
861 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
862 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
863 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
864 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
865 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
866 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
867 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
868 };
869
870 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
871 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
872 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
873 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
874 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
875 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
876 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
877 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
878 };
879
880 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
888 };
889
890 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
895 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
898 };
899
900 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
901 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
902 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
903 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
904 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
905 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
906 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
910 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
911 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
912 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
913 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
914 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
915 };
916
917 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
918 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
919 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
920 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
928 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
929 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
930 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
938 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
939 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
940 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
941 };
942
943 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
944 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
945 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
946 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
947 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
948 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
949 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
950 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
951 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
952 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
953 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
954 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
955 };
956
957 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
958 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
959 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
960 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
961 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
962 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
963 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
964 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
965 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
966 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
967 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
968 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
969 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
970 };
971
972 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
988 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
989 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
990 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
991 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
992 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
993 };
994
995 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
996 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
997 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
998 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
999 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
1000 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
1001 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
1002 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1003 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
1004 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
1005 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1006 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
1007 };
1008
1009 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
1010 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1011 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1012 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1019 };
1020
1021 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1031 };
1032
1033 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
1034 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1035 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1036 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
1037 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1038 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1039 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1040 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1041 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1042 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1043 };
1044
1045 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
1046 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1047 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1048 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1049 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1055 };
1056
1057 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1069 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1070 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1071 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1072 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1073 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1074 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1075 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1076 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1084 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1085 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1086 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1087 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1088 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1089 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1090 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1091 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1092 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1093 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1094 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1095 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1096 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1097 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1105 };
1106
1107 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1108 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1109 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1110 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1111 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1112 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1113 };
1114
1115 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1116 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1117 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1118 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1119 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1120 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1121 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1122 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1123 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1124 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1125 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1126 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1127 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1128 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1129 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1130 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1131 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1132 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1133 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1134 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1135 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1136 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1137 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1138 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1139 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1140 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1141 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1142 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1143 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1144 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1145 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1146 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1147 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1148 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1149 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1150 };
1151
1152 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1153 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1154 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1155 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1156 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1157 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1158 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1159 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1160 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1161 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1162 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1163 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1164 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1165 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1166 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1167 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1168 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1169 };
1170
1171 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = {
1172 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1173 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1174 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1175 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2),
1176 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03),
1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2),
1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1183 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1184 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1185 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
1195 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
1196 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
1197 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55),
1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03),
1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03),
1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba),
1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00),
1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba),
1207 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00),
1208 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13),
1209 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76),
1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f),
1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01),
1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a),
1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1222 };
1223
1224 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = {
1225 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05),
1226 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50),
1227 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50),
1228 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1229 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1230 };
1231
1232 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
1233 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04),
1234 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1235 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00),
1236 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3),
1237 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3),
1238 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8),
1239 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e),
1240 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36),
1241 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6),
1242 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64),
1243 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6),
1244 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee),
1245 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18),
1246 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a),
1247 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04),
1248 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36),
1249 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3),
1250 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1251 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80),
1252 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f),
1253 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08),
1254 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15),
1255 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0),
1256 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48),
1257 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1258 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1259 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00),
1260 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04),
1261 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88),
1262 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45),
1263 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d),
1264 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09),
1265 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05),
1266 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f),
1267 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14),
1268 };
1269
1270 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1271 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1272 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1273 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1274 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
1275 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
1276 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
1277 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
1278 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x55),
1279 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
1280 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1281 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1282 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
1283 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
1284 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
1285 };
1286
1287 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1288 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1289 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1290 };
1291
1292 /* list of regulators */
1293 struct qmp_regulator_data {
1294 const char *name;
1295 unsigned int enable_load;
1296 };
1297
1298 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1299 { .name = "vdda-phy", .enable_load = 21800 },
1300 { .name = "vdda-pll", .enable_load = 36000 },
1301 };
1302
1303 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1304 { 0x00, 0x0c, 0x15, 0x1a },
1305 { 0x02, 0x0e, 0x16, 0xff },
1306 { 0x02, 0x11, 0xff, 0xff },
1307 { 0x04, 0xff, 0xff, 0xff }
1308 };
1309
1310 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1311 { 0x02, 0x12, 0x16, 0x1a },
1312 { 0x09, 0x19, 0x1f, 0xff },
1313 { 0x10, 0x1f, 0xff, 0xff },
1314 { 0x1f, 0xff, 0xff, 0xff }
1315 };
1316
1317 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1318 { 0x00, 0x0c, 0x14, 0x19 },
1319 { 0x00, 0x0b, 0x12, 0xff },
1320 { 0x00, 0x0b, 0xff, 0xff },
1321 { 0x04, 0xff, 0xff, 0xff }
1322 };
1323
1324 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1325 { 0x08, 0x0f, 0x16, 0x1f },
1326 { 0x11, 0x1e, 0x1f, 0xff },
1327 { 0x19, 0x1f, 0xff, 0xff },
1328 { 0x1f, 0xff, 0xff, 0xff }
1329 };
1330
1331 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1332 { 0x00, 0x0c, 0x15, 0x1b },
1333 { 0x02, 0x0e, 0x16, 0xff },
1334 { 0x02, 0x11, 0xff, 0xff },
1335 { 0x04, 0xff, 0xff, 0xff }
1336 };
1337
1338 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1339 { 0x00, 0x0d, 0x14, 0x1a },
1340 { 0x00, 0x0e, 0x15, 0xff },
1341 { 0x00, 0x0d, 0xff, 0xff },
1342 { 0x03, 0xff, 0xff, 0xff }
1343 };
1344
1345 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1346 { 0x08, 0x0f, 0x16, 0x1f },
1347 { 0x11, 0x1e, 0x1f, 0xff },
1348 { 0x16, 0x1f, 0xff, 0xff },
1349 { 0x1f, 0xff, 0xff, 0xff }
1350 };
1351
1352 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1353 { 0x20, 0x2c, 0x35, 0x3b },
1354 { 0x22, 0x2e, 0x36, 0xff },
1355 { 0x22, 0x31, 0xff, 0xff },
1356 { 0x24, 0xff, 0xff, 0xff }
1357 };
1358
1359 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1360 { 0x22, 0x32, 0x36, 0x3a },
1361 { 0x29, 0x39, 0x3f, 0xff },
1362 { 0x30, 0x3f, 0xff, 0xff },
1363 { 0x3f, 0xff, 0xff, 0xff }
1364 };
1365
1366 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1367 { 0x20, 0x2d, 0x34, 0x3a },
1368 { 0x20, 0x2e, 0x35, 0xff },
1369 { 0x20, 0x2e, 0xff, 0xff },
1370 { 0x24, 0xff, 0xff, 0xff }
1371 };
1372
1373 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1374 { 0x28, 0x2f, 0x36, 0x3f },
1375 { 0x31, 0x3e, 0x3f, 0xff },
1376 { 0x36, 0x3f, 0xff, 0xff },
1377 { 0x3f, 0xff, 0xff, 0xff }
1378 };
1379
1380 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1381 { 0x20, 0x2d, 0x34, 0x3a },
1382 { 0x20, 0x2e, 0x35, 0xff },
1383 { 0x20, 0x2e, 0xff, 0xff },
1384 { 0x22, 0xff, 0xff, 0xff }
1385 };
1386
1387 struct qmp_combo;
1388
1389 struct qmp_combo_offsets {
1390 u16 com;
1391 u16 txa;
1392 u16 rxa;
1393 u16 txb;
1394 u16 rxb;
1395 u16 usb3_serdes;
1396 u16 usb3_pcs_misc;
1397 u16 usb3_pcs;
1398 u16 usb3_pcs_usb;
1399 u16 dp_serdes;
1400 u16 dp_txa;
1401 u16 dp_txb;
1402 u16 dp_dp_phy;
1403 };
1404
1405 struct qmp_phy_cfg {
1406 const struct qmp_combo_offsets *offsets;
1407
1408 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1409 const struct qmp_phy_init_tbl *serdes_tbl;
1410 int serdes_tbl_num;
1411 const struct qmp_phy_init_tbl *tx_tbl;
1412 int tx_tbl_num;
1413 const struct qmp_phy_init_tbl *rx_tbl;
1414 int rx_tbl_num;
1415 const struct qmp_phy_init_tbl *pcs_tbl;
1416 int pcs_tbl_num;
1417 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1418 int pcs_usb_tbl_num;
1419
1420 const struct qmp_phy_init_tbl *dp_serdes_tbl;
1421 int dp_serdes_tbl_num;
1422 const struct qmp_phy_init_tbl *dp_tx_tbl;
1423 int dp_tx_tbl_num;
1424
1425 /* Init sequence for DP PHY block link rates */
1426 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1427 int serdes_tbl_rbr_num;
1428 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1429 int serdes_tbl_hbr_num;
1430 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1431 int serdes_tbl_hbr2_num;
1432 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1433 int serdes_tbl_hbr3_num;
1434
1435 /* DP PHY swing and pre_emphasis tables */
1436 const u8 (*swing_hbr_rbr)[4][4];
1437 const u8 (*swing_hbr3_hbr2)[4][4];
1438 const u8 (*pre_emphasis_hbr_rbr)[4][4];
1439 const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1440
1441 /* DP PHY callbacks */
1442 int (*configure_dp_phy)(struct qmp_combo *qmp);
1443 void (*configure_dp_tx)(struct qmp_combo *qmp);
1444 int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1445 void (*dp_aux_init)(struct qmp_combo *qmp);
1446
1447 /* resets to be requested */
1448 const char * const *reset_list;
1449 int num_resets;
1450 /* regulators to be requested */
1451 const struct qmp_regulator_data *vreg_list;
1452 int num_vregs;
1453
1454 /* array of registers with different offsets */
1455 const unsigned int *regs;
1456
1457 /* true, if PHY needs delay after POWER_DOWN */
1458 bool has_pwrdn_delay;
1459
1460 /* Offset from PCS to PCS_USB region */
1461 unsigned int pcs_usb_offset;
1462
1463 };
1464
1465 struct qmp_combo {
1466 struct device *dev;
1467
1468 const struct qmp_phy_cfg *cfg;
1469
1470 void __iomem *com;
1471
1472 void __iomem *serdes;
1473 void __iomem *tx;
1474 void __iomem *rx;
1475 void __iomem *pcs;
1476 void __iomem *tx2;
1477 void __iomem *rx2;
1478 void __iomem *pcs_misc;
1479 void __iomem *pcs_usb;
1480
1481 void __iomem *dp_serdes;
1482 void __iomem *dp_tx;
1483 void __iomem *dp_tx2;
1484 void __iomem *dp_dp_phy;
1485
1486 struct clk *pipe_clk;
1487 struct clk_bulk_data *clks;
1488 int num_clks;
1489 struct reset_control_bulk_data *resets;
1490 struct regulator_bulk_data *vregs;
1491
1492 struct mutex phy_mutex;
1493 int init_count;
1494
1495 struct phy *usb_phy;
1496 enum phy_mode mode;
1497 unsigned int usb_init_count;
1498
1499 struct phy *dp_phy;
1500 unsigned int dp_aux_cfg;
1501 struct phy_configure_opts_dp dp_opts;
1502 unsigned int dp_init_count;
1503
1504 struct clk_fixed_rate pipe_clk_fixed;
1505 struct clk_hw dp_link_hw;
1506 struct clk_hw dp_pixel_hw;
1507
1508 struct typec_switch_dev *sw;
1509 enum typec_orientation orientation;
1510 };
1511
1512 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1513 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1514 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1515 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1516
1517 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1518 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1519 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1520 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1521
1522 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1523 {
1524 u32 reg;
1525
1526 reg = readl(base + offset);
1527 reg |= val;
1528 writel(reg, base + offset);
1529
1530 /* ensure that above write is through */
1531 readl(base + offset);
1532 }
1533
1534 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1535 {
1536 u32 reg;
1537
1538 reg = readl(base + offset);
1539 reg &= ~val;
1540 writel(reg, base + offset);
1541
1542 /* ensure that above write is through */
1543 readl(base + offset);
1544 }
1545
1546 /* list of clocks required by phy */
1547 static const char * const qmp_combo_phy_clk_l[] = {
1548 "aux", "cfg_ahb", "ref", "com_aux",
1549 };
1550
1551 /* list of resets */
1552 static const char * const msm8996_usb3phy_reset_l[] = {
1553 "phy", "common",
1554 };
1555
1556 static const char * const sc7180_usb3phy_reset_l[] = {
1557 "phy",
1558 };
1559
1560 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1561 .com = 0x0000,
1562 .txa = 0x1200,
1563 .rxa = 0x1400,
1564 .txb = 0x1600,
1565 .rxb = 0x1800,
1566 .usb3_serdes = 0x1000,
1567 .usb3_pcs_misc = 0x1a00,
1568 .usb3_pcs = 0x1c00,
1569 .usb3_pcs_usb = 0x1f00,
1570 .dp_serdes = 0x2000,
1571 .dp_txa = 0x2200,
1572 .dp_txb = 0x2600,
1573 .dp_dp_phy = 0x2a00,
1574 };
1575
1576 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1577 .com = 0x0000,
1578 .txa = 0x0400,
1579 .rxa = 0x0600,
1580 .txb = 0x0a00,
1581 .rxb = 0x0c00,
1582 .usb3_serdes = 0x1000,
1583 .usb3_pcs_misc = 0x1200,
1584 .usb3_pcs = 0x1400,
1585 .usb3_pcs_usb = 0x1700,
1586 .dp_serdes = 0x2000,
1587 .dp_dp_phy = 0x2200,
1588 };
1589
1590 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
1591 .offsets = &qmp_combo_offsets_v3,
1592
1593 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1594 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1595 .tx_tbl = qmp_v3_usb3_tx_tbl,
1596 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1597 .rx_tbl = qmp_v3_usb3_rx_tbl,
1598 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1599 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1600 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1601
1602 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1603 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1604 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1605 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1606
1607 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1608 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1609 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1610 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1611 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1612 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1613 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1614 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1615
1616 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1617 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1618 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1619 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1620
1621 .dp_aux_init = qmp_v3_dp_aux_init,
1622 .configure_dp_tx = qmp_v3_configure_dp_tx,
1623 .configure_dp_phy = qmp_v3_configure_dp_phy,
1624 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1625
1626 .reset_list = sc7180_usb3phy_reset_l,
1627 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1628 .vreg_list = qmp_phy_vreg_l,
1629 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1630 .regs = qmp_v3_usb3phy_regs_layout,
1631
1632 .has_pwrdn_delay = true,
1633 };
1634
1635 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
1636 .offsets = &qmp_combo_offsets_v3,
1637
1638 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1639 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1640 .tx_tbl = qmp_v3_usb3_tx_tbl,
1641 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1642 .rx_tbl = qmp_v3_usb3_rx_tbl,
1643 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1644 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
1645 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1646
1647 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1648 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1649 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1650 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1651
1652 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1653 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1654 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1655 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1656 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1657 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1658 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1659 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1660
1661 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1662 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1663 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1664 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1665
1666 .dp_aux_init = qmp_v3_dp_aux_init,
1667 .configure_dp_tx = qmp_v3_configure_dp_tx,
1668 .configure_dp_phy = qmp_v3_configure_dp_phy,
1669 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1670
1671 .reset_list = msm8996_usb3phy_reset_l,
1672 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1673 .vreg_list = qmp_phy_vreg_l,
1674 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1675 .regs = qmp_v3_usb3phy_regs_layout,
1676
1677 .has_pwrdn_delay = true,
1678 };
1679
1680 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
1681 .offsets = &qmp_combo_offsets_v3,
1682
1683 .serdes_tbl = sm8150_usb3_serdes_tbl,
1684 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1685 .tx_tbl = sm8150_usb3_tx_tbl,
1686 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1687 .rx_tbl = sm8150_usb3_rx_tbl,
1688 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1689 .pcs_tbl = sm8150_usb3_pcs_tbl,
1690 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1691 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
1692 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1693
1694 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1695 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1696 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
1697 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1698
1699 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1700 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1701 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1702 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1703 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1704 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1705 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1706 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1707
1708 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1709 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1710 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1711 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1712
1713 .dp_aux_init = qmp_v4_dp_aux_init,
1714 .configure_dp_tx = qmp_v4_configure_dp_tx,
1715 .configure_dp_phy = qmp_v4_configure_dp_phy,
1716 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1717
1718 .reset_list = msm8996_usb3phy_reset_l,
1719 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1720 .vreg_list = qmp_phy_vreg_l,
1721 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1722 .regs = qmp_v45_usb3phy_regs_layout,
1723 .pcs_usb_offset = 0x300,
1724
1725 .has_pwrdn_delay = true,
1726 };
1727
1728 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
1729 .offsets = &qmp_combo_offsets_v5,
1730
1731 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl,
1732 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
1733 .tx_tbl = sc8280xp_usb43dp_tx_tbl,
1734 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
1735 .rx_tbl = sc8280xp_usb43dp_rx_tbl,
1736 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
1737 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl,
1738 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
1739
1740 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl,
1741 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
1742 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl,
1743 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
1744
1745 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1746 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1747 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1748 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1749 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1750 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1751 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1752 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1753
1754 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1755 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1756 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1757 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1758
1759 .dp_aux_init = qmp_v4_dp_aux_init,
1760 .configure_dp_tx = qmp_v4_configure_dp_tx,
1761 .configure_dp_phy = qmp_v4_configure_dp_phy,
1762 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1763
1764 .reset_list = msm8996_usb3phy_reset_l,
1765 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1766 .vreg_list = qmp_phy_vreg_l,
1767 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1768 .regs = qmp_v5_5nm_usb3phy_regs_layout,
1769 };
1770
1771 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
1772 .offsets = &qmp_combo_offsets_v5,
1773
1774 .serdes_tbl = x1e80100_usb43dp_serdes_tbl,
1775 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl),
1776 .tx_tbl = x1e80100_usb43dp_tx_tbl,
1777 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl),
1778 .rx_tbl = x1e80100_usb43dp_rx_tbl,
1779 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl),
1780 .pcs_tbl = x1e80100_usb43dp_pcs_tbl,
1781 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl),
1782 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl,
1783 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
1784
1785 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1786 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1787 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
1788 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1789
1790 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1791 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1792 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1793 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1794 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1795 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1796 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1797 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1798
1799 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1800 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
1801 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1802 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1803
1804 .dp_aux_init = qmp_v4_dp_aux_init,
1805 .configure_dp_tx = qmp_v4_configure_dp_tx,
1806 .configure_dp_phy = qmp_v4_configure_dp_phy,
1807 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1808
1809 .reset_list = msm8996_usb3phy_reset_l,
1810 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1811 .vreg_list = qmp_phy_vreg_l,
1812 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1813 .regs = qmp_v45_usb3phy_regs_layout,
1814 };
1815
1816 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
1817 .offsets = &qmp_combo_offsets_v3,
1818
1819 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
1820 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1821 .tx_tbl = qmp_v3_usb3_tx_tbl,
1822 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1823 .rx_tbl = sm6350_usb3_rx_tbl,
1824 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
1825 .pcs_tbl = sm6350_usb3_pcs_tbl,
1826 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
1827
1828 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
1829 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
1830 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
1831 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
1832
1833 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
1834 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
1835 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
1836 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
1837 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
1838 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
1839 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
1840 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
1841
1842 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1843 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1844 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1845 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1846
1847 .dp_aux_init = qmp_v3_dp_aux_init,
1848 .configure_dp_tx = qmp_v3_configure_dp_tx,
1849 .configure_dp_phy = qmp_v3_configure_dp_phy,
1850 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
1851
1852 .reset_list = msm8996_usb3phy_reset_l,
1853 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1854 .vreg_list = qmp_phy_vreg_l,
1855 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1856 .regs = qmp_v3_usb3phy_regs_layout,
1857 };
1858
1859 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
1860 .offsets = &qmp_combo_offsets_v3,
1861
1862 .serdes_tbl = sm8150_usb3_serdes_tbl,
1863 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1864 .tx_tbl = sm8250_usb3_tx_tbl,
1865 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1866 .rx_tbl = sm8250_usb3_rx_tbl,
1867 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1868 .pcs_tbl = sm8250_usb3_pcs_tbl,
1869 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1870 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
1871 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1872
1873 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1874 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1875 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
1876 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
1877
1878 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1879 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1880 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1881 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1882 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1883 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1884 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1885 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1886
1887 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
1888 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
1889 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1890 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
1891
1892 .dp_aux_init = qmp_v4_dp_aux_init,
1893 .configure_dp_tx = qmp_v4_configure_dp_tx,
1894 .configure_dp_phy = qmp_v4_configure_dp_phy,
1895 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1896
1897 .reset_list = msm8996_usb3phy_reset_l,
1898 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1899 .vreg_list = qmp_phy_vreg_l,
1900 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1901 .regs = qmp_v45_usb3phy_regs_layout,
1902 .pcs_usb_offset = 0x300,
1903
1904 .has_pwrdn_delay = true,
1905 };
1906
1907 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
1908 .offsets = &qmp_combo_offsets_v3,
1909
1910 .serdes_tbl = sm8150_usb3_serdes_tbl,
1911 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1912 .tx_tbl = sm8350_usb3_tx_tbl,
1913 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1914 .rx_tbl = sm8350_usb3_rx_tbl,
1915 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1916 .pcs_tbl = sm8350_usb3_pcs_tbl,
1917 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1918 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
1919 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1920
1921 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
1922 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
1923 .dp_tx_tbl = qmp_v5_dp_tx_tbl,
1924 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
1925
1926 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
1927 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
1928 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
1929 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
1930 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
1931 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
1932 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
1933 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
1934
1935 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
1936 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
1937 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
1938 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
1939
1940 .dp_aux_init = qmp_v4_dp_aux_init,
1941 .configure_dp_tx = qmp_v4_configure_dp_tx,
1942 .configure_dp_phy = qmp_v4_configure_dp_phy,
1943 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1944
1945 .reset_list = msm8996_usb3phy_reset_l,
1946 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1947 .vreg_list = qmp_phy_vreg_l,
1948 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1949 .regs = qmp_v45_usb3phy_regs_layout,
1950
1951 .has_pwrdn_delay = true,
1952 };
1953
1954 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
1955 .offsets = &qmp_combo_offsets_v3,
1956
1957 .serdes_tbl = sm8550_usb3_serdes_tbl,
1958 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
1959 .tx_tbl = sm8550_usb3_tx_tbl,
1960 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1961 .rx_tbl = sm8550_usb3_rx_tbl,
1962 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1963 .pcs_tbl = sm8550_usb3_pcs_tbl,
1964 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1965 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
1966 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1967
1968 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1969 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1970 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
1971 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1972
1973 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1974 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1975 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1976 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1977 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1978 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1979 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1980 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1981
1982 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1983 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1984 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1985 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1986
1987 .dp_aux_init = qmp_v4_dp_aux_init,
1988 .configure_dp_tx = qmp_v4_configure_dp_tx,
1989 .configure_dp_phy = qmp_v4_configure_dp_phy,
1990 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1991
1992 .regs = qmp_v6_usb3phy_regs_layout,
1993 .reset_list = msm8996_usb3phy_reset_l,
1994 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1995 .vreg_list = qmp_phy_vreg_l,
1996 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1997 };
1998
1999 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
2000 {
2001 const struct qmp_phy_cfg *cfg = qmp->cfg;
2002 void __iomem *serdes = qmp->dp_serdes;
2003 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2004
2005 qmp_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num);
2006
2007 switch (dp_opts->link_rate) {
2008 case 1620:
2009 qmp_configure(serdes, cfg->serdes_tbl_rbr,
2010 cfg->serdes_tbl_rbr_num);
2011 break;
2012 case 2700:
2013 qmp_configure(serdes, cfg->serdes_tbl_hbr,
2014 cfg->serdes_tbl_hbr_num);
2015 break;
2016 case 5400:
2017 qmp_configure(serdes, cfg->serdes_tbl_hbr2,
2018 cfg->serdes_tbl_hbr2_num);
2019 break;
2020 case 8100:
2021 qmp_configure(serdes, cfg->serdes_tbl_hbr3,
2022 cfg->serdes_tbl_hbr3_num);
2023 break;
2024 default:
2025 /* Other link rates aren't supported */
2026 return -EINVAL;
2027 }
2028
2029 return 0;
2030 }
2031
2032 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
2033 {
2034 const struct qmp_phy_cfg *cfg = qmp->cfg;
2035
2036 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2037 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2038 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2039
2040 /* Turn on BIAS current for PHY/PLL */
2041 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2042 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2043 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2044
2045 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2046
2047 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2048 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2049 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2050 DP_PHY_PD_CTL_DP_CLAMP_EN,
2051 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2052
2053 writel(QSERDES_V3_COM_BIAS_EN |
2054 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2055 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2056 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2057 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2058
2059 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2060 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2061 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2062 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2063 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2064 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2065 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2066 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2067 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2068 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2069 qmp->dp_aux_cfg = 0;
2070
2071 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2072 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2073 PHY_AUX_REQ_ERR_MASK,
2074 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2075 }
2076
2077 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
2078 {
2079 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2080 const struct qmp_phy_cfg *cfg = qmp->cfg;
2081 unsigned int v_level = 0, p_level = 0;
2082 u8 voltage_swing_cfg, pre_emphasis_cfg;
2083 int i;
2084
2085 for (i = 0; i < dp_opts->lanes; i++) {
2086 v_level = max(v_level, dp_opts->voltage[i]);
2087 p_level = max(p_level, dp_opts->pre[i]);
2088 }
2089
2090 if (dp_opts->link_rate <= 2700) {
2091 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
2092 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
2093 } else {
2094 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
2095 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
2096 }
2097
2098 /* TODO: Move check to config check */
2099 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2100 return -EINVAL;
2101
2102 /* Enable MUX to use Cursor values from these registers */
2103 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2104 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2105
2106 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2107 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2108 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2109 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2110
2111 return 0;
2112 }
2113
2114 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
2115 {
2116 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2117 u32 bias_en, drvr_en;
2118
2119 if (qmp_combo_configure_dp_swing(qmp) < 0)
2120 return;
2121
2122 if (dp_opts->lanes == 1) {
2123 bias_en = 0x3e;
2124 drvr_en = 0x13;
2125 } else {
2126 bias_en = 0x3f;
2127 drvr_en = 0x10;
2128 }
2129
2130 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2131 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2132 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2133 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2134 }
2135
2136 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
2137 {
2138 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2139 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2140 u32 val;
2141
2142 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2143 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2144
2145 if (dp_opts->lanes == 4 || reverse)
2146 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2147 if (dp_opts->lanes == 4 || !reverse)
2148 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2149
2150 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2151
2152 if (reverse)
2153 writel(0x4c, qmp->pcs + QSERDES_DP_PHY_MODE);
2154 else
2155 writel(0x5c, qmp->pcs + QSERDES_DP_PHY_MODE);
2156
2157 return reverse;
2158 }
2159
2160 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
2161 {
2162 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2163 u32 phy_vco_div;
2164 unsigned long pixel_freq;
2165
2166 switch (dp_opts->link_rate) {
2167 case 1620:
2168 phy_vco_div = 0x1;
2169 pixel_freq = 1620000000UL / 2;
2170 break;
2171 case 2700:
2172 phy_vco_div = 0x1;
2173 pixel_freq = 2700000000UL / 2;
2174 break;
2175 case 5400:
2176 phy_vco_div = 0x2;
2177 pixel_freq = 5400000000UL / 4;
2178 break;
2179 case 8100:
2180 phy_vco_div = 0x0;
2181 pixel_freq = 8100000000UL / 6;
2182 break;
2183 default:
2184 /* Other link rates aren't supported */
2185 return -EINVAL;
2186 }
2187 writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_VCO_DIV);
2188
2189 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2190 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2191
2192 return 0;
2193 }
2194
2195 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
2196 {
2197 const struct qmp_phy_cfg *cfg = qmp->cfg;
2198 u32 status;
2199 int ret;
2200
2201 qmp_combo_configure_dp_mode(qmp);
2202
2203 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2204 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2205
2206 ret = qmp_combo_configure_dp_clocks(qmp);
2207 if (ret)
2208 return ret;
2209
2210 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2211 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2212 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2213 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2214 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2215
2216 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2217
2218 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2219 status,
2220 ((status & BIT(0)) > 0),
2221 500,
2222 10000))
2223 return -ETIMEDOUT;
2224
2225 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2226
2227 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2228 status,
2229 ((status & BIT(1)) > 0),
2230 500,
2231 10000))
2232 return -ETIMEDOUT;
2233
2234 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2235 udelay(2000);
2236 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2237
2238 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2239 status,
2240 ((status & BIT(1)) > 0),
2241 500,
2242 10000);
2243 }
2244
2245 /*
2246 * We need to calibrate the aux setting here as many times
2247 * as the caller tries
2248 */
2249 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2250 {
2251 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2252 u8 val;
2253
2254 qmp->dp_aux_cfg++;
2255 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2256 val = cfg1_settings[qmp->dp_aux_cfg];
2257
2258 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2259
2260 return 0;
2261 }
2262
2263 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2264 {
2265 const struct qmp_phy_cfg *cfg = qmp->cfg;
2266
2267 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2268 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2269 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2270
2271 /* Turn on BIAS current for PHY/PLL */
2272 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2273
2274 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2275 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2276 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2277 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2278 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2279 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2280 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2281 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2282 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2283 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2284 qmp->dp_aux_cfg = 0;
2285
2286 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2287 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2288 PHY_AUX_REQ_ERR_MASK,
2289 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2290 }
2291
2292 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2293 {
2294 const struct qmp_phy_cfg *cfg = qmp->cfg;
2295
2296 /* Program default values before writing proper values */
2297 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2298 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2299
2300 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2301 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2302
2303 qmp_combo_configure_dp_swing(qmp);
2304 }
2305
2306 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
2307 {
2308 const struct qmp_phy_cfg *cfg = qmp->cfg;
2309 u32 status;
2310 int ret;
2311
2312 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
2313
2314 qmp_combo_configure_dp_mode(qmp);
2315
2316 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2317 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2318
2319 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2320 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2321
2322 ret = qmp_combo_configure_dp_clocks(qmp);
2323 if (ret)
2324 return ret;
2325
2326 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2327 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2328 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2329 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2330
2331 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2332
2333 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2334 status,
2335 ((status & BIT(0)) > 0),
2336 500,
2337 10000))
2338 return -ETIMEDOUT;
2339
2340 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2341 status,
2342 ((status & BIT(0)) > 0),
2343 500,
2344 10000))
2345 return -ETIMEDOUT;
2346
2347 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2348 status,
2349 ((status & BIT(1)) > 0),
2350 500,
2351 10000))
2352 return -ETIMEDOUT;
2353
2354 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2355
2356 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2357 status,
2358 ((status & BIT(0)) > 0),
2359 500,
2360 10000))
2361 return -ETIMEDOUT;
2362
2363 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2364 status,
2365 ((status & BIT(1)) > 0),
2366 500,
2367 10000))
2368 return -ETIMEDOUT;
2369
2370 return 0;
2371 }
2372
2373 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2374 {
2375 const struct qmp_phy_cfg *cfg = qmp->cfg;
2376 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2377 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2378 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2379 u32 status;
2380 int ret;
2381
2382 ret = qmp_v456_configure_dp_phy(qmp);
2383 if (ret < 0)
2384 return ret;
2385
2386 /*
2387 * At least for 7nm DP PHY this has to be done after enabling link
2388 * clock.
2389 */
2390
2391 if (dp_opts->lanes == 1) {
2392 bias0_en = reverse ? 0x3e : 0x15;
2393 bias1_en = reverse ? 0x15 : 0x3e;
2394 drvr0_en = reverse ? 0x13 : 0x10;
2395 drvr1_en = reverse ? 0x10 : 0x13;
2396 } else if (dp_opts->lanes == 2) {
2397 bias0_en = reverse ? 0x3f : 0x15;
2398 bias1_en = reverse ? 0x15 : 0x3f;
2399 drvr0_en = 0x10;
2400 drvr1_en = 0x10;
2401 } else {
2402 bias0_en = 0x3f;
2403 bias1_en = 0x3f;
2404 drvr0_en = 0x10;
2405 drvr1_en = 0x10;
2406 }
2407
2408 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2409 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2410 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2411 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2412
2413 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2414 udelay(2000);
2415 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2416
2417 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2418 status,
2419 ((status & BIT(1)) > 0),
2420 500,
2421 10000))
2422 return -ETIMEDOUT;
2423
2424 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2425 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2426
2427 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2428 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2429
2430 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2431 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2432
2433 return 0;
2434
2435 return 0;
2436 }
2437
2438 /*
2439 * We need to calibrate the aux setting here as many times
2440 * as the caller tries
2441 */
2442 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2443 {
2444 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2445 u8 val;
2446
2447 qmp->dp_aux_cfg++;
2448 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2449 val = cfg1_settings[qmp->dp_aux_cfg];
2450
2451 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2452
2453 return 0;
2454 }
2455
2456 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2457 {
2458 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2459 struct qmp_combo *qmp = phy_get_drvdata(phy);
2460 const struct qmp_phy_cfg *cfg = qmp->cfg;
2461
2462 mutex_lock(&qmp->phy_mutex);
2463
2464 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2465 if (qmp->dp_opts.set_voltages) {
2466 cfg->configure_dp_tx(qmp);
2467 qmp->dp_opts.set_voltages = 0;
2468 }
2469
2470 mutex_unlock(&qmp->phy_mutex);
2471
2472 return 0;
2473 }
2474
2475 static int qmp_combo_dp_calibrate(struct phy *phy)
2476 {
2477 struct qmp_combo *qmp = phy_get_drvdata(phy);
2478 const struct qmp_phy_cfg *cfg = qmp->cfg;
2479 int ret = 0;
2480
2481 mutex_lock(&qmp->phy_mutex);
2482
2483 if (cfg->calibrate_dp_phy)
2484 ret = cfg->calibrate_dp_phy(qmp);
2485
2486 mutex_unlock(&qmp->phy_mutex);
2487
2488 return ret;
2489 }
2490
2491 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
2492 {
2493 const struct qmp_phy_cfg *cfg = qmp->cfg;
2494 void __iomem *com = qmp->com;
2495 int ret;
2496 u32 val;
2497
2498 if (!force && qmp->init_count++)
2499 return 0;
2500
2501 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2502 if (ret) {
2503 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2504 goto err_decrement_count;
2505 }
2506
2507 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2508 if (ret) {
2509 dev_err(qmp->dev, "reset assert failed\n");
2510 goto err_disable_regulators;
2511 }
2512
2513 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2514 if (ret) {
2515 dev_err(qmp->dev, "reset deassert failed\n");
2516 goto err_disable_regulators;
2517 }
2518
2519 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2520 if (ret)
2521 goto err_assert_reset;
2522
2523 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
2524
2525 /* override hardware control for reset of qmp phy */
2526 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2527 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2528 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2529
2530 /* Use software based port select and switch on typec orientation */
2531 val = SW_PORTSELECT_MUX;
2532 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
2533 val |= SW_PORTSELECT_VAL;
2534 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
2535 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
2536
2537 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2538 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2539 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2540 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2541
2542 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2543 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2544
2545 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2546 SW_PWRDN);
2547
2548 return 0;
2549
2550 err_assert_reset:
2551 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2552 err_disable_regulators:
2553 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2554 err_decrement_count:
2555 qmp->init_count--;
2556
2557 return ret;
2558 }
2559
2560 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
2561 {
2562 const struct qmp_phy_cfg *cfg = qmp->cfg;
2563
2564 if (!force && --qmp->init_count)
2565 return 0;
2566
2567 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2568
2569 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2570
2571 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2572
2573 return 0;
2574 }
2575
2576 static int qmp_combo_dp_init(struct phy *phy)
2577 {
2578 struct qmp_combo *qmp = phy_get_drvdata(phy);
2579 const struct qmp_phy_cfg *cfg = qmp->cfg;
2580 int ret;
2581
2582 mutex_lock(&qmp->phy_mutex);
2583
2584 ret = qmp_combo_com_init(qmp, false);
2585 if (ret)
2586 goto out_unlock;
2587
2588 cfg->dp_aux_init(qmp);
2589
2590 qmp->dp_init_count++;
2591
2592 out_unlock:
2593 mutex_unlock(&qmp->phy_mutex);
2594 return ret;
2595 }
2596
2597 static int qmp_combo_dp_exit(struct phy *phy)
2598 {
2599 struct qmp_combo *qmp = phy_get_drvdata(phy);
2600
2601 mutex_lock(&qmp->phy_mutex);
2602
2603 qmp_combo_com_exit(qmp, false);
2604
2605 qmp->dp_init_count--;
2606
2607 mutex_unlock(&qmp->phy_mutex);
2608
2609 return 0;
2610 }
2611
2612 static int qmp_combo_dp_power_on(struct phy *phy)
2613 {
2614 struct qmp_combo *qmp = phy_get_drvdata(phy);
2615 const struct qmp_phy_cfg *cfg = qmp->cfg;
2616 void __iomem *tx = qmp->dp_tx;
2617 void __iomem *tx2 = qmp->dp_tx2;
2618
2619 mutex_lock(&qmp->phy_mutex);
2620
2621 qmp_combo_dp_serdes_init(qmp);
2622
2623 qmp_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
2624 qmp_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
2625
2626 /* Configure special DP tx tunings */
2627 cfg->configure_dp_tx(qmp);
2628
2629 /* Configure link rate, swing, etc. */
2630 cfg->configure_dp_phy(qmp);
2631
2632 mutex_unlock(&qmp->phy_mutex);
2633
2634 return 0;
2635 }
2636
2637 static int qmp_combo_dp_power_off(struct phy *phy)
2638 {
2639 struct qmp_combo *qmp = phy_get_drvdata(phy);
2640
2641 mutex_lock(&qmp->phy_mutex);
2642
2643 /* Assert DP PHY power down */
2644 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2645
2646 mutex_unlock(&qmp->phy_mutex);
2647
2648 return 0;
2649 }
2650
2651 static int qmp_combo_usb_power_on(struct phy *phy)
2652 {
2653 struct qmp_combo *qmp = phy_get_drvdata(phy);
2654 const struct qmp_phy_cfg *cfg = qmp->cfg;
2655 void __iomem *serdes = qmp->serdes;
2656 void __iomem *tx = qmp->tx;
2657 void __iomem *rx = qmp->rx;
2658 void __iomem *tx2 = qmp->tx2;
2659 void __iomem *rx2 = qmp->rx2;
2660 void __iomem *pcs = qmp->pcs;
2661 void __iomem *pcs_usb = qmp->pcs_usb;
2662 void __iomem *status;
2663 unsigned int val;
2664 int ret;
2665
2666 qmp_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
2667
2668 ret = clk_prepare_enable(qmp->pipe_clk);
2669 if (ret) {
2670 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2671 return ret;
2672 }
2673
2674 /* Tx, Rx, and PCS configurations */
2675 qmp_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
2676 qmp_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
2677
2678 qmp_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
2679 qmp_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
2680
2681 qmp_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2682
2683 if (pcs_usb)
2684 qmp_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
2685
2686 if (cfg->has_pwrdn_delay)
2687 usleep_range(10, 20);
2688
2689 /* Pull PHY out of reset state */
2690 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2691
2692 /* start SerDes and Phy-Coding-Sublayer */
2693 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
2694
2695 status = pcs + cfg->regs[QPHY_PCS_STATUS];
2696 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
2697 PHY_INIT_COMPLETE_TIMEOUT);
2698 if (ret) {
2699 dev_err(qmp->dev, "phy initialization timed-out\n");
2700 goto err_disable_pipe_clk;
2701 }
2702
2703 return 0;
2704
2705 err_disable_pipe_clk:
2706 clk_disable_unprepare(qmp->pipe_clk);
2707
2708 return ret;
2709 }
2710
2711 static int qmp_combo_usb_power_off(struct phy *phy)
2712 {
2713 struct qmp_combo *qmp = phy_get_drvdata(phy);
2714 const struct qmp_phy_cfg *cfg = qmp->cfg;
2715
2716 clk_disable_unprepare(qmp->pipe_clk);
2717
2718 /* PHY reset */
2719 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2720
2721 /* stop SerDes and Phy-Coding-Sublayer */
2722 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
2723 SERDES_START | PCS_START);
2724
2725 /* Put PHY into POWER DOWN state: active low */
2726 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2727 SW_PWRDN);
2728
2729 return 0;
2730 }
2731
2732 static int qmp_combo_usb_init(struct phy *phy)
2733 {
2734 struct qmp_combo *qmp = phy_get_drvdata(phy);
2735 int ret;
2736
2737 mutex_lock(&qmp->phy_mutex);
2738 ret = qmp_combo_com_init(qmp, false);
2739 if (ret)
2740 goto out_unlock;
2741
2742 ret = qmp_combo_usb_power_on(phy);
2743 if (ret) {
2744 qmp_combo_com_exit(qmp, false);
2745 goto out_unlock;
2746 }
2747
2748 qmp->usb_init_count++;
2749
2750 out_unlock:
2751 mutex_unlock(&qmp->phy_mutex);
2752 return ret;
2753 }
2754
2755 static int qmp_combo_usb_exit(struct phy *phy)
2756 {
2757 struct qmp_combo *qmp = phy_get_drvdata(phy);
2758 int ret;
2759
2760 mutex_lock(&qmp->phy_mutex);
2761 ret = qmp_combo_usb_power_off(phy);
2762 if (ret)
2763 goto out_unlock;
2764
2765 ret = qmp_combo_com_exit(qmp, false);
2766 if (ret)
2767 goto out_unlock;
2768
2769 qmp->usb_init_count--;
2770
2771 out_unlock:
2772 mutex_unlock(&qmp->phy_mutex);
2773 return ret;
2774 }
2775
2776 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
2777 {
2778 struct qmp_combo *qmp = phy_get_drvdata(phy);
2779
2780 qmp->mode = mode;
2781
2782 return 0;
2783 }
2784
2785 static const struct phy_ops qmp_combo_usb_phy_ops = {
2786 .init = qmp_combo_usb_init,
2787 .exit = qmp_combo_usb_exit,
2788 .set_mode = qmp_combo_usb_set_mode,
2789 .owner = THIS_MODULE,
2790 };
2791
2792 static const struct phy_ops qmp_combo_dp_phy_ops = {
2793 .init = qmp_combo_dp_init,
2794 .configure = qmp_combo_dp_configure,
2795 .power_on = qmp_combo_dp_power_on,
2796 .calibrate = qmp_combo_dp_calibrate,
2797 .power_off = qmp_combo_dp_power_off,
2798 .exit = qmp_combo_dp_exit,
2799 .owner = THIS_MODULE,
2800 };
2801
2802 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
2803 {
2804 const struct qmp_phy_cfg *cfg = qmp->cfg;
2805 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2806 void __iomem *pcs_misc = qmp->pcs_misc;
2807 u32 intr_mask;
2808
2809 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
2810 qmp->mode == PHY_MODE_USB_DEVICE_SS)
2811 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2812 else
2813 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2814
2815 /* Clear any pending interrupts status */
2816 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2817 /* Writing 1 followed by 0 clears the interrupt */
2818 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2819
2820 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2821 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2822
2823 /* Enable required PHY autonomous mode interrupts */
2824 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2825
2826 /* Enable i/o clamp_n for autonomous mode */
2827 if (pcs_misc)
2828 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2829 }
2830
2831 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
2832 {
2833 const struct qmp_phy_cfg *cfg = qmp->cfg;
2834 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
2835 void __iomem *pcs_misc = qmp->pcs_misc;
2836
2837 /* Disable i/o clamp_n on resume for normal mode */
2838 if (pcs_misc)
2839 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2840
2841 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2842 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2843
2844 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2845 /* Writing 1 followed by 0 clears the interrupt */
2846 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2847 }
2848
2849 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
2850 {
2851 struct qmp_combo *qmp = dev_get_drvdata(dev);
2852
2853 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
2854
2855 if (!qmp->init_count) {
2856 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2857 return 0;
2858 }
2859
2860 qmp_combo_enable_autonomous_mode(qmp);
2861
2862 clk_disable_unprepare(qmp->pipe_clk);
2863 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2864
2865 return 0;
2866 }
2867
2868 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
2869 {
2870 struct qmp_combo *qmp = dev_get_drvdata(dev);
2871 int ret = 0;
2872
2873 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
2874
2875 if (!qmp->init_count) {
2876 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2877 return 0;
2878 }
2879
2880 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
2881 if (ret)
2882 return ret;
2883
2884 ret = clk_prepare_enable(qmp->pipe_clk);
2885 if (ret) {
2886 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2887 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
2888 return ret;
2889 }
2890
2891 qmp_combo_disable_autonomous_mode(qmp);
2892
2893 return 0;
2894 }
2895
2896 static const struct dev_pm_ops qmp_combo_pm_ops = {
2897 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
2898 qmp_combo_runtime_resume, NULL)
2899 };
2900
2901 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
2902 {
2903 const struct qmp_phy_cfg *cfg = qmp->cfg;
2904 struct device *dev = qmp->dev;
2905 int num = cfg->num_vregs;
2906 int ret, i;
2907
2908 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2909 if (!qmp->vregs)
2910 return -ENOMEM;
2911
2912 for (i = 0; i < num; i++)
2913 qmp->vregs[i].supply = cfg->vreg_list[i].name;
2914
2915 ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
2916 if (ret) {
2917 dev_err(dev, "failed at devm_regulator_bulk_get\n");
2918 return ret;
2919 }
2920
2921 for (i = 0; i < num; i++) {
2922 ret = regulator_set_load(qmp->vregs[i].consumer,
2923 cfg->vreg_list[i].enable_load);
2924 if (ret) {
2925 dev_err(dev, "failed to set load at %s\n",
2926 qmp->vregs[i].supply);
2927 return ret;
2928 }
2929 }
2930
2931 return 0;
2932 }
2933
2934 static int qmp_combo_reset_init(struct qmp_combo *qmp)
2935 {
2936 const struct qmp_phy_cfg *cfg = qmp->cfg;
2937 struct device *dev = qmp->dev;
2938 int i;
2939 int ret;
2940
2941 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2942 sizeof(*qmp->resets), GFP_KERNEL);
2943 if (!qmp->resets)
2944 return -ENOMEM;
2945
2946 for (i = 0; i < cfg->num_resets; i++)
2947 qmp->resets[i].id = cfg->reset_list[i];
2948
2949 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2950 if (ret)
2951 return dev_err_probe(dev, ret, "failed to get resets\n");
2952
2953 return 0;
2954 }
2955
2956 static int qmp_combo_clk_init(struct qmp_combo *qmp)
2957 {
2958 struct device *dev = qmp->dev;
2959 int num = ARRAY_SIZE(qmp_combo_phy_clk_l);
2960 int i;
2961
2962 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2963 if (!qmp->clks)
2964 return -ENOMEM;
2965
2966 for (i = 0; i < num; i++)
2967 qmp->clks[i].id = qmp_combo_phy_clk_l[i];
2968
2969 qmp->num_clks = num;
2970
2971 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
2972 }
2973
2974 static void phy_clk_release_provider(void *res)
2975 {
2976 of_clk_del_provider(res);
2977 }
2978
2979 /*
2980 * Register a fixed rate pipe clock.
2981 *
2982 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2983 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2984 * by the PHY driver for its operations.
2985 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2986 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2987 * Below picture shows this relationship.
2988 *
2989 * +---------------+
2990 * | PHY block |<<---------------------------------------+
2991 * | | |
2992 * | +-------+ | +-----+ |
2993 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2994 * clk | +-------+ | +-----+
2995 * +---------------+
2996 */
2997 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
2998 {
2999 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3000 struct clk_init_data init = { };
3001 char name[64];
3002
3003 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
3004 init.name = name;
3005 init.ops = &clk_fixed_rate_ops;
3006
3007 /* controllers using QMP phys use 125MHz pipe clock interface */
3008 fixed->fixed_rate = 125000000;
3009 fixed->hw.init = &init;
3010
3011 return devm_clk_hw_register(qmp->dev, &fixed->hw);
3012 }
3013
3014 /*
3015 * Display Port PLL driver block diagram for branch clocks
3016 *
3017 * +------------------------------+
3018 * | DP_VCO_CLK |
3019 * | |
3020 * | +-------------------+ |
3021 * | | (DP PLL/VCO) | |
3022 * | +---------+---------+ |
3023 * | v |
3024 * | +----------+-----------+ |
3025 * | | hsclk_divsel_clk_src | |
3026 * | +----------+-----------+ |
3027 * +------------------------------+
3028 * |
3029 * +---------<---------v------------>----------+
3030 * | |
3031 * +--------v----------------+ |
3032 * | dp_phy_pll_link_clk | |
3033 * | link_clk | |
3034 * +--------+----------------+ |
3035 * | |
3036 * | |
3037 * v v
3038 * Input to DISPCC block |
3039 * for link clk, crypto clk |
3040 * and interface clock |
3041 * |
3042 * |
3043 * +--------<------------+-----------------+---<---+
3044 * | | |
3045 * +----v---------+ +--------v-----+ +--------v------+
3046 * | vco_divided | | vco_divided | | vco_divided |
3047 * | _clk_src | | _clk_src | | _clk_src |
3048 * | | | | | |
3049 * |divsel_six | | divsel_two | | divsel_four |
3050 * +-------+------+ +-----+--------+ +--------+------+
3051 * | | |
3052 * v---->----------v-------------<------v
3053 * |
3054 * +----------+-----------------+
3055 * | dp_phy_pll_vco_div_clk |
3056 * +---------+------------------+
3057 * |
3058 * v
3059 * Input to DISPCC block
3060 * for DP pixel clock
3061 *
3062 */
3063 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3064 {
3065 switch (req->rate) {
3066 case 1620000000UL / 2:
3067 case 2700000000UL / 2:
3068 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3069 return 0;
3070 default:
3071 return -EINVAL;
3072 }
3073 }
3074
3075 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3076 {
3077 const struct qmp_combo *qmp;
3078 const struct phy_configure_opts_dp *dp_opts;
3079
3080 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3081 dp_opts = &qmp->dp_opts;
3082
3083 switch (dp_opts->link_rate) {
3084 case 1620:
3085 return 1620000000UL / 2;
3086 case 2700:
3087 return 2700000000UL / 2;
3088 case 5400:
3089 return 5400000000UL / 4;
3090 case 8100:
3091 return 8100000000UL / 6;
3092 default:
3093 return 0;
3094 }
3095 }
3096
3097 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3098 .determine_rate = qmp_dp_pixel_clk_determine_rate,
3099 .recalc_rate = qmp_dp_pixel_clk_recalc_rate,
3100 };
3101
3102 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3103 {
3104 switch (req->rate) {
3105 case 162000000:
3106 case 270000000:
3107 case 540000000:
3108 case 810000000:
3109 return 0;
3110 default:
3111 return -EINVAL;
3112 }
3113 }
3114
3115 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3116 {
3117 const struct qmp_combo *qmp;
3118 const struct phy_configure_opts_dp *dp_opts;
3119
3120 qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3121 dp_opts = &qmp->dp_opts;
3122
3123 switch (dp_opts->link_rate) {
3124 case 1620:
3125 case 2700:
3126 case 5400:
3127 case 8100:
3128 return dp_opts->link_rate * 100000;
3129 default:
3130 return 0;
3131 }
3132 }
3133
3134 static const struct clk_ops qmp_dp_link_clk_ops = {
3135 .determine_rate = qmp_dp_link_clk_determine_rate,
3136 .recalc_rate = qmp_dp_link_clk_recalc_rate,
3137 };
3138
3139 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3140 {
3141 struct qmp_combo *qmp = data;
3142 unsigned int idx = clkspec->args[0];
3143
3144 if (idx >= 2) {
3145 pr_err("%s: invalid index %u\n", __func__, idx);
3146 return ERR_PTR(-EINVAL);
3147 }
3148
3149 if (idx == 0)
3150 return &qmp->dp_link_hw;
3151
3152 return &qmp->dp_pixel_hw;
3153 }
3154
3155 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3156 {
3157 struct clk_init_data init = { };
3158 char name[64];
3159 int ret;
3160
3161 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3162 init.ops = &qmp_dp_link_clk_ops;
3163 init.name = name;
3164 qmp->dp_link_hw.init = &init;
3165 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3166 if (ret)
3167 return ret;
3168
3169 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3170 init.ops = &qmp_dp_pixel_clk_ops;
3171 init.name = name;
3172 qmp->dp_pixel_hw.init = &init;
3173 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3174 if (ret)
3175 return ret;
3176
3177 return 0;
3178 }
3179
3180 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3181 {
3182 struct qmp_combo *qmp = data;
3183
3184 switch (clkspec->args[0]) {
3185 case QMP_USB43DP_USB3_PIPE_CLK:
3186 return &qmp->pipe_clk_fixed.hw;
3187 case QMP_USB43DP_DP_LINK_CLK:
3188 return &qmp->dp_link_hw;
3189 case QMP_USB43DP_DP_VCO_DIV_CLK:
3190 return &qmp->dp_pixel_hw;
3191 }
3192
3193 return ERR_PTR(-EINVAL);
3194 }
3195
3196 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3197 struct device_node *dp_np)
3198 {
3199 int ret;
3200
3201 ret = phy_pipe_clk_register(qmp, usb_np);
3202 if (ret)
3203 return ret;
3204
3205 ret = phy_dp_clks_register(qmp, dp_np);
3206 if (ret)
3207 return ret;
3208
3209 /*
3210 * Register a single provider for bindings without child nodes.
3211 */
3212 if (usb_np == qmp->dev->of_node)
3213 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3214
3215 /*
3216 * Register multiple providers for legacy bindings with child nodes.
3217 */
3218 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3219 &qmp->pipe_clk_fixed.hw);
3220 if (ret)
3221 return ret;
3222
3223 /*
3224 * Roll a devm action because the clock provider is the child node, but
3225 * the child node is not actually a device.
3226 */
3227 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3228 if (ret)
3229 return ret;
3230
3231 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3232 if (ret)
3233 return ret;
3234
3235 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3236 }
3237
3238 #if IS_ENABLED(CONFIG_TYPEC)
3239 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3240 enum typec_orientation orientation)
3241 {
3242 struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3243 const struct qmp_phy_cfg *cfg = qmp->cfg;
3244
3245 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3246 return 0;
3247
3248 mutex_lock(&qmp->phy_mutex);
3249 qmp->orientation = orientation;
3250
3251 if (qmp->init_count) {
3252 if (qmp->usb_init_count)
3253 qmp_combo_usb_power_off(qmp->usb_phy);
3254 qmp_combo_com_exit(qmp, true);
3255
3256 qmp_combo_com_init(qmp, true);
3257 if (qmp->usb_init_count)
3258 qmp_combo_usb_power_on(qmp->usb_phy);
3259 if (qmp->dp_init_count)
3260 cfg->dp_aux_init(qmp);
3261 }
3262 mutex_unlock(&qmp->phy_mutex);
3263
3264 return 0;
3265 }
3266
3267 static void qmp_combo_typec_unregister(void *data)
3268 {
3269 struct qmp_combo *qmp = data;
3270
3271 typec_switch_unregister(qmp->sw);
3272 }
3273
3274 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3275 {
3276 struct typec_switch_desc sw_desc = {};
3277 struct device *dev = qmp->dev;
3278
3279 sw_desc.drvdata = qmp;
3280 sw_desc.fwnode = dev->fwnode;
3281 sw_desc.set = qmp_combo_typec_switch_set;
3282 qmp->sw = typec_switch_register(dev, &sw_desc);
3283 if (IS_ERR(qmp->sw)) {
3284 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3285 return PTR_ERR(qmp->sw);
3286 }
3287
3288 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp);
3289 }
3290 #else
3291 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp)
3292 {
3293 return 0;
3294 }
3295 #endif
3296
3297 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np)
3298 {
3299 struct device *dev = qmp->dev;
3300
3301 /*
3302 * Get memory resources from the DP child node:
3303 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3304 * tx2 -> 3; rx2 -> 4
3305 *
3306 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3307 * implementation.
3308 */
3309 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3310 if (IS_ERR(qmp->dp_tx))
3311 return PTR_ERR(qmp->dp_tx);
3312
3313 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3314 if (IS_ERR(qmp->dp_dp_phy))
3315 return PTR_ERR(qmp->dp_dp_phy);
3316
3317 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3318 if (IS_ERR(qmp->dp_tx2))
3319 return PTR_ERR(qmp->dp_tx2);
3320
3321 return 0;
3322 }
3323
3324 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np)
3325 {
3326 const struct qmp_phy_cfg *cfg = qmp->cfg;
3327 struct device *dev = qmp->dev;
3328
3329 /*
3330 * Get memory resources from the USB child node:
3331 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3332 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3333 */
3334 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3335 if (IS_ERR(qmp->tx))
3336 return PTR_ERR(qmp->tx);
3337
3338 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3339 if (IS_ERR(qmp->rx))
3340 return PTR_ERR(qmp->rx);
3341
3342 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3343 if (IS_ERR(qmp->pcs))
3344 return PTR_ERR(qmp->pcs);
3345
3346 if (cfg->pcs_usb_offset)
3347 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3348
3349 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3350 if (IS_ERR(qmp->tx2))
3351 return PTR_ERR(qmp->tx2);
3352
3353 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3354 if (IS_ERR(qmp->rx2))
3355 return PTR_ERR(qmp->rx2);
3356
3357 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3358 if (IS_ERR(qmp->pcs_misc)) {
3359 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
3360 qmp->pcs_misc = NULL;
3361 }
3362
3363 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
3364 if (IS_ERR(qmp->pipe_clk)) {
3365 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3366 "failed to get pipe clock\n");
3367 }
3368
3369 return 0;
3370 }
3371
3372 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
3373 struct device_node *dp_np)
3374 {
3375 struct platform_device *pdev = to_platform_device(qmp->dev);
3376 int ret;
3377
3378 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3379 if (IS_ERR(qmp->serdes))
3380 return PTR_ERR(qmp->serdes);
3381
3382 qmp->com = devm_platform_ioremap_resource(pdev, 1);
3383 if (IS_ERR(qmp->com))
3384 return PTR_ERR(qmp->com);
3385
3386 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
3387 if (IS_ERR(qmp->dp_serdes))
3388 return PTR_ERR(qmp->dp_serdes);
3389
3390 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np);
3391 if (ret)
3392 return ret;
3393
3394 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np);
3395 if (ret)
3396 return ret;
3397
3398 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
3399 if (ret < 0)
3400 return ret;
3401
3402 qmp->num_clks = ret;
3403
3404 return 0;
3405 }
3406
3407 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
3408 {
3409 struct platform_device *pdev = to_platform_device(qmp->dev);
3410 const struct qmp_phy_cfg *cfg = qmp->cfg;
3411 const struct qmp_combo_offsets *offs = cfg->offsets;
3412 struct device *dev = qmp->dev;
3413 void __iomem *base;
3414 int ret;
3415
3416 if (!offs)
3417 return -EINVAL;
3418
3419 base = devm_platform_ioremap_resource(pdev, 0);
3420 if (IS_ERR(base))
3421 return PTR_ERR(base);
3422
3423 qmp->com = base + offs->com;
3424 qmp->tx = base + offs->txa;
3425 qmp->rx = base + offs->rxa;
3426 qmp->tx2 = base + offs->txb;
3427 qmp->rx2 = base + offs->rxb;
3428
3429 qmp->serdes = base + offs->usb3_serdes;
3430 qmp->pcs_misc = base + offs->usb3_pcs_misc;
3431 qmp->pcs = base + offs->usb3_pcs;
3432 qmp->pcs_usb = base + offs->usb3_pcs_usb;
3433
3434 qmp->dp_serdes = base + offs->dp_serdes;
3435 if (offs->dp_txa) {
3436 qmp->dp_tx = base + offs->dp_txa;
3437 qmp->dp_tx2 = base + offs->dp_txb;
3438 } else {
3439 qmp->dp_tx = base + offs->txa;
3440 qmp->dp_tx2 = base + offs->txb;
3441 }
3442 qmp->dp_dp_phy = base + offs->dp_dp_phy;
3443
3444 ret = qmp_combo_clk_init(qmp);
3445 if (ret)
3446 return ret;
3447
3448 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
3449 if (IS_ERR(qmp->pipe_clk)) {
3450 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
3451 "failed to get usb3_pipe clock\n");
3452 }
3453
3454 return 0;
3455 }
3456
3457 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
3458 {
3459 struct qmp_combo *qmp = dev_get_drvdata(dev);
3460
3461 if (args->args_count == 0)
3462 return ERR_PTR(-EINVAL);
3463
3464 switch (args->args[0]) {
3465 case QMP_USB43DP_USB3_PHY:
3466 return qmp->usb_phy;
3467 case QMP_USB43DP_DP_PHY:
3468 return qmp->dp_phy;
3469 }
3470
3471 return ERR_PTR(-EINVAL);
3472 }
3473
3474 static int qmp_combo_probe(struct platform_device *pdev)
3475 {
3476 struct qmp_combo *qmp;
3477 struct device *dev = &pdev->dev;
3478 struct device_node *dp_np, *usb_np;
3479 struct phy_provider *phy_provider;
3480 int ret;
3481
3482 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3483 if (!qmp)
3484 return -ENOMEM;
3485
3486 qmp->dev = dev;
3487
3488 qmp->orientation = TYPEC_ORIENTATION_NORMAL;
3489
3490 qmp->cfg = of_device_get_match_data(dev);
3491 if (!qmp->cfg)
3492 return -EINVAL;
3493
3494 mutex_init(&qmp->phy_mutex);
3495
3496 ret = qmp_combo_reset_init(qmp);
3497 if (ret)
3498 return ret;
3499
3500 ret = qmp_combo_vreg_init(qmp);
3501 if (ret)
3502 return ret;
3503
3504 /* Check for legacy binding with child nodes. */
3505 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
3506 if (usb_np) {
3507 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
3508 if (!dp_np) {
3509 of_node_put(usb_np);
3510 return -EINVAL;
3511 }
3512
3513 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
3514 } else {
3515 usb_np = of_node_get(dev->of_node);
3516 dp_np = of_node_get(dev->of_node);
3517
3518 ret = qmp_combo_parse_dt(qmp);
3519 }
3520 if (ret)
3521 goto err_node_put;
3522
3523 ret = qmp_combo_typec_switch_register(qmp);
3524 if (ret)
3525 goto err_node_put;
3526
3527 ret = drm_aux_bridge_register(dev);
3528 if (ret)
3529 goto err_node_put;
3530
3531 pm_runtime_set_active(dev);
3532 ret = devm_pm_runtime_enable(dev);
3533 if (ret)
3534 goto err_node_put;
3535 /*
3536 * Prevent runtime pm from being ON by default. Users can enable
3537 * it using power/control in sysfs.
3538 */
3539 pm_runtime_forbid(dev);
3540
3541 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
3542 if (ret)
3543 goto err_node_put;
3544
3545 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
3546 if (IS_ERR(qmp->usb_phy)) {
3547 ret = PTR_ERR(qmp->usb_phy);
3548 dev_err(dev, "failed to create USB PHY: %d\n", ret);
3549 goto err_node_put;
3550 }
3551
3552 phy_set_drvdata(qmp->usb_phy, qmp);
3553
3554 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
3555 if (IS_ERR(qmp->dp_phy)) {
3556 ret = PTR_ERR(qmp->dp_phy);
3557 dev_err(dev, "failed to create DP PHY: %d\n", ret);
3558 goto err_node_put;
3559 }
3560
3561 phy_set_drvdata(qmp->dp_phy, qmp);
3562
3563 dev_set_drvdata(dev, qmp);
3564
3565 if (usb_np == dev->of_node)
3566 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
3567 else
3568 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3569
3570 of_node_put(usb_np);
3571 of_node_put(dp_np);
3572
3573 return PTR_ERR_OR_ZERO(phy_provider);
3574
3575 err_node_put:
3576 of_node_put(usb_np);
3577 of_node_put(dp_np);
3578 return ret;
3579 }
3580
3581 static const struct of_device_id qmp_combo_of_match_table[] = {
3582 {
3583 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
3584 .data = &sc7180_usb3dpphy_cfg,
3585 },
3586 {
3587 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
3588 .data = &sm8250_usb3dpphy_cfg,
3589 },
3590 {
3591 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
3592 .data = &sc8180x_usb3dpphy_cfg,
3593 },
3594 {
3595 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
3596 .data = &sc8280xp_usb43dpphy_cfg,
3597 },
3598 {
3599 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
3600 .data = &sdm845_usb3dpphy_cfg,
3601 },
3602 {
3603 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
3604 .data = &sm6350_usb3dpphy_cfg,
3605 },
3606 {
3607 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
3608 .data = &sc8180x_usb3dpphy_cfg,
3609 },
3610 {
3611 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
3612 .data = &sm8250_usb3dpphy_cfg,
3613 },
3614 {
3615 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
3616 .data = &sm8350_usb3dpphy_cfg,
3617 },
3618 {
3619 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
3620 .data = &sm8350_usb3dpphy_cfg,
3621 },
3622 {
3623 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
3624 .data = &sm8550_usb3dpphy_cfg,
3625 },
3626 {
3627 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
3628 .data = &sm8550_usb3dpphy_cfg,
3629 },
3630 {
3631 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
3632 .data = &x1e80100_usb3dpphy_cfg,
3633 },
3634 { }
3635 };
3636 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
3637
3638 static struct platform_driver qmp_combo_driver = {
3639 .probe = qmp_combo_probe,
3640 .driver = {
3641 .name = "qcom-qmp-combo-phy",
3642 .pm = &qmp_combo_pm_ops,
3643 .of_match_table = qmp_combo_of_match_table,
3644 },
3645 };
3646
3647 module_platform_driver(qmp_combo_driver);
3648
3649 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3650 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
3651 MODULE_LICENSE("GPL v2");