drivers/phy/ti/phy-j721e-wiz.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
   4  * Jean-Jacques Hiblot <jjhiblot@ti.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <dm/device_compat.h>
  11 #include <asm/gpio.h>
  12 #include <dm/lists.h>
  13 #include <dm/device-internal.h>
  14 #include <regmap.h>
  15 #include <reset-uclass.h>
  16 #include <dt-bindings/phy/phy.h>
  17
  18 #include <dt-bindings/phy/phy-ti.h>
  19
  20 #define WIZ_MAX_INPUT_CLOCKS    4
  21 /* To include mux clocks, divider clocks and gate clocks */
  22 #define WIZ_MAX_OUTPUT_CLOCKS   32
  23
  24 #define WIZ_MAX_LANES           4
  25 #define WIZ_MUX_NUM_CLOCKS      3
  26 #define WIZ_DIV_NUM_CLOCKS_16G  2
  27 #define WIZ_DIV_NUM_CLOCKS_10G  1
  28
  29 #define WIZ_SERDES_CTRL         0x404
  30 #define WIZ_SERDES_TOP_CTRL     0x408
  31 #define WIZ_SERDES_RST          0x40c
  32 #define WIZ_SERDES_TYPEC        0x410
  33 #define WIZ_LANECTL(n)          (0x480 + (0x40 * (n)))
  34 #define WIZ_LANEDIV(n)          (0x484 + (0x40 * (n)))
  35
  36 #define WIZ_MAX_LANES           4
  37 #define WIZ_MUX_NUM_CLOCKS      3
  38 #define WIZ_DIV_NUM_CLOCKS_16G  2
  39 #define WIZ_DIV_NUM_CLOCKS_10G  1
  40
  41 #define WIZ_SERDES_TYPEC_LN10_SWAP      BIT(30)
  42
  43 enum wiz_lane_standard_mode {
  44         LANE_MODE_GEN1,
  45         LANE_MODE_GEN2,
  46         LANE_MODE_GEN3,
  47         LANE_MODE_GEN4,
  48 };
  49
  50 enum wiz_refclk_mux_sel {
  51         PLL0_REFCLK,
  52         PLL1_REFCLK,
  53         REFCLK_DIG,
  54 };
  55
  56 enum wiz_refclk_div_sel {
  57         CMN_REFCLK,
  58         CMN_REFCLK1,
  59 };
  60
  61 enum wiz_clock_input {
  62         WIZ_CORE_REFCLK,
  63         WIZ_EXT_REFCLK,
  64         WIZ_CORE_REFCLK1,
  65         WIZ_EXT_REFCLK1,
  66 };
  67
  68 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  69 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  70 static const struct reg_field pll1_refclk_mux_sel =
  71                                         REG_FIELD(WIZ_SERDES_RST, 29, 29);
  72 static const struct reg_field pll1_refclk_mux_sel_2 =
  73                                         REG_FIELD(WIZ_SERDES_RST, 22, 23);
  74 static const struct reg_field pll0_refclk_mux_sel =
  75                                         REG_FIELD(WIZ_SERDES_RST, 28, 28);
  76 static const struct reg_field pll0_refclk_mux_sel_2 =
  77                                         REG_FIELD(WIZ_SERDES_RST, 28, 29);
  78 static const struct reg_field refclk_dig_sel_16g =
  79                                         REG_FIELD(WIZ_SERDES_RST, 24, 25);
  80 static const struct reg_field refclk_dig_sel_10g =
  81                                         REG_FIELD(WIZ_SERDES_RST, 24, 24);
  82 static const struct reg_field pma_cmn_refclk_int_mode =
  83                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
  84 static const struct reg_field pma_cmn_refclk1_int_mode =
  85                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
  86 static const struct reg_field pma_cmn_refclk_mode =
  87                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
  88 static const struct reg_field pma_cmn_refclk_dig_div =
  89                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
  90 static const struct reg_field pma_cmn_refclk1_dig_div =
  91                                         REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
  92
  93 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
  94         REG_FIELD(WIZ_LANECTL(0), 30, 31),
  95         REG_FIELD(WIZ_LANECTL(1), 30, 31),
  96         REG_FIELD(WIZ_LANECTL(2), 30, 31),
  97         REG_FIELD(WIZ_LANECTL(3), 30, 31),
  98 };
  99
 100 enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
 101
 102 static const struct reg_field p_align[WIZ_MAX_LANES] = {
 103         REG_FIELD(WIZ_LANECTL(0), 29, 29),
 104         REG_FIELD(WIZ_LANECTL(1), 29, 29),
 105         REG_FIELD(WIZ_LANECTL(2), 29, 29),
 106         REG_FIELD(WIZ_LANECTL(3), 29, 29),
 107 };
 108
 109 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
 110         REG_FIELD(WIZ_LANECTL(0), 28, 28),
 111         REG_FIELD(WIZ_LANECTL(1), 28, 28),
 112         REG_FIELD(WIZ_LANECTL(2), 28, 28),
 113         REG_FIELD(WIZ_LANECTL(3), 28, 28),
 114 };
 115
 116 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
 117         REG_FIELD(WIZ_LANECTL(0), 24, 25),
 118         REG_FIELD(WIZ_LANECTL(1), 24, 25),
 119         REG_FIELD(WIZ_LANECTL(2), 24, 25),
 120         REG_FIELD(WIZ_LANECTL(3), 24, 25),
 121 };
 122
 123 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
 124         REG_FIELD(WIZ_LANECTL(0), 22, 23),
 125         REG_FIELD(WIZ_LANECTL(1), 22, 23),
 126         REG_FIELD(WIZ_LANECTL(2), 22, 23),
 127         REG_FIELD(WIZ_LANECTL(3), 22, 23),
 128 };
 129
 130 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
 131         REG_FIELD(WIZ_LANEDIV(0), 16, 22),
 132         REG_FIELD(WIZ_LANEDIV(1), 16, 22),
 133         REG_FIELD(WIZ_LANEDIV(2), 16, 22),
 134         REG_FIELD(WIZ_LANEDIV(3), 16, 22),
 135 };
 136
 137 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
 138         REG_FIELD(WIZ_LANEDIV(0), 0, 8),
 139         REG_FIELD(WIZ_LANEDIV(1), 0, 8),
 140         REG_FIELD(WIZ_LANEDIV(2), 0, 8),
 141         REG_FIELD(WIZ_LANEDIV(3), 0, 8),
 142 };
 143
 144 struct wiz_clk_mux_sel {
 145         enum wiz_refclk_mux_sel mux_sel;
 146         u32                     table[WIZ_MAX_INPUT_CLOCKS];
 147         const char              *node_name;
 148         u32                     num_parents;
 149         u32                     parents[WIZ_MAX_INPUT_CLOCKS];
 150 };
 151
 152 struct wiz_clk_div_sel {
 153         enum wiz_refclk_div_sel div_sel;
 154         const char              *node_name;
 155 };
 156
 157 static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
 158         {
 159                 /*
 160                  * Mux value to be configured for each of the input clocks
 161                  * in the order populated in device tree
 162                  */
 163                 .num_parents = 2,
 164                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 165                 .mux_sel = PLL0_REFCLK,
 166                 .table = { 1, 0 },
 167                 .node_name = "pll0-refclk",
 168         },
 169         {
 170                 .num_parents = 2,
 171                 .parents = { WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK1 },
 172                 .mux_sel = PLL1_REFCLK,
 173                 .table = { 1, 0 },
 174                 .node_name = "pll1-refclk",
 175         },
 176         {
 177                 .num_parents = 4,
 178                 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK, WIZ_EXT_REFCLK1 },
 179                 .mux_sel = REFCLK_DIG,
 180                 .table = { 1, 3, 0, 2 },
 181                 .node_name = "refclk-dig",
 182         },
 183 };
 184
 185 static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
 186         {
 187                 /*
 188                  * Mux value to be configured for each of the input clocks
 189                  * in the order populated in device tree
 190                  */
 191                 .num_parents = 2,
 192                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 193                 .mux_sel = PLL0_REFCLK,
 194                 .table = { 1, 0 },
 195                 .node_name = "pll0-refclk",
 196         },
 197         {
 198                 .num_parents = 2,
 199                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 200                 .mux_sel = PLL1_REFCLK,
 201                 .table = { 1, 0 },
 202                 .node_name = "pll1-refclk",
 203         },
 204         {
 205                 .num_parents = 2,
 206                 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 207                 .mux_sel = REFCLK_DIG,
 208                 .table = { 1, 0 },
 209                 .node_name = "refclk-dig",
 210         },
 211 };
 212
 213 static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
 214         {
 215                 .num_parents = 3,
 216                 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 217                 .table = { 2, 3, 0 },
 218                 .node_name = "pll0-refclk",
 219         },
 220         {
 221                 .num_parents = 3,
 222                 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 223                 .table = { 2, 3, 0 },
 224                 .node_name = "pll1-refclk",
 225         },
 226         {
 227                 .num_parents = 3,
 228                 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 229                 .table = { 2, 3, 0 },
 230                 .node_name = "refclk-dig",
 231         },
 232 };
 233
 234 static struct wiz_clk_div_sel clk_div_sel[] = {
 235         {
 236                 .div_sel = CMN_REFCLK,
 237                 .node_name = "cmn-refclk-dig-div",
 238         },
 239         {
 240                 .div_sel = CMN_REFCLK1,
 241                 .node_name = "cmn-refclk1-dig-div",
 242         },
 243 };
 244
 245 enum wiz_type {
 246         J721E_WIZ_16G,
 247         J721E_WIZ_10G,
 248         AM64_WIZ_10G,
 249         J784S4_WIZ_10G,
 250 };
 251
 252 struct wiz_data {
 253         enum wiz_type type;
 254         const struct reg_field *pll0_refclk_mux_sel;
 255         const struct reg_field *pll1_refclk_mux_sel;
 256         const struct reg_field *refclk_dig_sel;
 257         const struct reg_field *pma_cmn_refclk1_dig_div;
 258         const struct reg_field *pma_cmn_refclk1_int_mode;
 259         const struct wiz_clk_mux_sel *clk_mux_sel;
 260         unsigned int clk_div_sel_num;
 261 };
 262
 263 static const struct wiz_data j721e_16g_data = {
 264         .type = J721E_WIZ_16G,
 265         .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
 266         .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
 267         .refclk_dig_sel = &refclk_dig_sel_16g,
 268         .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
 269         .clk_mux_sel = clk_mux_sel_16g,
 270         .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
 271 };
 272
 273 static const struct wiz_data j721e_10g_data = {
 274         .type = J721E_WIZ_10G,
 275         .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
 276         .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
 277         .refclk_dig_sel = &refclk_dig_sel_10g,
 278         .clk_mux_sel = clk_mux_sel_10g,
 279         .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
 280 };
 281
 282 static struct wiz_data am64_10g_data = {
 283         .type = AM64_WIZ_10G,
 284         .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
 285         .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
 286         .refclk_dig_sel = &refclk_dig_sel_10g,
 287         .clk_mux_sel = clk_mux_sel_10g,
 288         .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
 289 };
 290
 291 static struct wiz_data j784s4_wiz_10g = {
 292         .type = J784S4_WIZ_10G,
 293         .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
 294         .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
 295         .refclk_dig_sel = &refclk_dig_sel_16g,
 296         .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
 297         .clk_mux_sel = clk_mux_sel_10g_2_refclk,
 298         .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
 299 };
 300
 301 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN      100     /* ms */
 302 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX      1000
 303
 304 struct wiz {
 305         struct regmap           *regmap;
 306         enum wiz_type           type;
 307         struct wiz_clk_mux_sel  *clk_mux_sel;
 308         struct wiz_clk_div_sel  *clk_div_sel;
 309         unsigned int            clk_div_sel_num;
 310         struct regmap_field     *por_en;
 311         struct regmap_field     *phy_reset_n;
 312         struct regmap_field     *phy_en_refclk;
 313         struct regmap_field     *p_enable[WIZ_MAX_LANES];
 314         struct regmap_field     *p_align[WIZ_MAX_LANES];
 315         struct regmap_field     *p_raw_auto_start[WIZ_MAX_LANES];
 316         struct regmap_field     *p_standard_mode[WIZ_MAX_LANES];
 317         struct regmap_field     *p_mac_div_sel0[WIZ_MAX_LANES];
 318         struct regmap_field     *p_mac_div_sel1[WIZ_MAX_LANES];
 319         struct regmap_field     *p0_fullrt_div[WIZ_MAX_LANES];
 320         struct regmap_field     *pma_cmn_refclk_int_mode;
 321         struct regmap_field     *pma_cmn_refclk1_int_mode;
 322         struct regmap_field     *pma_cmn_refclk_mode;
 323         struct regmap_field     *pma_cmn_refclk_dig_div;
 324         struct regmap_field     *pma_cmn_refclk1_dig_div;
 325         struct regmap_field     *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
 326         struct regmap_field     *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
 327
 328         struct udevice          *dev;
 329         u32                     num_lanes;
 330         struct gpio_desc        *gpio_typec_dir;
 331         u32                     lane_phy_type[WIZ_MAX_LANES];
 332         struct clk              *input_clks[WIZ_MAX_INPUT_CLOCKS];
 333         unsigned int            id;
 334         const struct wiz_data   *data;
 335 };
 336
 337 struct wiz_div_clk {
 338         struct clk parent_clk;
 339         struct wiz *wiz;
 340 };
 341
 342 struct wiz_mux_clk {
 343         struct clk parent_clks[4];
 344         struct wiz *wiz;
 345 };
 346
 347 struct wiz_clk {
 348         struct wiz *wiz;
 349 };
 350
 351 struct wiz_reset {
 352         struct wiz *wiz;
 353 };
 354
 355 static ulong wiz_div_clk_get_rate(struct clk *clk)
 356 {
 357         struct udevice *dev = clk->dev;
 358         struct wiz_div_clk *priv = dev_get_priv(dev);
 359         struct wiz_clk_div_sel *data = dev_get_plat(dev);
 360         struct wiz *wiz = priv->wiz;
 361         ulong parent_rate = clk_get_rate(&priv->parent_clk);
 362         u32 val;
 363
 364         regmap_field_read(wiz->div_sel_field[data->div_sel], &val);
 365
 366         return parent_rate >> val;
 367 }
 368
 369 static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate)
 370 {
 371         struct udevice *dev = clk->dev;
 372         struct wiz_div_clk *priv = dev_get_priv(dev);
 373         struct wiz_clk_div_sel *data = dev_get_plat(dev);
 374         struct wiz *wiz = priv->wiz;
 375         ulong parent_rate = clk_get_rate(&priv->parent_clk);
 376         u32 div = parent_rate / rate;
 377
 378         div = __ffs(div);
 379         regmap_field_write(wiz->div_sel_field[data->div_sel], div);
 380
 381         return parent_rate >> div;
 382 }
 383
 384 const struct clk_ops wiz_div_clk_ops = {
 385         .get_rate = wiz_div_clk_get_rate,
 386         .set_rate = wiz_div_clk_set_rate,
 387 };
 388
 389 int wiz_div_clk_probe(struct udevice *dev)
 390 {
 391         struct wiz_div_clk *priv = dev_get_priv(dev);
 392         struct clk parent_clk;
 393         int rc;
 394
 395         rc = clk_get_by_index(dev, 0, &parent_clk);
 396         if (rc) {
 397                 dev_err(dev, "unable to get parent clock. ret %d\n", rc);
 398                 return rc;
 399         }
 400         priv->parent_clk = parent_clk;
 401         priv->wiz = dev_get_priv(dev->parent);
 402         return 0;
 403 }
 404
 405 U_BOOT_DRIVER(wiz_div_clk) = {
 406         .name           = "wiz_div_clk",
 407         .id             = UCLASS_CLK,
 408         .priv_auto      = sizeof(struct wiz_div_clk),
 409         .ops            = &wiz_div_clk_ops,
 410         .probe          = wiz_div_clk_probe,
 411 };
 412
 413 static int wiz_clk_mux_set_parent(struct clk *clk,  struct clk *parent)
 414 {
 415         struct udevice *dev = clk->dev;
 416         struct wiz_mux_clk *priv = dev_get_priv(dev);
 417         struct wiz_clk_mux_sel *data = dev_get_plat(dev);
 418         struct wiz *wiz = priv->wiz;
 419         int i;
 420
 421         for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++)
 422                 if (parent->dev == priv->parent_clks[i].dev)
 423                         break;
 424
 425         if (i == ARRAY_SIZE(priv->parent_clks))
 426                 return -EINVAL;
 427
 428         regmap_field_write(wiz->mux_sel_field[data->mux_sel], data->table[i]);
 429         return 0;
 430 }
 431
 432 static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 433 {
 434         struct udevice *dev = clk->dev;
 435         struct wiz_mux_clk *priv = dev_get_priv(dev);
 436         struct wiz *wiz = priv->wiz;
 437
 438         clk->id = wiz->id;
 439
 440         return 0;
 441 }
 442
 443 static const struct clk_ops wiz_clk_mux_ops = {
 444         .set_parent = wiz_clk_mux_set_parent,
 445         .of_xlate = wiz_clk_xlate,
 446 };
 447
 448 int wiz_mux_clk_probe(struct udevice *dev)
 449 {
 450         struct wiz_mux_clk *priv = dev_get_priv(dev);
 451         int rc;
 452         int i;
 453
 454         for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
 455                 rc = clk_get_by_index(dev, i, &priv->parent_clks[i]);
 456                 if (rc)
 457                         priv->parent_clks[i].dev = NULL;
 458         }
 459         priv->wiz = dev_get_priv(dev->parent);
 460         return 0;
 461 }
 462
 463 U_BOOT_DRIVER(wiz_mux_clk) = {
 464         .name           = "wiz_mux_clk",
 465         .id             = UCLASS_CLK,
 466         .priv_auto      = sizeof(struct wiz_mux_clk),
 467         .ops            = &wiz_clk_mux_ops,
 468         .probe          = wiz_mux_clk_probe,
 469 };
 470
 471 static int wiz_clk_set_parent(struct clk *clk,  struct clk *parent)
 472 {
 473         struct udevice *dev = clk->dev;
 474         struct wiz_clk *priv = dev_get_priv(dev);
 475         const struct wiz_clk_mux_sel *mux_sel;
 476         struct wiz *wiz = priv->wiz;
 477         int num_parents;
 478         int i, j, id;
 479
 480         id = clk->id >> 10;
 481
 482         /* set_parent is applicable only for MUX clocks */
 483         if (id > TI_WIZ_REFCLK_DIG)
 484                 return 0;
 485
 486         for (i = 0; i < WIZ_MAX_INPUT_CLOCKS; i++)
 487                 if (wiz->input_clks[i]->dev == parent->dev)
 488                         break;
 489
 490         if (i == WIZ_MAX_INPUT_CLOCKS)
 491                 return -EINVAL;
 492
 493         mux_sel = &wiz->clk_mux_sel[id];
 494         num_parents = mux_sel->num_parents;
 495         for (j = 0; j < num_parents; j++)
 496                 if (mux_sel->parents[j] == i)
 497                         break;
 498
 499         if (j == num_parents)
 500                 return -EINVAL;
 501
 502         regmap_field_write(wiz->mux_sel_field[id], mux_sel->table[j]);
 503
 504         return 0;
 505 }
 506
 507 static int wiz_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
 508 {
 509         struct udevice *dev = clk->dev;
 510         struct wiz_clk *priv = dev_get_priv(dev);
 511         struct wiz *wiz = priv->wiz;
 512
 513         clk->id = args->args[0] << 10 | wiz->id;
 514
 515         return 0;
 516 }
 517
 518 static const struct clk_ops wiz_clk_ops = {
 519         .set_parent = wiz_clk_set_parent,
 520         .of_xlate = wiz_clk_of_xlate,
 521 };
 522
 523 int wiz_clk_probe(struct udevice *dev)
 524 {
 525         struct wiz_clk *priv = dev_get_priv(dev);
 526
 527         priv->wiz = dev_get_priv(dev->parent);
 528
 529         return 0;
 530 }
 531
 532 U_BOOT_DRIVER(wiz_clk) = {
 533         .name           = "wiz_clk",
 534         .id             = UCLASS_CLK,
 535         .priv_auto      = sizeof(struct wiz_clk),
 536         .ops            = &wiz_clk_ops,
 537         .probe          = wiz_clk_probe,
 538 };
 539
 540 static int wiz_reset_request(struct reset_ctl *reset_ctl)
 541 {
 542         return 0;
 543 }
 544
 545 static int wiz_reset_free(struct reset_ctl *reset_ctl)
 546 {
 547         return 0;
 548 }
 549
 550 static int wiz_reset_assert(struct reset_ctl *reset_ctl)
 551 {
 552         struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
 553         struct wiz *wiz = priv->wiz;
 554         int ret;
 555         int id = reset_ctl->id;
 556
 557         if (id == 0) {
 558                 ret = regmap_field_write(wiz->phy_reset_n, false);
 559                 return ret;
 560         }
 561
 562         ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
 563         return ret;
 564 }
 565
 566 static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
 567 {
 568         if (wiz->type != AM64_WIZ_10G)
 569                 return 0;
 570
 571         if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
 572                 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
 573
 574         return 0;
 575 }
 576
 577 static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
 578 {
 579         struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
 580         struct wiz *wiz = priv->wiz;
 581         int ret;
 582         int id = reset_ctl->id;
 583
 584         ret = wiz_phy_fullrt_div(wiz, id - 1);
 585         if (ret)
 586                 return ret;
 587
 588         /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
 589         if (id == 0 && wiz->gpio_typec_dir) {
 590                 if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
 591                         regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
 592                                            WIZ_SERDES_TYPEC_LN10_SWAP,
 593                                            WIZ_SERDES_TYPEC_LN10_SWAP);
 594                 } else {
 595                         regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
 596                                            WIZ_SERDES_TYPEC_LN10_SWAP, 0);
 597                 }
 598         }
 599
 600         if (id == 0) {
 601                 ret = regmap_field_write(wiz->phy_reset_n, true);
 602                 return ret;
 603         }
 604
 605         if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
 606                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
 607         else
 608                 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
 609
 610         return ret;
 611 }
 612
 613 static struct reset_ops wiz_reset_ops = {
 614         .request = wiz_reset_request,
 615         .rfree = wiz_reset_free,
 616         .rst_assert = wiz_reset_assert,
 617         .rst_deassert = wiz_reset_deassert,
 618 };
 619
 620 int wiz_reset_probe(struct udevice *dev)
 621 {
 622         struct wiz_reset *priv = dev_get_priv(dev);
 623
 624         priv->wiz = dev_get_priv(dev->parent);
 625
 626         return 0;
 627 }
 628
 629 U_BOOT_DRIVER(wiz_reset) = {
 630         .name = "wiz-reset",
 631         .id = UCLASS_RESET,
 632         .probe = wiz_reset_probe,
 633         .ops = &wiz_reset_ops,
 634         .flags = DM_FLAG_LEAVE_PD_ON,
 635 };
 636
 637 static int wiz_reset(struct wiz *wiz)
 638 {
 639         int ret;
 640
 641         ret = regmap_field_write(wiz->por_en, 0x1);
 642         if (ret)
 643                 return ret;
 644
 645         mdelay(1);
 646
 647         ret = regmap_field_write(wiz->por_en, 0x0);
 648         if (ret)
 649                 return ret;
 650
 651         return 0;
 652 }
 653
 654 static int wiz_p_mac_div_sel(struct wiz *wiz)
 655 {
 656         u32 num_lanes = wiz->num_lanes;
 657         int ret;
 658         int i;
 659
 660         for (i = 0; i < num_lanes; i++) {
 661                 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
 662                         ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
 663                         if (ret)
 664                                 return ret;
 665
 666                         ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
 667                         if (ret)
 668                                 return ret;
 669                 }
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int wiz_mode_select(struct wiz *wiz)
 676 {
 677         u32 num_lanes = wiz->num_lanes;
 678         int ret;
 679         int i;
 680
 681         for (i = 0; i < num_lanes; i++) {
 682                 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
 683                         ret = regmap_field_write(wiz->p_standard_mode[i],
 684                                                  LANE_MODE_GEN2);
 685                         if (ret)
 686                                 return ret;
 687                 }
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
 694 {
 695         u32 num_lanes = wiz->num_lanes;
 696         int i;
 697         int ret;
 698
 699         for (i = 0; i < num_lanes; i++) {
 700                 ret = regmap_field_write(wiz->p_align[i], enable);
 701                 if (ret)
 702                         return ret;
 703
 704                 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
 705                 if (ret)
 706                         return ret;
 707         }
 708
 709         return 0;
 710 }
 711
 712 static int wiz_init(struct wiz *wiz)
 713 {
 714         struct udevice *dev = wiz->dev;
 715         int ret;
 716
 717         ret = wiz_reset(wiz);
 718         if (ret) {
 719                 dev_err(dev, "WIZ reset failed\n");
 720                 return ret;
 721         }
 722
 723         ret = wiz_mode_select(wiz);
 724         if (ret) {
 725                 dev_err(dev, "WIZ mode select failed\n");
 726                 return ret;
 727         }
 728
 729         ret = wiz_p_mac_div_sel(wiz);
 730         if (ret) {
 731                 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
 732                 return ret;
 733         }
 734
 735         ret = wiz_init_raw_interface(wiz, true);
 736         if (ret) {
 737                 dev_err(dev, "WIZ interface initialization failed\n");
 738                 return ret;
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int wiz_regfield_init(struct wiz *wiz)
 745 {
 746         struct regmap *regmap = wiz->regmap;
 747         int num_lanes = wiz->num_lanes;
 748         struct udevice *dev = wiz->dev;
 749         const struct wiz_data *data = wiz->data;
 750         int i;
 751
 752         wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
 753         if (IS_ERR(wiz->por_en)) {
 754                 dev_err(dev, "POR_EN reg field init failed\n");
 755                 return PTR_ERR(wiz->por_en);
 756         }
 757
 758         wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
 759                                                    phy_reset_n);
 760         if (IS_ERR(wiz->phy_reset_n)) {
 761                 dev_err(dev, "PHY_RESET_N reg field init failed\n");
 762                 return PTR_ERR(wiz->phy_reset_n);
 763         }
 764
 765         wiz->pma_cmn_refclk_int_mode =
 766                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
 767         if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
 768                 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
 769                 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
 770         }
 771
 772         if (data->pma_cmn_refclk1_int_mode) {
 773                 wiz->pma_cmn_refclk1_int_mode =
 774                         devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode);
 775                 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
 776                         dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
 777                         return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
 778                 }
 779         }
 780
 781         wiz->pma_cmn_refclk_mode =
 782                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
 783         if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
 784                 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
 785                 return PTR_ERR(wiz->pma_cmn_refclk_mode);
 786         }
 787
 788         wiz->div_sel_field[CMN_REFCLK] =
 789                 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
 790         if (IS_ERR(wiz->div_sel_field[CMN_REFCLK])) {
 791                 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
 792                 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
 793         }
 794
 795         if (data->pma_cmn_refclk1_dig_div) {
 796                 wiz->div_sel_field[CMN_REFCLK1] =
 797                         devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_dig_div);
 798                 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
 799                         dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
 800                         return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
 801                 }
 802         }
 803
 804         wiz->mux_sel_field[PLL0_REFCLK] =
 805                 devm_regmap_field_alloc(dev, regmap, *data->pll0_refclk_mux_sel);
 806         if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
 807                 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
 808                 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
 809         }
 810
 811         wiz->mux_sel_field[PLL1_REFCLK] =
 812                 devm_regmap_field_alloc(dev, regmap, *data->pll1_refclk_mux_sel);
 813         if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
 814                 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
 815                 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
 816         }
 817
 818         wiz->mux_sel_field[REFCLK_DIG] =
 819                 devm_regmap_field_alloc(dev, regmap, *data->refclk_dig_sel);
 820         if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
 821                 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
 822                 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
 823         }
 824
 825         for (i = 0; i < num_lanes; i++) {
 826                 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
 827                                                            p_enable[i]);
 828                 if (IS_ERR(wiz->p_enable[i])) {
 829                         dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 830                         return PTR_ERR(wiz->p_enable[i]);
 831                 }
 832
 833                 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
 834                                                           p_align[i]);
 835                 if (IS_ERR(wiz->p_align[i])) {
 836                         dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
 837                         return PTR_ERR(wiz->p_align[i]);
 838                 }
 839
 840                 wiz->p_raw_auto_start[i] =
 841                   devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
 842                 if (IS_ERR(wiz->p_raw_auto_start[i])) {
 843                         dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
 844                                 i);
 845                         return PTR_ERR(wiz->p_raw_auto_start[i]);
 846                 }
 847
 848                 wiz->p_standard_mode[i] =
 849                   devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
 850                 if (IS_ERR(wiz->p_standard_mode[i])) {
 851                         dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
 852                                 i);
 853                         return PTR_ERR(wiz->p_standard_mode[i]);
 854                 }
 855
 856                 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
 857                 if (IS_ERR(wiz->p0_fullrt_div[i])) {
 858                         dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
 859                         return PTR_ERR(wiz->p0_fullrt_div[i]);
 860                 }
 861
 862                 wiz->p_mac_div_sel0[i] =
 863                   devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
 864                 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
 865                         dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
 866                                 i);
 867                         return PTR_ERR(wiz->p_mac_div_sel0[i]);
 868                 }
 869
 870                 wiz->p_mac_div_sel1[i] =
 871                   devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
 872                 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
 873                         dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
 874                                 i);
 875                         return PTR_ERR(wiz->p_mac_div_sel1[i]);
 876                 }
 877         }
 878
 879         return 0;
 880 }
 881
 882 static int wiz_clock_init(struct wiz *wiz)
 883 {
 884         struct udevice *dev = wiz->dev;
 885         unsigned long rate;
 886         struct clk *clk;
 887         int ret;
 888
 889         clk = devm_clk_get(dev, "core_ref_clk");
 890         if (IS_ERR(clk)) {
 891                 dev_err(dev, "core_ref_clk clock not found\n");
 892                 ret = PTR_ERR(clk);
 893                 return ret;
 894         }
 895         wiz->input_clks[WIZ_CORE_REFCLK] = clk;
 896
 897         rate = clk_get_rate(clk);
 898         if (rate >= 100000000)
 899                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
 900         else
 901                 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
 902
 903         if (wiz->data->pma_cmn_refclk1_int_mode) {
 904                 clk = devm_clk_get(dev, "core_ref1_clk");
 905                 if (IS_ERR(clk)) {
 906                         dev_err(dev, "core_ref1_clk clock not found\n");
 907                         ret = PTR_ERR(clk);
 908                         return ret;
 909                 }
 910                 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
 911
 912                 rate = clk_get_rate(clk);
 913                 if (rate >= 100000000)
 914                         regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
 915                 else
 916                         regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
 917         } else {
 918                 /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
 919                 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
 920         }
 921
 922         clk = devm_clk_get(dev, "ext_ref_clk");
 923         if (IS_ERR(clk)) {
 924                 dev_err(dev, "ext_ref_clk clock not found\n");
 925                 ret = PTR_ERR(clk);
 926                 return ret;
 927         }
 928
 929         wiz->input_clks[WIZ_EXT_REFCLK] = clk;
 930         /* Initialize EXT_REFCLK1 to the same clock reference to maintain old DT compatibility */
 931         wiz->input_clks[WIZ_EXT_REFCLK1] = clk;
 932
 933         rate = clk_get_rate(clk);
 934         if (rate >= 100000000)
 935                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
 936         else
 937                 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
 938
 939         return 0;
 940 }
 941
 942 static ofnode get_child_by_name(struct udevice *dev, const char *name)
 943 {
 944         int l = strlen(name);
 945         ofnode node = dev_read_first_subnode(dev);
 946
 947         while (ofnode_valid(node)) {
 948                 const char *child_name = ofnode_get_name(node);
 949
 950                 if (!strncmp(child_name, name, l)) {
 951                         if (child_name[l] == '\0' || child_name[l] == '@')
 952                                 return node;
 953                 }
 954                 node = dev_read_next_subnode(node);
 955         }
 956         return node;
 957 }
 958
 959 static int j721e_wiz_bind_clocks(struct wiz *wiz)
 960 {
 961         struct udevice *dev = wiz->dev;
 962         struct driver *wiz_clk_drv;
 963         int i, rc;
 964
 965         wiz_clk_drv = lists_driver_lookup_name("wiz_clk");
 966         if (!wiz_clk_drv) {
 967                 dev_err(dev, "Cannot find driver 'wiz_clk'\n");
 968                 return -ENOENT;
 969         }
 970
 971         for (i = 0; i < WIZ_DIV_NUM_CLOCKS_10G; i++) {
 972                 rc = device_bind(dev, wiz_clk_drv, clk_div_sel[i].node_name,
 973                                  &clk_div_sel[i], dev_ofnode(dev), NULL);
 974                 if (rc) {
 975                         dev_err(dev, "cannot bind driver for clock %s\n",
 976                                 clk_div_sel[i].node_name);
 977                 }
 978         }
 979
 980         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
 981                 rc = device_bind(dev, wiz_clk_drv, clk_mux_sel_10g[i].node_name,
 982                                  &clk_mux_sel_10g[i], dev_ofnode(dev), NULL);
 983                 if (rc) {
 984                         dev_err(dev, "cannot bind driver for clock %s\n",
 985                                 clk_mux_sel_10g[i].node_name);
 986                 }
 987         }
 988
 989         return 0;
 990 }
 991
 992 static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
 993 {
 994         struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
 995         struct udevice *dev = wiz->dev;
 996         enum wiz_type type = wiz->type;
 997         struct driver *div_clk_drv;
 998         struct driver *mux_clk_drv;
 999         ofnode node;
1000         int i, rc;
1001
1002         if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G)
1003                 return j721e_wiz_bind_clocks(wiz);
1004
1005         div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
1006         if (!div_clk_drv) {
1007                 dev_err(dev, "Cannot find driver 'wiz_div_clk'\n");
1008                 return -ENOENT;
1009         }
1010
1011         mux_clk_drv = lists_driver_lookup_name("wiz_mux_clk");
1012         if (!mux_clk_drv) {
1013                 dev_err(dev, "Cannot find driver 'wiz_mux_clk'\n");
1014                 return -ENOENT;
1015         }
1016
1017         for (i = 0; i < wiz->clk_div_sel_num; i++) {
1018                 node = get_child_by_name(dev, clk_div_sel[i].node_name);
1019                 if (!ofnode_valid(node)) {
1020                         dev_err(dev, "cannot find node for clock %s\n",
1021                                 clk_div_sel[i].node_name);
1022                         continue;
1023                 }
1024                 rc = device_bind(dev, div_clk_drv, clk_div_sel[i].node_name,
1025                                  &clk_div_sel[i], node, NULL);
1026                 if (rc) {
1027                         dev_err(dev, "cannot bind driver for clock %s\n",
1028                                 clk_div_sel[i].node_name);
1029                 }
1030         }
1031
1032         for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1033                 node = get_child_by_name(dev, clk_mux_sel[i].node_name);
1034                 if (!ofnode_valid(node)) {
1035                         dev_err(dev, "cannot find node for clock %s\n",
1036                                 clk_mux_sel[i].node_name);
1037                         continue;
1038                 }
1039                 rc = device_bind(dev, mux_clk_drv, clk_mux_sel[i].node_name,
1040                                  &clk_mux_sel[i], node, NULL);
1041                 if (rc) {
1042                         dev_err(dev, "cannot bind driver for clock %s\n",
1043                                 clk_mux_sel[i].node_name);
1044                 }
1045         }
1046
1047         return 0;
1048 }
1049
1050 static int j721e_wiz_bind_reset(struct udevice *dev)
1051 {
1052         int rc;
1053         struct driver *drv;
1054
1055         drv = lists_driver_lookup_name("wiz-reset");
1056         if (!drv) {
1057                 dev_err(dev, "Cannot find driver 'wiz-reset'\n");
1058                 return -ENOENT;
1059         }
1060
1061         rc = device_bind(dev, drv, "wiz-reset", NULL, dev_ofnode(dev), NULL);
1062         if (rc) {
1063                 dev_err(dev, "cannot bind driver for wiz-reset\n");
1064                 return rc;
1065         }
1066
1067         return 0;
1068 }
1069
1070 static int j721e_wiz_bind(struct udevice *dev)
1071 {
1072         dm_scan_fdt_dev(dev);
1073
1074         return 0;
1075 }
1076
1077 static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
1078 {
1079         ofnode child, serdes;
1080
1081         serdes = get_child_by_name(dev, "serdes");
1082         if (!ofnode_valid(serdes)) {
1083                 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1084                 return -EINVAL;
1085         }
1086
1087         ofnode_for_each_subnode(child, serdes) {
1088                 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1089                 int ret, i;
1090
1091                 ret = ofnode_read_u32(child, "reg", &reg);
1092                 if (ret) {
1093                         dev_err(dev, "%s: Reading \"reg\" from failed: %d\n",
1094                                 __func__, ret);
1095                         return ret;
1096                 }
1097                 ofnode_read_u32(child, "cdns,num-lanes", &num_lanes);
1098                 ofnode_read_u32(child, "cdns,phy-type", &phy_type);
1099
1100                 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1101                         reg, reg + num_lanes - 1, phy_type);
1102
1103                 for (i = reg; i < reg + num_lanes; i++)
1104                         wiz->lane_phy_type[i] = phy_type;
1105         }
1106
1107         return 0;
1108 }
1109
1110 static int j721e_wiz_probe(struct udevice *dev)
1111 {
1112         struct wiz *wiz = dev_get_priv(dev);
1113         struct ofnode_phandle_args args;
1114         unsigned int val;
1115         int rc, i;
1116         ofnode node;
1117         struct regmap *regmap;
1118         u32 num_lanes;
1119
1120         node = get_child_by_name(dev, "serdes");
1121
1122         if (!ofnode_valid(node)) {
1123                 dev_err(dev, "Failed to get SERDES child DT node\n");
1124                 return -ENODEV;
1125         }
1126
1127         rc = regmap_init_mem(node, &regmap);
1128         if (rc)  {
1129                 dev_err(dev, "Failed to get memory resource\n");
1130                 return rc;
1131         }
1132         rc = dev_read_u32(dev, "num-lanes", &num_lanes);
1133         if (rc) {
1134                 dev_err(dev, "Failed to read num-lanes property\n");
1135                 goto err_addr_to_resource;
1136         }
1137
1138         if (num_lanes > WIZ_MAX_LANES) {
1139                 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1140                 goto err_addr_to_resource;
1141         }
1142
1143         wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1144                                                       GPIOD_IS_IN);
1145         if (IS_ERR(wiz->gpio_typec_dir)) {
1146                 rc = PTR_ERR(wiz->gpio_typec_dir);
1147                 dev_err(dev, "Failed to request typec-dir gpio: %d\n", rc);
1148                 goto err_addr_to_resource;
1149         }
1150
1151         rc = dev_read_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0, 0, &args);
1152         if (rc) {
1153                 dev_err(dev, "Failed to get power domain: %d\n", rc);
1154                 goto err_addr_to_resource;
1155         }
1156
1157         wiz->id = args.args[0];
1158         wiz->regmap = regmap;
1159         wiz->num_lanes = num_lanes;
1160         wiz->dev = dev;
1161         wiz->clk_div_sel = clk_div_sel;
1162
1163         wiz->data = (struct wiz_data *)dev_get_driver_data(dev);
1164         wiz->type = wiz->data->type;
1165
1166         wiz->clk_mux_sel = (struct wiz_clk_mux_sel *)wiz->data->clk_mux_sel;
1167         wiz->clk_div_sel_num = wiz->data->clk_div_sel_num;
1168
1169         rc = wiz_get_lane_phy_types(dev, wiz);
1170         if (rc) {
1171                 dev_err(dev, "Failed to get lane PHY types\n");
1172                 goto err_addr_to_resource;
1173         }
1174
1175         rc = wiz_regfield_init(wiz);
1176         if (rc) {
1177                 dev_err(dev, "Failed to initialize regfields\n");
1178                 goto err_addr_to_resource;
1179         }
1180
1181         for (i = 0; i < wiz->num_lanes; i++) {
1182                 regmap_field_read(wiz->p_enable[i], &val);
1183                 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1184                         dev_err(dev, "SERDES already configured\n");
1185                         rc = -EBUSY;
1186                         goto err_addr_to_resource;
1187                 }
1188         }
1189
1190         rc = j721e_wiz_bind_of_clocks(wiz);
1191         if (rc) {
1192                 dev_err(dev, "Failed to bind clocks\n");
1193                 goto err_addr_to_resource;
1194         }
1195
1196         rc = j721e_wiz_bind_reset(dev);
1197         if (rc) {
1198                 dev_err(dev, "Failed to bind reset\n");
1199                 goto err_addr_to_resource;
1200         }
1201
1202         rc = wiz_clock_init(wiz);
1203         if (rc) {
1204                 dev_warn(dev, "Failed to initialize clocks\n");
1205                 goto err_addr_to_resource;
1206         }
1207
1208         rc = wiz_init(wiz);
1209         if (rc) {
1210                 dev_err(dev, "WIZ initialization failed\n");
1211                 goto err_addr_to_resource;
1212         }
1213
1214         return 0;
1215
1216 err_addr_to_resource:
1217         free(regmap);
1218
1219         return rc;
1220 }
1221
1222 static int j721e_wiz_remove(struct udevice *dev)
1223 {
1224         struct wiz *wiz = dev_get_priv(dev);
1225
1226         if (wiz->regmap)
1227                 free(wiz->regmap);
1228
1229         return 0;
1230 }
1231
1232 static const struct udevice_id j721e_wiz_ids[] = {
1233         {
1234                 .compatible = "ti,j721e-wiz-16g", .data = (ulong)&j721e_16g_data,
1235         },
1236         {
1237                 .compatible = "ti,j721e-wiz-10g", .data = (ulong)&j721e_10g_data,
1238         },
1239         {
1240                 .compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
1241         },
1242         {
1243                 .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
1244         },
1245         {}
1246 };
1247
1248 U_BOOT_DRIVER(phy_j721e_wiz) = {
1249         .name           = "phy-j721e-wiz",
1250         .id             = UCLASS_NOP,
1251         .of_match       = j721e_wiz_ids,
1252         .bind           = j721e_wiz_bind,
1253         .probe          = j721e_wiz_probe,
1254         .remove         = j721e_wiz_remove,
1255         .priv_auto      = sizeof(struct wiz),
1256         .flags          = DM_FLAG_LEAVE_PD_ON,
1257 };