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dm: core: Create a new header file for 'compat' features
[thirdparty/u-boot.git] / drivers / pinctrl / meson / pinctrl-meson.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
4 */
5
6 #include <common.h>
7 #include <dm.h>
8 #include <malloc.h>
9 #include <dm/device-internal.h>
10 #include <dm/device_compat.h>
11 #include <dm/lists.h>
12 #include <dm/pinctrl.h>
13 #include <fdt_support.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/sizes.h>
17 #include <asm/gpio.h>
18
19 #include "pinctrl-meson.h"
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 static const char *meson_pinctrl_dummy_name = "_dummy";
24
25 static char pin_name[PINNAME_SIZE];
26
27 int meson_pinctrl_get_groups_count(struct udevice *dev)
28 {
29 struct meson_pinctrl *priv = dev_get_priv(dev);
30
31 return priv->data->num_groups;
32 }
33
34 const char *meson_pinctrl_get_group_name(struct udevice *dev,
35 unsigned int selector)
36 {
37 struct meson_pinctrl *priv = dev_get_priv(dev);
38
39 if (!priv->data->groups[selector].name)
40 return meson_pinctrl_dummy_name;
41
42 return priv->data->groups[selector].name;
43 }
44
45 int meson_pinctrl_get_pins_count(struct udevice *dev)
46 {
47 struct meson_pinctrl *priv = dev_get_priv(dev);
48
49 return priv->data->num_pins;
50 }
51
52 const char *meson_pinctrl_get_pin_name(struct udevice *dev,
53 unsigned int selector)
54 {
55 struct meson_pinctrl *priv = dev_get_priv(dev);
56
57 if (selector > priv->data->num_pins ||
58 selector > priv->data->funcs[0].num_groups)
59 snprintf(pin_name, PINNAME_SIZE, "Error");
60 else
61 snprintf(pin_name, PINNAME_SIZE, "%s",
62 priv->data->funcs[0].groups[selector]);
63
64 return pin_name;
65 }
66
67 int meson_pinmux_get_functions_count(struct udevice *dev)
68 {
69 struct meson_pinctrl *priv = dev_get_priv(dev);
70
71 return priv->data->num_funcs;
72 }
73
74 const char *meson_pinmux_get_function_name(struct udevice *dev,
75 unsigned int selector)
76 {
77 struct meson_pinctrl *priv = dev_get_priv(dev);
78
79 return priv->data->funcs[selector].name;
80 }
81
82 static int meson_gpio_calc_reg_and_bit(struct udevice *dev, unsigned int offset,
83 enum meson_reg_type reg_type,
84 unsigned int *reg, unsigned int *bit)
85 {
86 struct meson_pinctrl *priv = dev_get_priv(dev);
87 struct meson_bank *bank = NULL;
88 struct meson_reg_desc *desc;
89 unsigned int pin;
90 int i;
91
92 pin = priv->data->pin_base + offset;
93
94 for (i = 0; i < priv->data->num_banks; i++) {
95 if (pin >= priv->data->banks[i].first &&
96 pin <= priv->data->banks[i].last) {
97 bank = &priv->data->banks[i];
98 break;
99 }
100 }
101
102 if (!bank)
103 return -EINVAL;
104
105 desc = &bank->regs[reg_type];
106 *reg = desc->reg * 4;
107 *bit = desc->bit + pin - bank->first;
108
109 return 0;
110 }
111
112 int meson_gpio_get(struct udevice *dev, unsigned int offset)
113 {
114 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
115 unsigned int reg, bit;
116 int ret;
117
118 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, &reg,
119 &bit);
120 if (ret)
121 return ret;
122
123 return !!(readl(priv->reg_gpio + reg) & BIT(bit));
124 }
125
126 int meson_gpio_set(struct udevice *dev, unsigned int offset, int value)
127 {
128 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
129 unsigned int reg, bit;
130 int ret;
131
132 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
133 &bit);
134 if (ret)
135 return ret;
136
137 clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
138
139 return 0;
140 }
141
142 int meson_gpio_get_direction(struct udevice *dev, unsigned int offset)
143 {
144 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
145 unsigned int reg, bit, val;
146 int ret;
147
148 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
149 &bit);
150 if (ret)
151 return ret;
152
153 val = readl(priv->reg_gpio + reg);
154
155 return (val & BIT(bit)) ? GPIOF_INPUT : GPIOF_OUTPUT;
156 }
157
158 int meson_gpio_direction_input(struct udevice *dev, unsigned int offset)
159 {
160 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
161 unsigned int reg, bit;
162 int ret;
163
164 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
165 &bit);
166 if (ret)
167 return ret;
168
169 setbits_le32(priv->reg_gpio + reg, BIT(bit));
170
171 return 0;
172 }
173
174 int meson_gpio_direction_output(struct udevice *dev,
175 unsigned int offset, int value)
176 {
177 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
178 unsigned int reg, bit;
179 int ret;
180
181 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_DIR, &reg,
182 &bit);
183 if (ret)
184 return ret;
185
186 clrbits_le32(priv->reg_gpio + reg, BIT(bit));
187
188 ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, &reg,
189 &bit);
190 if (ret)
191 return ret;
192
193 clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), value ? BIT(bit) : 0);
194
195 return 0;
196 }
197
198 static int meson_pinconf_bias_set(struct udevice *dev, unsigned int pin,
199 unsigned int param)
200 {
201 struct meson_pinctrl *priv = dev_get_priv(dev);
202 unsigned int offset = pin - priv->data->pin_base;
203 unsigned int reg, bit;
204 int ret;
205
206 ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULLEN, &reg, &bit);
207 if (ret)
208 return ret;
209
210 if (param == PIN_CONFIG_BIAS_DISABLE) {
211 clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 0);
212 return 0;
213 }
214
215 /* othewise, enable the bias and select level */
216 clrsetbits_le32(priv->reg_pullen + reg, BIT(bit), 1);
217 ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_PULL, &reg, &bit);
218 if (ret)
219 return ret;
220
221 clrsetbits_le32(priv->reg_pull + reg, BIT(bit),
222 param == PIN_CONFIG_BIAS_PULL_UP);
223
224 return 0;
225 }
226
227 static int meson_pinconf_drive_strength_set(struct udevice *dev,
228 unsigned int pin,
229 unsigned int drive_strength_ua)
230 {
231 struct meson_pinctrl *priv = dev_get_priv(dev);
232 unsigned int offset = pin - priv->data->pin_base;
233 unsigned int reg, bit;
234 unsigned int ds_val;
235 int ret;
236
237 if (!priv->reg_ds) {
238 dev_err(dev, "drive-strength-microamp not supported\n");
239 return -ENOTSUPP;
240 }
241
242 ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_DS, &reg, &bit);
243 if (ret)
244 return ret;
245
246 bit = bit << 1;
247
248 if (drive_strength_ua <= 500) {
249 ds_val = MESON_PINCONF_DRV_500UA;
250 } else if (drive_strength_ua <= 2500) {
251 ds_val = MESON_PINCONF_DRV_2500UA;
252 } else if (drive_strength_ua <= 3000) {
253 ds_val = MESON_PINCONF_DRV_3000UA;
254 } else if (drive_strength_ua <= 4000) {
255 ds_val = MESON_PINCONF_DRV_4000UA;
256 } else {
257 dev_warn(dev,
258 "pin %u: invalid drive-strength-microamp : %d , default to 4mA\n",
259 pin, drive_strength_ua);
260 ds_val = MESON_PINCONF_DRV_4000UA;
261 }
262
263 clrsetbits_le32(priv->reg_ds + reg, 0x3 << bit, ds_val << bit);
264
265 return 0;
266 }
267
268 int meson_pinconf_set(struct udevice *dev, unsigned int pin,
269 unsigned int param, unsigned int arg)
270 {
271 int ret;
272
273 switch (param) {
274 case PIN_CONFIG_BIAS_DISABLE:
275 case PIN_CONFIG_BIAS_PULL_UP:
276 case PIN_CONFIG_BIAS_PULL_DOWN:
277 ret = meson_pinconf_bias_set(dev, pin, param);
278 break;
279 case PIN_CONFIG_DRIVE_STRENGTH_UA:
280 ret = meson_pinconf_drive_strength_set(dev, pin, arg);
281 break;
282 default:
283 dev_err(dev, "unsupported configuration parameter %u\n", param);
284 return -EINVAL;
285 }
286
287 return ret;
288 }
289
290 int meson_pinconf_group_set(struct udevice *dev,
291 unsigned int group_selector,
292 unsigned int param, unsigned int arg)
293 {
294 struct meson_pinctrl *priv = dev_get_priv(dev);
295 struct meson_pmx_group *grp = &priv->data->groups[group_selector];
296 int i, ret;
297
298 for (i = 0; i < grp->num_pins; i++) {
299 ret = meson_pinconf_set(dev, grp->pins[i], param, arg);
300 if (ret)
301 return ret;
302 }
303
304 return 0;
305 }
306
307 int meson_gpio_probe(struct udevice *dev)
308 {
309 struct meson_pinctrl *priv = dev_get_priv(dev->parent);
310 struct gpio_dev_priv *uc_priv;
311
312 uc_priv = dev_get_uclass_priv(dev);
313 uc_priv->bank_name = priv->data->name;
314 uc_priv->gpio_count = priv->data->num_pins;
315
316 return 0;
317 }
318
319 static fdt_addr_t parse_address(int offset, const char *name, int na, int ns)
320 {
321 int index, len = 0;
322 const fdt32_t *reg;
323
324 index = fdt_stringlist_search(gd->fdt_blob, offset, "reg-names", name);
325 if (index < 0)
326 return FDT_ADDR_T_NONE;
327
328 reg = fdt_getprop(gd->fdt_blob, offset, "reg", &len);
329 if (!reg || (len <= (index * sizeof(fdt32_t) * (na + ns))))
330 return FDT_ADDR_T_NONE;
331
332 reg += index * (na + ns);
333
334 return fdt_translate_address((void *)gd->fdt_blob, offset, reg);
335 }
336
337 int meson_pinctrl_probe(struct udevice *dev)
338 {
339 struct meson_pinctrl *priv = dev_get_priv(dev);
340 struct uclass_driver *drv;
341 struct udevice *gpio_dev;
342 fdt_addr_t addr;
343 int node, gpio = -1, len;
344 int na, ns;
345 char *name;
346
347 na = fdt_address_cells(gd->fdt_blob, dev_of_offset(dev->parent));
348 if (na < 1) {
349 debug("bad #address-cells\n");
350 return -EINVAL;
351 }
352
353 ns = fdt_size_cells(gd->fdt_blob, dev_of_offset(dev->parent));
354 if (ns < 1) {
355 debug("bad #size-cells\n");
356 return -EINVAL;
357 }
358
359 fdt_for_each_subnode(node, gd->fdt_blob, dev_of_offset(dev)) {
360 if (fdt_getprop(gd->fdt_blob, node, "gpio-controller", &len)) {
361 gpio = node;
362 break;
363 }
364 }
365
366 if (!gpio) {
367 debug("gpio node not found\n");
368 return -EINVAL;
369 }
370
371 addr = parse_address(gpio, "mux", na, ns);
372 if (addr == FDT_ADDR_T_NONE) {
373 debug("mux address not found\n");
374 return -EINVAL;
375 }
376 priv->reg_mux = (void __iomem *)addr;
377
378 addr = parse_address(gpio, "gpio", na, ns);
379 if (addr == FDT_ADDR_T_NONE) {
380 debug("gpio address not found\n");
381 return -EINVAL;
382 }
383 priv->reg_gpio = (void __iomem *)addr;
384
385 addr = parse_address(gpio, "pull", na, ns);
386 /* Use gpio region if pull one is not present */
387 if (addr == FDT_ADDR_T_NONE)
388 priv->reg_pull = priv->reg_gpio;
389 else
390 priv->reg_pull = (void __iomem *)addr;
391
392 addr = parse_address(gpio, "pull-enable", na, ns);
393 /* Use pull region if pull-enable one is not present */
394 if (addr == FDT_ADDR_T_NONE)
395 priv->reg_pullen = priv->reg_pull;
396 else
397 priv->reg_pullen = (void __iomem *)addr;
398
399 addr = parse_address(gpio, "ds", na, ns);
400 /* Drive strength region is optional */
401 if (addr == FDT_ADDR_T_NONE)
402 priv->reg_ds = NULL;
403 else
404 priv->reg_ds = (void __iomem *)addr;
405
406 priv->data = (struct meson_pinctrl_data *)dev_get_driver_data(dev);
407
408 /* Lookup GPIO driver */
409 drv = lists_uclass_lookup(UCLASS_GPIO);
410 if (!drv) {
411 puts("Cannot find GPIO driver\n");
412 return -ENOENT;
413 }
414
415 name = calloc(1, 32);
416 sprintf(name, "meson-gpio");
417
418 /* Create child device UCLASS_GPIO and bind it */
419 device_bind(dev, priv->data->gpio_driver, name, NULL, gpio, &gpio_dev);
420 dev_set_of_offset(gpio_dev, gpio);
421
422 return 0;
423 }