2 * Pinctrl driver for Microchip PIC32 SoCs
3 * Copyright (c) 2015 Microchip Technology Inc.
4 * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <dm/pinctrl.h>
13 #include <mach/pic32.h>
15 DECLARE_GLOBAL_DATA_PTR
;
17 /* PIC32 has 10 peripheral ports with 16 pins each.
18 * Ports are marked PORTA-PORTK or PORT0-PORT9.
29 PIC32_PORT_J
= 8, /* no PORT_I */
31 PIC32_PINS_PER_PORT
= 16,
34 #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
35 #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
37 /* pin configuration descriptor */
38 struct pic32_pin_config
{
39 u16 port
; /* port number */
40 u16 pin
; /* pin number in the port */
41 u32 config
; /* one of PIN_CONFIG_* */
43 #define PIN_CONFIG(_prt, _pin, _cfg) \
44 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
46 /* In PIC32 muxing is performed at pin-level through two
47 * different set of registers - one set for input functions,
48 * and other for output functions.
49 * Pin configuration is handled through port register.
51 /* Port control registers */
52 struct pic32_reg_port
{
53 struct pic32_reg_atomic ansel
;
54 struct pic32_reg_atomic tris
;
55 struct pic32_reg_atomic port
;
56 struct pic32_reg_atomic lat
;
57 struct pic32_reg_atomic odc
;
58 struct pic32_reg_atomic cnpu
;
59 struct pic32_reg_atomic cnpd
;
60 struct pic32_reg_atomic cncon
;
61 struct pic32_reg_atomic unused
[8];
64 /* Input function mux registers */
65 struct pic32_reg_in_mux
{
112 /* output mux register offset */
113 #define PPS_OUT(__port, __pin) \
114 (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
117 struct pic32_pinctrl_priv
{
118 struct pic32_reg_in_mux
*mux_in
; /* mux input function */
119 struct pic32_reg_port
*pinconf
; /* pin configuration*/
120 void __iomem
*mux_out
; /* mux output function */
136 static int pic32_pinconfig_one(struct pic32_pinctrl_priv
*priv
,
137 u32 port_nr
, u32 pin
, u32 param
)
139 struct pic32_reg_port
*port
;
141 port
= &priv
->pinconf
[port_nr
];
143 case PIN_CONFIG_PIC32_DIGITAL
:
144 writel(BIT(pin
), &port
->ansel
.clr
);
146 case PIN_CONFIG_PIC32_ANALOG
:
147 writel(BIT(pin
), &port
->ansel
.set
);
149 case PIN_CONFIG_INPUT_ENABLE
:
150 writel(BIT(pin
), &port
->tris
.set
);
152 case PIN_CONFIG_OUTPUT
:
153 writel(BIT(pin
), &port
->tris
.clr
);
155 case PIN_CONFIG_BIAS_PULL_UP
:
156 writel(BIT(pin
), &port
->cnpu
.set
);
158 case PIN_CONFIG_BIAS_PULL_DOWN
:
159 writel(BIT(pin
), &port
->cnpd
.set
);
161 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
162 writel(BIT(pin
), &port
->odc
.set
);
171 static int pic32_pinconfig_set(struct pic32_pinctrl_priv
*priv
,
172 const struct pic32_pin_config
*list
, int count
)
176 for (i
= 0 ; i
< count
; i
++)
177 pic32_pinconfig_one(priv
, list
[i
].port
,
178 list
[i
].pin
, list
[i
].config
);
183 static void pic32_eth_pin_config(struct udevice
*dev
)
185 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
186 const struct pic32_pin_config configs
[] = {
188 PIN_CONFIG(PIC32_PORT_D
, 11, PIN_CONFIG_PIC32_DIGITAL
),
189 PIN_CONFIG(PIC32_PORT_D
, 11, PIN_CONFIG_OUTPUT
),
191 PIN_CONFIG(PIC32_PORT_D
, 6, PIN_CONFIG_PIC32_DIGITAL
),
192 PIN_CONFIG(PIC32_PORT_D
, 6, PIN_CONFIG_OUTPUT
),
194 PIN_CONFIG(PIC32_PORT_H
, 13, PIN_CONFIG_PIC32_DIGITAL
),
195 PIN_CONFIG(PIC32_PORT_H
, 13, PIN_CONFIG_INPUT_ENABLE
),
197 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_PIC32_DIGITAL
),
198 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_INPUT_ENABLE
),
199 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_BIAS_PULL_DOWN
),
201 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_PIC32_DIGITAL
),
202 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_INPUT_ENABLE
),
203 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_BIAS_PULL_DOWN
),
205 PIN_CONFIG(PIC32_PORT_J
, 11, PIN_CONFIG_PIC32_DIGITAL
),
206 PIN_CONFIG(PIC32_PORT_J
, 11, PIN_CONFIG_INPUT_ENABLE
),
208 PIN_CONFIG(PIC32_PORT_J
, 9, PIN_CONFIG_PIC32_DIGITAL
),
209 PIN_CONFIG(PIC32_PORT_J
, 9, PIN_CONFIG_OUTPUT
),
211 PIN_CONFIG(PIC32_PORT_J
, 8, PIN_CONFIG_PIC32_DIGITAL
),
212 PIN_CONFIG(PIC32_PORT_J
, 8, PIN_CONFIG_OUTPUT
),
214 PIN_CONFIG(PIC32_PORT_J
, 1, PIN_CONFIG_PIC32_DIGITAL
),
215 PIN_CONFIG(PIC32_PORT_J
, 1, PIN_CONFIG_INPUT_ENABLE
),
217 PIN_CONFIG(PIC32_PORT_F
, 3, PIN_CONFIG_PIC32_DIGITAL
),
218 PIN_CONFIG(PIC32_PORT_F
, 3, PIN_CONFIG_INPUT_ENABLE
),
221 pic32_pinconfig_set(priv
, configs
, ARRAY_SIZE(configs
));
224 static int pic32_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
226 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
229 case PERIPH_ID_UART2
:
230 /* PPS for U2 RX/TX */
231 writel(0x02, priv
->mux_out
+ PPS_OUT(PIC32_PORT_G
, 9));
232 writel(0x05, &priv
->mux_in
->u2rx
); /* B0 */
233 /* set digital mode */
234 pic32_pinconfig_one(priv
, PIC32_PORT_G
, 9,
235 PIN_CONFIG_PIC32_DIGITAL
);
236 pic32_pinconfig_one(priv
, PIC32_PORT_B
, 0,
237 PIN_CONFIG_PIC32_DIGITAL
);
240 pic32_eth_pin_config(dev
);
243 debug("%s: unknown-unhandled case\n", __func__
);
250 static int pic32_pinctrl_get_periph_id(struct udevice
*dev
,
251 struct udevice
*periph
)
256 ret
= fdtdec_get_int_array(gd
->fdt_blob
, periph
->of_offset
,
257 "interrupts", cell
, ARRAY_SIZE(cell
));
261 /* interrupt number */
264 return PERIPH_ID_UART1
;
266 return PERIPH_ID_UART2
;
268 return PERIPH_ID_SPI1
;
270 return PERIPH_ID_SPI2
;
272 return PERIPH_ID_I2C1
;
274 return PERIPH_ID_I2C2
;
276 return PERIPH_ID_USB
;
278 return PERIPH_ID_SQI
;
280 return PERIPH_ID_SDHCI
;
282 return PERIPH_ID_ETH
;
290 static int pic32_pinctrl_set_state_simple(struct udevice
*dev
,
291 struct udevice
*periph
)
295 debug("%s: periph %s\n", __func__
, periph
->name
);
296 func
= pic32_pinctrl_get_periph_id(dev
, periph
);
299 return pic32_pinctrl_request(dev
, func
, 0);
302 static struct pinctrl_ops pic32_pinctrl_ops
= {
303 .set_state_simple
= pic32_pinctrl_set_state_simple
,
304 .request
= pic32_pinctrl_request
,
305 .get_periph_id
= pic32_pinctrl_get_periph_id
,
308 static int pic32_pinctrl_probe(struct udevice
*dev
)
310 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
311 struct fdt_resource res
;
312 void *fdt
= (void *)gd
->fdt_blob
;
313 int node
= dev
->of_offset
;
316 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
319 printf("pinctrl: resource \"ppsin\" not found\n");
322 priv
->mux_in
= ioremap(res
.start
, fdt_resource_size(&res
));
324 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
327 printf("pinctrl: resource \"ppsout\" not found\n");
330 priv
->mux_out
= ioremap(res
.start
, fdt_resource_size(&res
));
332 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
335 printf("pinctrl: resource \"port\" not found\n");
338 priv
->pinconf
= ioremap(res
.start
, fdt_resource_size(&res
));
343 static const struct udevice_id pic32_pinctrl_ids
[] = {
344 { .compatible
= "microchip,pic32mzda-pinctrl" },
348 U_BOOT_DRIVER(pinctrl_pic32
) = {
349 .name
= "pinctrl_pic32",
350 .id
= UCLASS_PINCTRL
,
351 .of_match
= pic32_pinctrl_ids
,
352 .ops
= &pic32_pinctrl_ops
,
353 .probe
= pic32_pinctrl_probe
,
354 .bind
= dm_scan_fdt_dev
,
355 .priv_auto_alloc_size
= sizeof(struct pic32_pinctrl_priv
),