2 * Pinctrl driver for Microchip PIC32 SoCs
3 * Copyright (c) 2015 Microchip Technology Inc.
4 * Written by Purna Chandra Mandal <purna.mandal@microchip.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <dm/pinctrl.h>
14 #include <mach/pic32.h>
16 DECLARE_GLOBAL_DATA_PTR
;
18 /* PIC32 has 10 peripheral ports with 16 pins each.
19 * Ports are marked PORTA-PORTK or PORT0-PORT9.
30 PIC32_PORT_J
= 8, /* no PORT_I */
32 PIC32_PINS_PER_PORT
= 16,
35 #define PIN_CONFIG_PIC32_DIGITAL (PIN_CONFIG_END + 1)
36 #define PIN_CONFIG_PIC32_ANALOG (PIN_CONFIG_END + 2)
38 /* pin configuration descriptor */
39 struct pic32_pin_config
{
40 u16 port
; /* port number */
41 u16 pin
; /* pin number in the port */
42 u32 config
; /* one of PIN_CONFIG_* */
44 #define PIN_CONFIG(_prt, _pin, _cfg) \
45 {.port = (_prt), .pin = (_pin), .config = (_cfg), }
47 /* In PIC32 muxing is performed at pin-level through two
48 * different set of registers - one set for input functions,
49 * and other for output functions.
50 * Pin configuration is handled through port register.
52 /* Port control registers */
53 struct pic32_reg_port
{
54 struct pic32_reg_atomic ansel
;
55 struct pic32_reg_atomic tris
;
56 struct pic32_reg_atomic port
;
57 struct pic32_reg_atomic lat
;
58 struct pic32_reg_atomic odc
;
59 struct pic32_reg_atomic cnpu
;
60 struct pic32_reg_atomic cnpd
;
61 struct pic32_reg_atomic cncon
;
62 struct pic32_reg_atomic unused
[8];
65 /* Input function mux registers */
66 struct pic32_reg_in_mux
{
113 /* output mux register offset */
114 #define PPS_OUT(__port, __pin) \
115 (((__port) * PIC32_PINS_PER_PORT + (__pin)) << 2)
118 struct pic32_pinctrl_priv
{
119 struct pic32_reg_in_mux
*mux_in
; /* mux input function */
120 struct pic32_reg_port
*pinconf
; /* pin configuration*/
121 void __iomem
*mux_out
; /* mux output function */
137 static int pic32_pinconfig_one(struct pic32_pinctrl_priv
*priv
,
138 u32 port_nr
, u32 pin
, u32 param
)
140 struct pic32_reg_port
*port
;
142 port
= &priv
->pinconf
[port_nr
];
144 case PIN_CONFIG_PIC32_DIGITAL
:
145 writel(BIT(pin
), &port
->ansel
.clr
);
147 case PIN_CONFIG_PIC32_ANALOG
:
148 writel(BIT(pin
), &port
->ansel
.set
);
150 case PIN_CONFIG_INPUT_ENABLE
:
151 writel(BIT(pin
), &port
->tris
.set
);
153 case PIN_CONFIG_OUTPUT
:
154 writel(BIT(pin
), &port
->tris
.clr
);
156 case PIN_CONFIG_BIAS_PULL_UP
:
157 writel(BIT(pin
), &port
->cnpu
.set
);
159 case PIN_CONFIG_BIAS_PULL_DOWN
:
160 writel(BIT(pin
), &port
->cnpd
.set
);
162 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
163 writel(BIT(pin
), &port
->odc
.set
);
172 static int pic32_pinconfig_set(struct pic32_pinctrl_priv
*priv
,
173 const struct pic32_pin_config
*list
, int count
)
177 for (i
= 0 ; i
< count
; i
++)
178 pic32_pinconfig_one(priv
, list
[i
].port
,
179 list
[i
].pin
, list
[i
].config
);
184 static void pic32_eth_pin_config(struct udevice
*dev
)
186 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
187 const struct pic32_pin_config configs
[] = {
189 PIN_CONFIG(PIC32_PORT_D
, 11, PIN_CONFIG_PIC32_DIGITAL
),
190 PIN_CONFIG(PIC32_PORT_D
, 11, PIN_CONFIG_OUTPUT
),
192 PIN_CONFIG(PIC32_PORT_D
, 6, PIN_CONFIG_PIC32_DIGITAL
),
193 PIN_CONFIG(PIC32_PORT_D
, 6, PIN_CONFIG_OUTPUT
),
195 PIN_CONFIG(PIC32_PORT_H
, 13, PIN_CONFIG_PIC32_DIGITAL
),
196 PIN_CONFIG(PIC32_PORT_H
, 13, PIN_CONFIG_INPUT_ENABLE
),
198 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_PIC32_DIGITAL
),
199 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_INPUT_ENABLE
),
200 PIN_CONFIG(PIC32_PORT_H
, 8, PIN_CONFIG_BIAS_PULL_DOWN
),
202 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_PIC32_DIGITAL
),
203 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_INPUT_ENABLE
),
204 PIN_CONFIG(PIC32_PORT_H
, 5, PIN_CONFIG_BIAS_PULL_DOWN
),
206 PIN_CONFIG(PIC32_PORT_J
, 11, PIN_CONFIG_PIC32_DIGITAL
),
207 PIN_CONFIG(PIC32_PORT_J
, 11, PIN_CONFIG_INPUT_ENABLE
),
209 PIN_CONFIG(PIC32_PORT_J
, 9, PIN_CONFIG_PIC32_DIGITAL
),
210 PIN_CONFIG(PIC32_PORT_J
, 9, PIN_CONFIG_OUTPUT
),
212 PIN_CONFIG(PIC32_PORT_J
, 8, PIN_CONFIG_PIC32_DIGITAL
),
213 PIN_CONFIG(PIC32_PORT_J
, 8, PIN_CONFIG_OUTPUT
),
215 PIN_CONFIG(PIC32_PORT_J
, 1, PIN_CONFIG_PIC32_DIGITAL
),
216 PIN_CONFIG(PIC32_PORT_J
, 1, PIN_CONFIG_INPUT_ENABLE
),
218 PIN_CONFIG(PIC32_PORT_F
, 3, PIN_CONFIG_PIC32_DIGITAL
),
219 PIN_CONFIG(PIC32_PORT_F
, 3, PIN_CONFIG_INPUT_ENABLE
),
222 pic32_pinconfig_set(priv
, configs
, ARRAY_SIZE(configs
));
225 static int pic32_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
227 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
230 case PERIPH_ID_UART2
:
231 /* PPS for U2 RX/TX */
232 writel(0x02, priv
->mux_out
+ PPS_OUT(PIC32_PORT_G
, 9));
233 writel(0x05, &priv
->mux_in
->u2rx
); /* B0 */
234 /* set digital mode */
235 pic32_pinconfig_one(priv
, PIC32_PORT_G
, 9,
236 PIN_CONFIG_PIC32_DIGITAL
);
237 pic32_pinconfig_one(priv
, PIC32_PORT_B
, 0,
238 PIN_CONFIG_PIC32_DIGITAL
);
241 pic32_eth_pin_config(dev
);
244 debug("%s: unknown-unhandled case\n", __func__
);
251 static int pic32_pinctrl_get_periph_id(struct udevice
*dev
,
252 struct udevice
*periph
)
257 ret
= fdtdec_get_int_array(gd
->fdt_blob
, periph
->of_offset
,
258 "interrupts", cell
, ARRAY_SIZE(cell
));
262 /* interrupt number */
265 return PERIPH_ID_UART1
;
267 return PERIPH_ID_UART2
;
269 return PERIPH_ID_SPI1
;
271 return PERIPH_ID_SPI2
;
273 return PERIPH_ID_I2C1
;
275 return PERIPH_ID_I2C2
;
277 return PERIPH_ID_USB
;
279 return PERIPH_ID_SQI
;
281 return PERIPH_ID_SDHCI
;
283 return PERIPH_ID_ETH
;
291 static int pic32_pinctrl_set_state_simple(struct udevice
*dev
,
292 struct udevice
*periph
)
296 debug("%s: periph %s\n", __func__
, periph
->name
);
297 func
= pic32_pinctrl_get_periph_id(dev
, periph
);
300 return pic32_pinctrl_request(dev
, func
, 0);
303 static struct pinctrl_ops pic32_pinctrl_ops
= {
304 .set_state_simple
= pic32_pinctrl_set_state_simple
,
305 .request
= pic32_pinctrl_request
,
306 .get_periph_id
= pic32_pinctrl_get_periph_id
,
309 static int pic32_pinctrl_probe(struct udevice
*dev
)
311 struct pic32_pinctrl_priv
*priv
= dev_get_priv(dev
);
312 struct fdt_resource res
;
313 void *fdt
= (void *)gd
->fdt_blob
;
314 int node
= dev
->of_offset
;
317 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
320 printf("pinctrl: resource \"ppsin\" not found\n");
323 priv
->mux_in
= ioremap(res
.start
, fdt_resource_size(&res
));
325 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
328 printf("pinctrl: resource \"ppsout\" not found\n");
331 priv
->mux_out
= ioremap(res
.start
, fdt_resource_size(&res
));
333 ret
= fdt_get_named_resource(fdt
, node
, "reg", "reg-names",
336 printf("pinctrl: resource \"port\" not found\n");
339 priv
->pinconf
= ioremap(res
.start
, fdt_resource_size(&res
));
344 static int pic32_pinctrl_bind(struct udevice
*dev
)
346 /* scan child GPIO banks */
347 return dm_scan_fdt_node(dev
, gd
->fdt_blob
, dev
->of_offset
, false);
350 static const struct udevice_id pic32_pinctrl_ids
[] = {
351 { .compatible
= "microchip,pic32mzda-pinctrl" },
355 U_BOOT_DRIVER(pinctrl_pic32
) = {
356 .name
= "pinctrl_pic32",
357 .id
= UCLASS_PINCTRL
,
358 .of_match
= pic32_pinctrl_ids
,
359 .ops
= &pic32_pinctrl_ops
,
360 .probe
= pic32_pinctrl_probe
,
361 .bind
= pic32_pinctrl_bind
,
362 .priv_auto_alloc_size
= sizeof(struct pic32_pinctrl_priv
),