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doc: rockchip: Adapt Pine64 Rock64 board instructions
[thirdparty/u-boot.git] / drivers / pinctrl / renesas / pfc-r8a77990.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R8A77990 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 *
7 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c
8 *
9 * R8A7796 processor support - PFC hardware block.
10 *
11 * Copyright (C) 2016-2017 Renesas Electronics Corp.
12 */
13
14 #include <common.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <dm/pinctrl.h>
18 #include <linux/kernel.h>
19
20 #include "sh_pfc.h"
21
22 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP | \
23 SH_PFC_PIN_CFG_PULL_DOWN)
24
25 #define CPU_ALL_PORT(fn, sfx) \
26 PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
35 PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
36 PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
38 PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
39 PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
40 PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
41 PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
42 PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
43 PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
44 PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
45 PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
46 /*
47 * F_() : just information
48 * FM() : macro for FN_xxx / xxx_MARK
49 */
50
51 /* GPSR0 */
52 #define GPSR0_17 F_(SDA4, IP7_27_24)
53 #define GPSR0_16 F_(SCL4, IP7_23_20)
54 #define GPSR0_15 F_(D15, IP7_19_16)
55 #define GPSR0_14 F_(D14, IP7_15_12)
56 #define GPSR0_13 F_(D13, IP7_11_8)
57 #define GPSR0_12 F_(D12, IP7_7_4)
58 #define GPSR0_11 F_(D11, IP7_3_0)
59 #define GPSR0_10 F_(D10, IP6_31_28)
60 #define GPSR0_9 F_(D9, IP6_27_24)
61 #define GPSR0_8 F_(D8, IP6_23_20)
62 #define GPSR0_7 F_(D7, IP6_19_16)
63 #define GPSR0_6 F_(D6, IP6_15_12)
64 #define GPSR0_5 F_(D5, IP6_11_8)
65 #define GPSR0_4 F_(D4, IP6_7_4)
66 #define GPSR0_3 F_(D3, IP6_3_0)
67 #define GPSR0_2 F_(D2, IP5_31_28)
68 #define GPSR0_1 F_(D1, IP5_27_24)
69 #define GPSR0_0 F_(D0, IP5_23_20)
70
71 /* GPSR1 */
72 #define GPSR1_22 F_(WE0_N, IP5_19_16)
73 #define GPSR1_21 F_(CS0_N, IP5_15_12)
74 #define GPSR1_20 FM(CLKOUT)
75 #define GPSR1_19 F_(A19, IP5_11_8)
76 #define GPSR1_18 F_(A18, IP5_7_4)
77 #define GPSR1_17 F_(A17, IP5_3_0)
78 #define GPSR1_16 F_(A16, IP4_31_28)
79 #define GPSR1_15 F_(A15, IP4_27_24)
80 #define GPSR1_14 F_(A14, IP4_23_20)
81 #define GPSR1_13 F_(A13, IP4_19_16)
82 #define GPSR1_12 F_(A12, IP4_15_12)
83 #define GPSR1_11 F_(A11, IP4_11_8)
84 #define GPSR1_10 F_(A10, IP4_7_4)
85 #define GPSR1_9 F_(A9, IP4_3_0)
86 #define GPSR1_8 F_(A8, IP3_31_28)
87 #define GPSR1_7 F_(A7, IP3_27_24)
88 #define GPSR1_6 F_(A6, IP3_23_20)
89 #define GPSR1_5 F_(A5, IP3_19_16)
90 #define GPSR1_4 F_(A4, IP3_15_12)
91 #define GPSR1_3 F_(A3, IP3_11_8)
92 #define GPSR1_2 F_(A2, IP3_7_4)
93 #define GPSR1_1 F_(A1, IP3_3_0)
94 #define GPSR1_0 F_(A0, IP2_31_28)
95
96 /* GPSR2 */
97 #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
98 #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
99 #define GPSR2_23 F_(RD_N, IP2_19_16)
100 #define GPSR2_22 F_(BS_N, IP2_15_12)
101 #define GPSR2_21 FM(AVB_PHY_INT)
102 #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
103 #define GPSR2_19 FM(AVB_RD3)
104 #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
105 #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
106 #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
107 #define GPSR2_15 FM(AVB_RXC)
108 #define GPSR2_14 FM(AVB_RX_CTL)
109 #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
110 #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
111 #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
112 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
113 #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
114 #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
115 #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
116 #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
117 #define GPSR2_5 FM(QSPI0_SSL)
118 #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
119 #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
120 #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
121 #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
122 #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
123
124 /* GPSR3 */
125 #define GPSR3_15 F_(SD1_WP, IP11_7_4)
126 #define GPSR3_14 F_(SD1_CD, IP11_3_0)
127 #define GPSR3_13 F_(SD0_WP, IP10_31_28)
128 #define GPSR3_12 F_(SD0_CD, IP10_27_24)
129 #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
130 #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
131 #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
132 #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
133 #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
134 #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
135 #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
136 #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
137 #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
138 #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
139 #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
140 #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
141
142 /* GPSR4 */
143 #define GPSR4_10 F_(SD3_DS, IP10_23_20)
144 #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
145 #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
146 #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
147 #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
148 #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
149 #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
150 #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
151 #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
152 #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
153 #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
154
155 /* GPSR5 */
156 #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
157 #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
158 #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
159 #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
160 #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
161 #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
162 #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
163 #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
164 #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
165 #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
166 #define GPSR5_9 F_(RX2_A, IP12_15_12)
167 #define GPSR5_8 F_(TX2_A, IP12_11_8)
168 #define GPSR5_7 F_(SCK2_A, IP12_7_4)
169 #define GPSR5_6 F_(TX1, IP12_3_0)
170 #define GPSR5_5 F_(RX1, IP11_31_28)
171 #define GPSR5_4 F_(RTS0_N_TANS_A, IP11_23_20)
172 #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
173 #define GPSR5_2 F_(TX0_A, IP11_15_12)
174 #define GPSR5_1 F_(RX0_A, IP11_11_8)
175 #define GPSR5_0 F_(SCK0_A, IP11_27_24)
176
177 /* GPSR6 */
178 #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
179 #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
180 #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
181 #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
182 #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
183 #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
184 #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
185 #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
186 #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
187 #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
188 #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
189 #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
190 #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
191 #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
192 #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
193 #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
194 #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
195 #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
196
197 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
198 #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
199 #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
200 #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
201 #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
202 #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
203 #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH_A) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE_A) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222 #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224 #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP3_15_12 FM(A4) FM(RTS4_N_TANS_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230
231 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
232 #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_TANS_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_TANS_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264
265 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
266 #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267 #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268 #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP11_23_20 FM(RTS0_N_TANS_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N_TANS) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298
299 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
300 #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310 #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311 #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312 #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332
333 #define PINMUX_GPSR \
334 \
335 \
336 \
337 \
338 \
339 \
340 \
341 GPSR2_25 \
342 GPSR2_24 \
343 GPSR2_23 \
344 GPSR1_22 GPSR2_22 \
345 GPSR1_21 GPSR2_21 \
346 GPSR1_20 GPSR2_20 \
347 GPSR1_19 GPSR2_19 GPSR5_19 \
348 GPSR1_18 GPSR2_18 GPSR5_18 \
349 GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
350 GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
351 GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
352 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
353 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
354 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
355 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
356 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
357 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
358 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
359 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
360 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
361 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
362 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
363 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
364 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
365 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
366 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
367
368 #define PINMUX_IPSR \
369 \
370 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
371 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
372 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
373 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
374 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
375 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
376 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
377 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
378 \
379 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
380 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
381 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
382 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
383 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
384 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
385 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
386 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
387 \
388 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
389 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
390 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
391 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
392 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
393 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
394 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
395 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
396 \
397 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
398 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
399 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
400 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
401 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
402 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
403 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
404 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
405
406 /* The bit numbering in MOD_SEL fields is reversed */
407 #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
408 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
409
410 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
411 #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
412 #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
413 #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
414 #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
415 #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
416 #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
417 #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
418 #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
419 #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
420 #define MOD_SEL0_16 FM(SEL_NDFC_0) FM(SEL_NDFC_1)
421 #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
422 #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
423 #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
424 #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
425 #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
426 #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
427 #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
428 #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
429 #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
430 #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
431 #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
432 #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
433
434 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
435 #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
436 #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
437 #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
438 #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
439 #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
440 #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
441 #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
442 #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
443 #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
444 #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
445 #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
446 #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
447 #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
448 #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
449 #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
450 #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
451 #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
452 #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
453 #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
454
455 #define PINMUX_MOD_SELS \
456 \
457 MOD_SEL1_31 \
458 MOD_SEL0_30_29 MOD_SEL1_30 \
459 MOD_SEL1_29 \
460 MOD_SEL0_28 MOD_SEL1_28 \
461 MOD_SEL0_27_26 \
462 MOD_SEL1_26 \
463 MOD_SEL0_25 MOD_SEL1_25 \
464 MOD_SEL0_24 MOD_SEL1_24_23_22 \
465 MOD_SEL0_23 \
466 MOD_SEL0_22 \
467 MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
468 MOD_SEL0_19_18_17 MOD_SEL1_18 \
469 MOD_SEL1_17 \
470 MOD_SEL0_16 MOD_SEL1_16 \
471 MOD_SEL0_15 MOD_SEL1_15 \
472 MOD_SEL0_14 MOD_SEL1_14_13 \
473 MOD_SEL0_13_12 \
474 MOD_SEL1_12_11 \
475 MOD_SEL0_11_10 \
476 MOD_SEL1_10_9 \
477 MOD_SEL0_9 \
478 MOD_SEL0_8 MOD_SEL1_8 \
479 MOD_SEL0_7 MOD_SEL1_7 \
480 MOD_SEL0_6_5 MOD_SEL1_6_5 \
481 MOD_SEL0_4 MOD_SEL1_4 \
482 MOD_SEL0_3 \
483 MOD_SEL0_2 \
484 MOD_SEL0_1_0
485
486 /*
487 * These pins are not able to be muxed but have other properties
488 * that can be set, such as pull-up/pull-down enable.
489 */
490 #define PINMUX_STATIC \
491 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
492 FM(AVB_TD3) \
493 FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
494 FM(ASEBRK) \
495 FM(MLB_REF)
496
497 enum {
498 PINMUX_RESERVED = 0,
499
500 PINMUX_DATA_BEGIN,
501 GP_ALL(DATA),
502 PINMUX_DATA_END,
503
504 #define F_(x, y)
505 #define FM(x) FN_##x,
506 PINMUX_FUNCTION_BEGIN,
507 GP_ALL(FN),
508 PINMUX_GPSR
509 PINMUX_IPSR
510 PINMUX_MOD_SELS
511 PINMUX_FUNCTION_END,
512 #undef F_
513 #undef FM
514
515 #define F_(x, y)
516 #define FM(x) x##_MARK,
517 PINMUX_MARK_BEGIN,
518 PINMUX_GPSR
519 PINMUX_IPSR
520 PINMUX_MOD_SELS
521 PINMUX_STATIC
522 PINMUX_MARK_END,
523 #undef F_
524 #undef FM
525 };
526
527 static const u16 pinmux_data[] = {
528 PINMUX_DATA_GP_ALL(),
529
530 PINMUX_SINGLE(CLKOUT),
531 PINMUX_SINGLE(AVB_PHY_INT),
532 PINMUX_SINGLE(AVB_RD3),
533 PINMUX_SINGLE(AVB_RXC),
534 PINMUX_SINGLE(AVB_RX_CTL),
535 PINMUX_SINGLE(QSPI0_SSL),
536
537 /* IPSR0 */
538 PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
539 PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
540
541 PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
542 PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
543
544 PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
545 PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
546
547 PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
548 PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
549
550 PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
551 PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
552
553 PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
554 PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
555 PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
556 PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
557
558 PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
559 PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
560 PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
561 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
562
563 PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
564 PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
565 PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
566 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
567
568 /* IPSR1 */
569 PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
570 PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
571 PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
572 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
573
574 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
575 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
576 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
577 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
578
579 PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
580 PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
581 PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
582 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
583
584 PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
585 PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
586 PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
587 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
588
589 PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
590 PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
591 PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
592 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
593
594 PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
595
596 PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
597
598 PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
599
600 /* IPSR2 */
601 PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
602
603 PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
604
605 PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
606
607 PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
608 PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
609 PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
610 PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
611 PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
612 PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
613
614 PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
615 PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
616 PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
617 PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
618 PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
619 PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
620 PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
621
622 PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
623 PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
624 PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH_A),
625 PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
626 PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
627 PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
628 PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
629
630 PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
631 PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
632 PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE_A),
633 PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
634 PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
635 PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
636
637 PINMUX_IPSR_GPSR(IP2_31_28, A0),
638 PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
639 PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
640 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
641 PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
642 PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
643 PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
644 PINMUX_IPSR_GPSR(IP2_31_28, IERX),
645 PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
646
647 /* IPSR3 */
648 PINMUX_IPSR_GPSR(IP3_3_0, A1),
649 PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
650 PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
651 PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
652 PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
653 PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
654 PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
655 PINMUX_IPSR_GPSR(IP3_3_0, IETX),
656 PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
657
658 PINMUX_IPSR_GPSR(IP3_7_4, A2),
659 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
660 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
661 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
662 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
663 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
664 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
665 PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
666
667 PINMUX_IPSR_GPSR(IP3_11_8, A3),
668 PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
669 PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
670 PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
671 PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
672 PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
673 PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
674 PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
675
676 PINMUX_IPSR_GPSR(IP3_15_12, A4),
677 PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_TANS_A, SEL_SCIF4_0),
678 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
679 PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
680 PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
681 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
682 PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
683
684 PINMUX_IPSR_GPSR(IP3_19_16, A5),
685 PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
686 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
687 PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
688 PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
689 PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
690 PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
691
692 PINMUX_IPSR_GPSR(IP3_23_20, A6),
693 PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
694 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
695 PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
696 PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
697
698 PINMUX_IPSR_GPSR(IP3_27_24, A7),
699 PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
700 PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
701 PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
702 PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
703
704 PINMUX_IPSR_GPSR(IP3_31_28, A8),
705 PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
706 PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
707 PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
708 PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
709 PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
710 PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
711 PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
712
713 /* IPSR4 */
714 PINMUX_IPSR_GPSR(IP4_3_0, A9),
715 PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
716 PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
717 PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
718 PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
719 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
720 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
721
722 PINMUX_IPSR_GPSR(IP4_7_4, A10),
723 PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
724 PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
725 PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
726 PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
727 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
728 PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
729 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
730
731 PINMUX_IPSR_GPSR(IP4_11_8, A11),
732 PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
733 PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
734 PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
735 PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
736 PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
737 PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
738
739 PINMUX_IPSR_GPSR(IP4_15_12, A12),
740 PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
741 PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
742 PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
743 PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
744 PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
745 PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
746
747 PINMUX_IPSR_GPSR(IP4_19_16, A13),
748 PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
749 PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
750 PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
751 PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
752 PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
753 PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
754
755 PINMUX_IPSR_GPSR(IP4_23_20, A14),
756 PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
757 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
758 PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
759 PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
760 PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
761 PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
762
763 PINMUX_IPSR_GPSR(IP4_27_24, A15),
764 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
765 PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
766 PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
767 PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
768 PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
769 PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
770
771 PINMUX_IPSR_GPSR(IP4_31_28, A16),
772 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
773 PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
774 PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
775 PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
776 PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
777 PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
778
779 /* IPSR5 */
780 PINMUX_IPSR_GPSR(IP5_3_0, A17),
781 PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
782 PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
783 PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
784 PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
785 PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
786
787 PINMUX_IPSR_GPSR(IP5_7_4, A18),
788 PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
789 PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
790 PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
791 PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
792 PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
793 PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
794
795 PINMUX_IPSR_GPSR(IP5_11_8, A19),
796 PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
797 PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
798 PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
799 PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
800 PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
801 PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
802
803 PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
804 PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
805 PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
806 PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
807 PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
808
809 PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
810 PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
811 PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
812 PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
813 PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
814
815 PINMUX_IPSR_GPSR(IP5_23_20, D0),
816 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
817 PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
818 PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
819 PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
820
821 PINMUX_IPSR_GPSR(IP5_27_24, D1),
822 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
823 PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
824 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
825 PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
826 PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
827 PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
828 PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
829
830 PINMUX_IPSR_GPSR(IP5_31_28, D2),
831 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
832 PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
833 PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
834 PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
835 PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
836 PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
837
838 /* IPSR6 */
839 PINMUX_IPSR_GPSR(IP6_3_0, D3),
840 PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
841 PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
842 PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
843 PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
844 PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
845 PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
846
847 PINMUX_IPSR_GPSR(IP6_7_4, D4),
848 PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
849 PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
850 PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
851 PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_TANS_A, SEL_SCIF3_0),
852 PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
853 PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
854
855 PINMUX_IPSR_GPSR(IP6_11_8, D5),
856 PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
858 PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
859 PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
860 PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
861
862 PINMUX_IPSR_GPSR(IP6_15_12, D6),
863 PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
864 PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
865 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
866 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
867 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
868
869 PINMUX_IPSR_GPSR(IP6_19_16, D7),
870 PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
871 PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
872 PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
873 PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
874 PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
875
876 PINMUX_IPSR_GPSR(IP6_23_20, D8),
877 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
878 PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
879 PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
880 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
881 PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
882 PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
883 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
884
885 PINMUX_IPSR_GPSR(IP6_27_24, D9),
886 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
887 PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
888 PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
889 PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
890 PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
891 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
892
893 PINMUX_IPSR_GPSR(IP6_31_28, D10),
894 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
895 PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
896 PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
897 PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
898 PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
899 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
900
901 /* IPSR7 */
902 PINMUX_IPSR_GPSR(IP7_3_0, D11),
903 PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
904 PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
905 PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
906 PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
907 PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
908 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
909
910 PINMUX_IPSR_GPSR(IP7_7_4, D12),
911 PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
912 PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
913 PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
914 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
915 PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
916
917 PINMUX_IPSR_GPSR(IP7_11_8, D13),
918 PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
919 PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
920 PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
921 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
922 PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
923 PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
924
925 PINMUX_IPSR_GPSR(IP7_15_12, D14),
926 PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
927 PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
928 PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
929 PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
930 PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
931
932 PINMUX_IPSR_GPSR(IP7_19_16, D15),
933 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
934 PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
935 PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
936 PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
937 PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
938
939 PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
940 PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
941 PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
942 PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
943 PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
944 PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
945
946 PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
947 PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
948 PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
949 PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
950 PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
951
952 PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
953 PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
954 PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
955 PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
956 PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
957 PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
958
959 /* IPSR8 */
960 PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
961 PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
962 PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
963 PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
964
965 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
966 PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
967 PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
968 PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
969
970 PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
971 PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
972 PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
973 PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
974 PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
975
976 PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
977 PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
978 PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
979 PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
980 PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
981
982 PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
983 PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
984 PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
985 PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
986 PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
987 PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
988
989 PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
990 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDFC_1),
991
992 PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
993 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDFC_1),
994
995 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
996 PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDFC_1),
997
998 /* IPSR9 */
999 PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
1000 PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDFC_1),
1001
1002 PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
1003 PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDFC_1),
1004
1005 PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
1006 PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDFC_1),
1007
1008 PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
1009 PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
1010
1011 PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
1012 PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
1013
1014 PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
1015 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
1016
1017 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
1018 PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
1019
1020 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
1021 PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
1022
1023 /* IPSR10 */
1024 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
1025 PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
1026
1027 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
1028 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
1029
1030 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
1031 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
1032
1033 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
1034 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
1035
1036 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
1037 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
1038
1039 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
1040 PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
1041
1042 PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
1043 PINMUX_IPSR_GPSR(IP10_27_24, NFALE_A),
1044 PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
1045 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1046 PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
1047 PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
1048 PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
1049 PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
1050
1051 PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
1052 PINMUX_IPSR_GPSR(IP10_31_28, NFRB_N_A),
1053 PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
1054 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1055 PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
1056 PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
1057 PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
1058 PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
1059
1060 /* IPSR11 */
1061 PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
1062 PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDFC_0),
1063 PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
1064 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1065 PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
1066
1067 PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
1068 PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDFC_0),
1069 PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
1070 PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
1071 PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
1072
1073 PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
1074 PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
1075 PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
1076 PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
1077 PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
1078
1079 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
1080 PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
1081 PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
1082 PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
1083 PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
1084
1085 PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
1086 PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDFC_0),
1087 PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
1088 PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
1089 PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
1090 PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
1091
1092 PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_TANS_A, SEL_SCIF0_0),
1093 PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDFC_0),
1094 PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
1095 PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
1096 PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
1097 PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
1098
1099 PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
1100 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
1101 PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
1102 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1103 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1104 PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
1105 PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
1106
1107 PINMUX_IPSR_GPSR(IP11_31_28, RX1),
1108 PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
1109 PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
1110 PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
1111
1112 /* IPSR12 */
1113 PINMUX_IPSR_GPSR(IP12_3_0, TX1),
1114 PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
1115 PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
1116 PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
1117
1118 PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
1119 PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
1120 PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
1121 PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
1122 PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
1123 PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
1124 PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
1125
1126 PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
1127 PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
1128 PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
1129 PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
1130 PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
1131 PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
1132
1133 PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
1134 PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
1135 PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
1136 PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
1137 PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
1138 PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
1139
1140 PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
1141 PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
1142
1143 PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
1144 PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
1145 PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
1146
1147 PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
1148 PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
1149 PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
1150
1151 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1152 PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
1153 PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
1154
1155 /* IPSR13 */
1156 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1157 PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
1158 PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
1159 PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
1160 PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
1161 PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
1162
1163 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1164 PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
1165 PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
1166 PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
1167 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
1168 PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
1169
1170 PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
1171 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
1172 PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
1173
1174 PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
1175 PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
1176 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
1177 PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
1178 PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
1179 PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
1180
1181 PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
1182 PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
1183 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
1184 PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
1185 PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
1186 PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
1187
1188 PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
1189 PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
1190 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
1191 PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
1192
1193 PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
1194
1195 PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
1196
1197 /* IPSR14 */
1198 PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
1199
1200 PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
1201 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
1202 PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
1203
1204 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
1205 PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
1206 PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
1207 PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
1208
1209 PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
1210 PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
1211
1212 PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
1213 PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
1214
1215 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
1216 PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
1217 PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
1218 PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
1219
1220 PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
1221 PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
1222 PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
1223
1224 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
1225 PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
1226 PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
1227 PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
1228 PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
1229
1230 /* IPSR15 */
1231 PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
1232 PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
1233 PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
1234 PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
1235
1236 PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
1237 PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
1238 PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
1239 PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
1240
1241 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
1242 PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
1243 PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
1244 PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
1245 PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
1246 PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
1247
1248 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
1249 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1250 PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
1251 PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
1252 PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
1253 PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
1254 PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
1255
1256 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
1257 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1258 PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
1259 PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
1260 PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
1261 PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
1262 PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
1263
1264 PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
1265
1266 PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
1267 PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
1268
1269 PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
1270 PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
1271
1272 /*
1273 * Static pins can not be muxed between different functions but
1274 * still need mark entries in the pinmux list. Add each static
1275 * pin to the list without an associated function. The sh-pfc
1276 * core will do the right thing and skip trying to mux the pin
1277 * while still applying configuration to it.
1278 */
1279 #define FM(x) PINMUX_DATA(x##_MARK, 0),
1280 PINMUX_STATIC
1281 #undef FM
1282 };
1283
1284 /*
1285 * R8A77990 has 7 banks with 32 GPIOs in each => 224 GPIOs.
1286 * Physical layout rows: A - AE, cols: 1 - 25.
1287 */
1288 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1289 #define PIN_NUMBER(r, c) (((r) - 'A') * 25 + (c) + 300)
1290 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1291 #define PIN_NONE U16_MAX
1292
1293 static const struct sh_pfc_pin pinmux_pins[] = {
1294 PINMUX_GPIO_GP_ALL(),
1295
1296 /*
1297 * Pins not associated with a GPIO port.
1298 *
1299 * The pin positions are different between different R8A77990
1300 * packages, all that is needed for the pfc driver is a unique
1301 * number for each pin. To this end use the pin layout from
1302 * R8A77990 to calculate a unique number for each pin.
1303 */
1304 SH_PFC_PIN_NAMED_CFG('F', 1, TRST_N, CFG_FLAGS),
1305 SH_PFC_PIN_NAMED_CFG('F', 3, TMS, CFG_FLAGS),
1306 SH_PFC_PIN_NAMED_CFG('F', 4, TCK, CFG_FLAGS),
1307 SH_PFC_PIN_NAMED_CFG('G', 2, TDI, CFG_FLAGS),
1308 SH_PFC_PIN_NAMED_CFG('G', 3, FSCLKST_N, CFG_FLAGS),
1309 SH_PFC_PIN_NAMED_CFG('H', 1, ASEBRK, CFG_FLAGS),
1310 SH_PFC_PIN_NAMED_CFG('N', 1, AVB_TXC, CFG_FLAGS),
1311 SH_PFC_PIN_NAMED_CFG('N', 2, AVB_TD0, CFG_FLAGS),
1312 SH_PFC_PIN_NAMED_CFG('N', 3, AVB_TD1, CFG_FLAGS),
1313 SH_PFC_PIN_NAMED_CFG('N', 5, AVB_TD2, CFG_FLAGS),
1314 SH_PFC_PIN_NAMED_CFG('N', 6, AVB_TD3, CFG_FLAGS),
1315 SH_PFC_PIN_NAMED_CFG('P', 3, AVB_TX_CTL, CFG_FLAGS),
1316 SH_PFC_PIN_NAMED_CFG('P', 4, AVB_MDIO, CFG_FLAGS),
1317 SH_PFC_PIN_NAMED_CFG('P', 5, AVB_MDC, CFG_FLAGS),
1318 SH_PFC_PIN_NAMED_CFG('T', 21, MLB_REF, CFG_FLAGS),
1319 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 3, PRESETOUT_N, CFG_FLAGS),
1320 };
1321
1322 /* - AUDIO CLOCK ------------------------------------------------------------ */
1323 static const unsigned int audio_clk_a_pins[] = {
1324 /* CLK A */
1325 RCAR_GP_PIN(6, 8),
1326 };
1327
1328 static const unsigned int audio_clk_a_mux[] = {
1329 AUDIO_CLKA_MARK,
1330 };
1331
1332 static const unsigned int audio_clk_b_a_pins[] = {
1333 /* CLK B_A */
1334 RCAR_GP_PIN(5, 7),
1335 };
1336
1337 static const unsigned int audio_clk_b_a_mux[] = {
1338 AUDIO_CLKB_A_MARK,
1339 };
1340
1341 static const unsigned int audio_clk_b_b_pins[] = {
1342 /* CLK B_B */
1343 RCAR_GP_PIN(6, 7),
1344 };
1345
1346 static const unsigned int audio_clk_b_b_mux[] = {
1347 AUDIO_CLKB_B_MARK,
1348 };
1349
1350 static const unsigned int audio_clk_b_c_pins[] = {
1351 /* CLK B_C */
1352 RCAR_GP_PIN(6, 13),
1353 };
1354
1355 static const unsigned int audio_clk_b_c_mux[] = {
1356 AUDIO_CLKB_C_MARK,
1357 };
1358
1359 static const unsigned int audio_clk_c_a_pins[] = {
1360 /* CLK C_A */
1361 RCAR_GP_PIN(5, 16),
1362 };
1363
1364 static const unsigned int audio_clk_c_a_mux[] = {
1365 AUDIO_CLKC_A_MARK,
1366 };
1367
1368 static const unsigned int audio_clk_c_b_pins[] = {
1369 /* CLK C_B */
1370 RCAR_GP_PIN(6, 3),
1371 };
1372
1373 static const unsigned int audio_clk_c_b_mux[] = {
1374 AUDIO_CLKC_B_MARK,
1375 };
1376
1377 static const unsigned int audio_clk_c_c_pins[] = {
1378 /* CLK C_C */
1379 RCAR_GP_PIN(6, 14),
1380 };
1381
1382 static const unsigned int audio_clk_c_c_mux[] = {
1383 AUDIO_CLKC_C_MARK,
1384 };
1385
1386 static const unsigned int audio_clkout_a_pins[] = {
1387 /* CLKOUT_A */
1388 RCAR_GP_PIN(5, 3),
1389 };
1390
1391 static const unsigned int audio_clkout_a_mux[] = {
1392 AUDIO_CLKOUT_A_MARK,
1393 };
1394
1395 static const unsigned int audio_clkout_b_pins[] = {
1396 /* CLKOUT_B */
1397 RCAR_GP_PIN(5, 13),
1398 };
1399
1400 static const unsigned int audio_clkout_b_mux[] = {
1401 AUDIO_CLKOUT_B_MARK,
1402 };
1403
1404 static const unsigned int audio_clkout1_a_pins[] = {
1405 /* CLKOUT1_A */
1406 RCAR_GP_PIN(5, 4),
1407 };
1408
1409 static const unsigned int audio_clkout1_a_mux[] = {
1410 AUDIO_CLKOUT1_A_MARK,
1411 };
1412
1413 static const unsigned int audio_clkout1_b_pins[] = {
1414 /* CLKOUT1_B */
1415 RCAR_GP_PIN(5, 5),
1416 };
1417
1418 static const unsigned int audio_clkout1_b_mux[] = {
1419 AUDIO_CLKOUT1_B_MARK,
1420 };
1421
1422 static const unsigned int audio_clkout1_c_pins[] = {
1423 /* CLKOUT1_C */
1424 RCAR_GP_PIN(6, 7),
1425 };
1426
1427 static const unsigned int audio_clkout1_c_mux[] = {
1428 AUDIO_CLKOUT1_C_MARK,
1429 };
1430
1431 static const unsigned int audio_clkout2_a_pins[] = {
1432 /* CLKOUT2_A */
1433 RCAR_GP_PIN(5, 8),
1434 };
1435
1436 static const unsigned int audio_clkout2_a_mux[] = {
1437 AUDIO_CLKOUT2_A_MARK,
1438 };
1439
1440 static const unsigned int audio_clkout2_b_pins[] = {
1441 /* CLKOUT2_B */
1442 RCAR_GP_PIN(6, 4),
1443 };
1444
1445 static const unsigned int audio_clkout2_b_mux[] = {
1446 AUDIO_CLKOUT2_B_MARK,
1447 };
1448
1449 static const unsigned int audio_clkout2_c_pins[] = {
1450 /* CLKOUT2_C */
1451 RCAR_GP_PIN(6, 15),
1452 };
1453
1454 static const unsigned int audio_clkout2_c_mux[] = {
1455 AUDIO_CLKOUT2_C_MARK,
1456 };
1457
1458 static const unsigned int audio_clkout3_a_pins[] = {
1459 /* CLKOUT3_A */
1460 RCAR_GP_PIN(5, 9),
1461 };
1462
1463 static const unsigned int audio_clkout3_a_mux[] = {
1464 AUDIO_CLKOUT3_A_MARK,
1465 };
1466
1467 static const unsigned int audio_clkout3_b_pins[] = {
1468 /* CLKOUT3_B */
1469 RCAR_GP_PIN(5, 6),
1470 };
1471
1472 static const unsigned int audio_clkout3_b_mux[] = {
1473 AUDIO_CLKOUT3_B_MARK,
1474 };
1475
1476 static const unsigned int audio_clkout3_c_pins[] = {
1477 /* CLKOUT3_C */
1478 RCAR_GP_PIN(6, 16),
1479 };
1480
1481 static const unsigned int audio_clkout3_c_mux[] = {
1482 AUDIO_CLKOUT3_C_MARK,
1483 };
1484
1485 /* - EtherAVB --------------------------------------------------------------- */
1486 static const unsigned int avb_link_pins[] = {
1487 /* AVB_LINK */
1488 RCAR_GP_PIN(2, 23),
1489 };
1490
1491 static const unsigned int avb_link_mux[] = {
1492 AVB_LINK_MARK,
1493 };
1494
1495 static const unsigned int avb_magic_pins[] = {
1496 /* AVB_MAGIC */
1497 RCAR_GP_PIN(2, 22),
1498 };
1499
1500 static const unsigned int avb_magic_mux[] = {
1501 AVB_MAGIC_MARK,
1502 };
1503
1504 static const unsigned int avb_phy_int_pins[] = {
1505 /* AVB_PHY_INT */
1506 RCAR_GP_PIN(2, 21),
1507 };
1508
1509 static const unsigned int avb_phy_int_mux[] = {
1510 AVB_PHY_INT_MARK,
1511 };
1512
1513 static const unsigned int avb_mii_pins[] = {
1514 /*
1515 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1516 * AVB_RD1, AVB_RD2, AVB_RD3,
1517 * AVB_TXCREFCLK
1518 */
1519 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1520 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1521 RCAR_GP_PIN(2, 20),
1522 };
1523
1524 static const unsigned int avb_mii_mux[] = {
1525 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1526 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1527 AVB_TXCREFCLK_MARK,
1528 };
1529
1530 static const unsigned int avb_avtp_pps_pins[] = {
1531 /* AVB_AVTP_PPS */
1532 RCAR_GP_PIN(1, 2),
1533 };
1534
1535 static const unsigned int avb_avtp_pps_mux[] = {
1536 AVB_AVTP_PPS_MARK,
1537 };
1538
1539 static const unsigned int avb_avtp_match_a_pins[] = {
1540 /* AVB_AVTP_MATCH_A */
1541 RCAR_GP_PIN(2, 24),
1542 };
1543
1544 static const unsigned int avb_avtp_match_a_mux[] = {
1545 AVB_AVTP_MATCH_A_MARK,
1546 };
1547
1548 static const unsigned int avb_avtp_capture_a_pins[] = {
1549 /* AVB_AVTP_CAPTURE_A */
1550 RCAR_GP_PIN(2, 25),
1551 };
1552
1553 static const unsigned int avb_avtp_capture_a_mux[] = {
1554 AVB_AVTP_CAPTURE_A_MARK,
1555 };
1556
1557 /* - CAN ------------------------------------------------------------------ */
1558 static const unsigned int can0_data_pins[] = {
1559 /* TX, RX */
1560 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1561 };
1562
1563 static const unsigned int can0_data_mux[] = {
1564 CAN0_TX_MARK, CAN0_RX_MARK,
1565 };
1566
1567 static const unsigned int can1_data_pins[] = {
1568 /* TX, RX */
1569 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1570 };
1571
1572 static const unsigned int can1_data_mux[] = {
1573 CAN1_TX_MARK, CAN1_RX_MARK,
1574 };
1575
1576 /* - CAN Clock -------------------------------------------------------------- */
1577 static const unsigned int can_clk_pins[] = {
1578 /* CLK */
1579 RCAR_GP_PIN(0, 14),
1580 };
1581
1582 static const unsigned int can_clk_mux[] = {
1583 CAN_CLK_MARK,
1584 };
1585
1586 /* - CAN FD --------------------------------------------------------------- */
1587 static const unsigned int canfd0_data_pins[] = {
1588 /* TX, RX */
1589 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1590 };
1591
1592 static const unsigned int canfd0_data_mux[] = {
1593 CANFD0_TX_MARK, CANFD0_RX_MARK,
1594 };
1595
1596 static const unsigned int canfd1_data_pins[] = {
1597 /* TX, RX */
1598 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1599 };
1600
1601 static const unsigned int canfd1_data_mux[] = {
1602 CANFD1_TX_MARK, CANFD1_RX_MARK,
1603 };
1604
1605 /* - DRIF0 --------------------------------------------------------------- */
1606 static const unsigned int drif0_ctrl_a_pins[] = {
1607 /* CLK, SYNC */
1608 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1609 };
1610
1611 static const unsigned int drif0_ctrl_a_mux[] = {
1612 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1613 };
1614
1615 static const unsigned int drif0_data0_a_pins[] = {
1616 /* D0 */
1617 RCAR_GP_PIN(5, 17),
1618 };
1619
1620 static const unsigned int drif0_data0_a_mux[] = {
1621 RIF0_D0_A_MARK,
1622 };
1623
1624 static const unsigned int drif0_data1_a_pins[] = {
1625 /* D1 */
1626 RCAR_GP_PIN(5, 18),
1627 };
1628
1629 static const unsigned int drif0_data1_a_mux[] = {
1630 RIF0_D1_A_MARK,
1631 };
1632
1633 static const unsigned int drif0_ctrl_b_pins[] = {
1634 /* CLK, SYNC */
1635 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1636 };
1637
1638 static const unsigned int drif0_ctrl_b_mux[] = {
1639 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1640 };
1641
1642 static const unsigned int drif0_data0_b_pins[] = {
1643 /* D0 */
1644 RCAR_GP_PIN(3, 13),
1645 };
1646
1647 static const unsigned int drif0_data0_b_mux[] = {
1648 RIF0_D0_B_MARK,
1649 };
1650
1651 static const unsigned int drif0_data1_b_pins[] = {
1652 /* D1 */
1653 RCAR_GP_PIN(3, 14),
1654 };
1655
1656 static const unsigned int drif0_data1_b_mux[] = {
1657 RIF0_D1_B_MARK,
1658 };
1659
1660 /* - DRIF1 --------------------------------------------------------------- */
1661 static const unsigned int drif1_ctrl_pins[] = {
1662 /* CLK, SYNC */
1663 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1664 };
1665
1666 static const unsigned int drif1_ctrl_mux[] = {
1667 RIF1_CLK_MARK, RIF1_SYNC_MARK,
1668 };
1669
1670 static const unsigned int drif1_data0_pins[] = {
1671 /* D0 */
1672 RCAR_GP_PIN(5, 2),
1673 };
1674
1675 static const unsigned int drif1_data0_mux[] = {
1676 RIF1_D0_MARK,
1677 };
1678
1679 static const unsigned int drif1_data1_pins[] = {
1680 /* D1 */
1681 RCAR_GP_PIN(5, 3),
1682 };
1683
1684 static const unsigned int drif1_data1_mux[] = {
1685 RIF1_D1_MARK,
1686 };
1687
1688 /* - DRIF2 --------------------------------------------------------------- */
1689 static const unsigned int drif2_ctrl_a_pins[] = {
1690 /* CLK, SYNC */
1691 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1692 };
1693
1694 static const unsigned int drif2_ctrl_a_mux[] = {
1695 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1696 };
1697
1698 static const unsigned int drif2_data0_a_pins[] = {
1699 /* D0 */
1700 RCAR_GP_PIN(2, 8),
1701 };
1702
1703 static const unsigned int drif2_data0_a_mux[] = {
1704 RIF2_D0_A_MARK,
1705 };
1706
1707 static const unsigned int drif2_data1_a_pins[] = {
1708 /* D1 */
1709 RCAR_GP_PIN(2, 9),
1710 };
1711
1712 static const unsigned int drif2_data1_a_mux[] = {
1713 RIF2_D1_A_MARK,
1714 };
1715
1716 static const unsigned int drif2_ctrl_b_pins[] = {
1717 /* CLK, SYNC */
1718 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1719 };
1720
1721 static const unsigned int drif2_ctrl_b_mux[] = {
1722 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1723 };
1724
1725 static const unsigned int drif2_data0_b_pins[] = {
1726 /* D0 */
1727 RCAR_GP_PIN(1, 6),
1728 };
1729
1730 static const unsigned int drif2_data0_b_mux[] = {
1731 RIF2_D0_B_MARK,
1732 };
1733
1734 static const unsigned int drif2_data1_b_pins[] = {
1735 /* D1 */
1736 RCAR_GP_PIN(1, 7),
1737 };
1738
1739 static const unsigned int drif2_data1_b_mux[] = {
1740 RIF2_D1_B_MARK,
1741 };
1742
1743 /* - DRIF3 --------------------------------------------------------------- */
1744 static const unsigned int drif3_ctrl_a_pins[] = {
1745 /* CLK, SYNC */
1746 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1747 };
1748
1749 static const unsigned int drif3_ctrl_a_mux[] = {
1750 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1751 };
1752
1753 static const unsigned int drif3_data0_a_pins[] = {
1754 /* D0 */
1755 RCAR_GP_PIN(2, 12),
1756 };
1757
1758 static const unsigned int drif3_data0_a_mux[] = {
1759 RIF3_D0_A_MARK,
1760 };
1761
1762 static const unsigned int drif3_data1_a_pins[] = {
1763 /* D1 */
1764 RCAR_GP_PIN(2, 13),
1765 };
1766
1767 static const unsigned int drif3_data1_a_mux[] = {
1768 RIF3_D1_A_MARK,
1769 };
1770
1771 static const unsigned int drif3_ctrl_b_pins[] = {
1772 /* CLK, SYNC */
1773 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1774 };
1775
1776 static const unsigned int drif3_ctrl_b_mux[] = {
1777 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1778 };
1779
1780 static const unsigned int drif3_data0_b_pins[] = {
1781 /* D0 */
1782 RCAR_GP_PIN(0, 10),
1783 };
1784
1785 static const unsigned int drif3_data0_b_mux[] = {
1786 RIF3_D0_B_MARK,
1787 };
1788
1789 static const unsigned int drif3_data1_b_pins[] = {
1790 /* D1 */
1791 RCAR_GP_PIN(0, 11),
1792 };
1793
1794 static const unsigned int drif3_data1_b_mux[] = {
1795 RIF3_D1_B_MARK,
1796 };
1797
1798 /* - DU --------------------------------------------------------------------- */
1799 static const unsigned int du_rgb666_pins[] = {
1800 /* R[7:2], G[7:2], B[7:2] */
1801 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1802 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1803 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1804 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1805 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1806 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1807 };
1808 static const unsigned int du_rgb666_mux[] = {
1809 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1810 DU_DR3_MARK, DU_DR2_MARK,
1811 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1812 DU_DG3_MARK, DU_DG2_MARK,
1813 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1814 DU_DB3_MARK, DU_DB2_MARK,
1815 };
1816 static const unsigned int du_rgb888_pins[] = {
1817 /* R[7:0], G[7:0], B[7:0] */
1818 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
1819 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
1820 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1821 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1822 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1823 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1824 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1825 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1826 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1827 };
1828 static const unsigned int du_rgb888_mux[] = {
1829 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1830 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1831 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1832 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1833 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1834 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1835 };
1836 static const unsigned int du_clk_in_0_pins[] = {
1837 /* CLKIN0 */
1838 RCAR_GP_PIN(0, 16),
1839 };
1840 static const unsigned int du_clk_in_0_mux[] = {
1841 DU_DOTCLKIN0_MARK
1842 };
1843 static const unsigned int du_clk_in_1_pins[] = {
1844 /* CLKIN1 */
1845 RCAR_GP_PIN(1, 1),
1846 };
1847 static const unsigned int du_clk_in_1_mux[] = {
1848 DU_DOTCLKIN1_MARK
1849 };
1850 static const unsigned int du_clk_out_0_pins[] = {
1851 /* CLKOUT */
1852 RCAR_GP_PIN(1, 3),
1853 };
1854 static const unsigned int du_clk_out_0_mux[] = {
1855 DU_DOTCLKOUT0_MARK
1856 };
1857 static const unsigned int du_sync_pins[] = {
1858 /* VSYNC, HSYNC */
1859 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1860 };
1861 static const unsigned int du_sync_mux[] = {
1862 DU_VSYNC_MARK, DU_HSYNC_MARK
1863 };
1864 static const unsigned int du_disp_cde_pins[] = {
1865 /* DISP_CDE */
1866 RCAR_GP_PIN(1, 1),
1867 };
1868 static const unsigned int du_disp_cde_mux[] = {
1869 DU_DISP_CDE_MARK,
1870 };
1871 static const unsigned int du_cde_pins[] = {
1872 /* CDE */
1873 RCAR_GP_PIN(1, 0),
1874 };
1875 static const unsigned int du_cde_mux[] = {
1876 DU_CDE_MARK,
1877 };
1878 static const unsigned int du_disp_pins[] = {
1879 /* DISP */
1880 RCAR_GP_PIN(1, 2),
1881 };
1882 static const unsigned int du_disp_mux[] = {
1883 DU_DISP_MARK,
1884 };
1885
1886 /* - HSCIF0 --------------------------------------------------*/
1887 static const unsigned int hscif0_data_a_pins[] = {
1888 /* RX, TX */
1889 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1890 };
1891
1892 static const unsigned int hscif0_data_a_mux[] = {
1893 HRX0_A_MARK, HTX0_A_MARK,
1894 };
1895
1896 static const unsigned int hscif0_clk_a_pins[] = {
1897 /* SCK */
1898 RCAR_GP_PIN(5, 7),
1899 };
1900
1901 static const unsigned int hscif0_clk_a_mux[] = {
1902 HSCK0_A_MARK,
1903 };
1904
1905 static const unsigned int hscif0_ctrl_a_pins[] = {
1906 /* RTS, CTS */
1907 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1908 };
1909
1910 static const unsigned int hscif0_ctrl_a_mux[] = {
1911 HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1912 };
1913
1914 static const unsigned int hscif0_data_b_pins[] = {
1915 /* RX, TX */
1916 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1917 };
1918
1919 static const unsigned int hscif0_data_b_mux[] = {
1920 HRX0_B_MARK, HTX0_B_MARK,
1921 };
1922
1923 static const unsigned int hscif0_clk_b_pins[] = {
1924 /* SCK */
1925 RCAR_GP_PIN(6, 13),
1926 };
1927
1928 static const unsigned int hscif0_clk_b_mux[] = {
1929 HSCK0_B_MARK,
1930 };
1931
1932 /* - HSCIF1 ------------------------------------------------- */
1933 static const unsigned int hscif1_data_a_pins[] = {
1934 /* RX, TX */
1935 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1936 };
1937
1938 static const unsigned int hscif1_data_a_mux[] = {
1939 HRX1_A_MARK, HTX1_A_MARK,
1940 };
1941
1942 static const unsigned int hscif1_clk_a_pins[] = {
1943 /* SCK */
1944 RCAR_GP_PIN(5, 0),
1945 };
1946
1947 static const unsigned int hscif1_clk_a_mux[] = {
1948 HSCK1_A_MARK,
1949 };
1950
1951 static const unsigned int hscif1_data_b_pins[] = {
1952 /* RX, TX */
1953 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1954 };
1955
1956 static const unsigned int hscif1_data_b_mux[] = {
1957 HRX1_B_MARK, HTX1_B_MARK,
1958 };
1959
1960 static const unsigned int hscif1_clk_b_pins[] = {
1961 /* SCK */
1962 RCAR_GP_PIN(3, 0),
1963 };
1964
1965 static const unsigned int hscif1_clk_b_mux[] = {
1966 HSCK1_B_MARK,
1967 };
1968
1969 static const unsigned int hscif1_ctrl_b_pins[] = {
1970 /* RTS, CTS */
1971 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1972 };
1973
1974 static const unsigned int hscif1_ctrl_b_mux[] = {
1975 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1976 };
1977
1978 /* - HSCIF2 ------------------------------------------------- */
1979 static const unsigned int hscif2_data_a_pins[] = {
1980 /* RX, TX */
1981 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1982 };
1983
1984 static const unsigned int hscif2_data_a_mux[] = {
1985 HRX2_A_MARK, HTX2_A_MARK,
1986 };
1987
1988 static const unsigned int hscif2_clk_a_pins[] = {
1989 /* SCK */
1990 RCAR_GP_PIN(6, 14),
1991 };
1992
1993 static const unsigned int hscif2_clk_a_mux[] = {
1994 HSCK2_A_MARK,
1995 };
1996
1997 static const unsigned int hscif2_ctrl_a_pins[] = {
1998 /* RTS, CTS */
1999 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2000 };
2001
2002 static const unsigned int hscif2_ctrl_a_mux[] = {
2003 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2004 };
2005
2006 static const unsigned int hscif2_data_b_pins[] = {
2007 /* RX, TX */
2008 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2009 };
2010
2011 static const unsigned int hscif2_data_b_mux[] = {
2012 HRX2_B_MARK, HTX2_B_MARK,
2013 };
2014
2015 /* - HSCIF3 ------------------------------------------------*/
2016 static const unsigned int hscif3_data_a_pins[] = {
2017 /* RX, TX */
2018 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2019 };
2020
2021 static const unsigned int hscif3_data_a_mux[] = {
2022 HRX3_A_MARK, HTX3_A_MARK,
2023 };
2024
2025 static const unsigned int hscif3_data_b_pins[] = {
2026 /* RX, TX */
2027 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2028 };
2029
2030 static const unsigned int hscif3_data_b_mux[] = {
2031 HRX3_B_MARK, HTX3_B_MARK,
2032 };
2033
2034 static const unsigned int hscif3_clk_b_pins[] = {
2035 /* SCK */
2036 RCAR_GP_PIN(0, 4),
2037 };
2038
2039 static const unsigned int hscif3_clk_b_mux[] = {
2040 HSCK3_B_MARK,
2041 };
2042
2043 static const unsigned int hscif3_data_c_pins[] = {
2044 /* RX, TX */
2045 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2046 };
2047
2048 static const unsigned int hscif3_data_c_mux[] = {
2049 HRX3_C_MARK, HTX3_C_MARK,
2050 };
2051
2052 static const unsigned int hscif3_clk_c_pins[] = {
2053 /* SCK */
2054 RCAR_GP_PIN(2, 11),
2055 };
2056
2057 static const unsigned int hscif3_clk_c_mux[] = {
2058 HSCK3_C_MARK,
2059 };
2060
2061 static const unsigned int hscif3_ctrl_c_pins[] = {
2062 /* RTS, CTS */
2063 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2064 };
2065
2066 static const unsigned int hscif3_ctrl_c_mux[] = {
2067 HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2068 };
2069
2070 static const unsigned int hscif3_data_d_pins[] = {
2071 /* RX, TX */
2072 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2073 };
2074
2075 static const unsigned int hscif3_data_d_mux[] = {
2076 HRX3_D_MARK, HTX3_D_MARK,
2077 };
2078
2079 static const unsigned int hscif3_data_e_pins[] = {
2080 /* RX, TX */
2081 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2082 };
2083
2084 static const unsigned int hscif3_data_e_mux[] = {
2085 HRX3_E_MARK, HTX3_E_MARK,
2086 };
2087
2088 static const unsigned int hscif3_ctrl_e_pins[] = {
2089 /* RTS, CTS */
2090 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2091 };
2092
2093 static const unsigned int hscif3_ctrl_e_mux[] = {
2094 HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2095 };
2096
2097 /* - HSCIF4 -------------------------------------------------- */
2098 static const unsigned int hscif4_data_a_pins[] = {
2099 /* RX, TX */
2100 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2101 };
2102
2103 static const unsigned int hscif4_data_a_mux[] = {
2104 HRX4_A_MARK, HTX4_A_MARK,
2105 };
2106
2107 static const unsigned int hscif4_clk_a_pins[] = {
2108 /* SCK */
2109 RCAR_GP_PIN(2, 0),
2110 };
2111
2112 static const unsigned int hscif4_clk_a_mux[] = {
2113 HSCK4_A_MARK,
2114 };
2115
2116 static const unsigned int hscif4_ctrl_a_pins[] = {
2117 /* RTS, CTS */
2118 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2119 };
2120
2121 static const unsigned int hscif4_ctrl_a_mux[] = {
2122 HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2123 };
2124
2125 static const unsigned int hscif4_data_b_pins[] = {
2126 /* RX, TX */
2127 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2128 };
2129
2130 static const unsigned int hscif4_data_b_mux[] = {
2131 HRX4_B_MARK, HTX4_B_MARK,
2132 };
2133
2134 static const unsigned int hscif4_clk_b_pins[] = {
2135 /* SCK */
2136 RCAR_GP_PIN(2, 6),
2137 };
2138
2139 static const unsigned int hscif4_clk_b_mux[] = {
2140 HSCK4_B_MARK,
2141 };
2142
2143 static const unsigned int hscif4_data_c_pins[] = {
2144 /* RX, TX */
2145 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2146 };
2147
2148 static const unsigned int hscif4_data_c_mux[] = {
2149 HRX4_C_MARK, HTX4_C_MARK,
2150 };
2151
2152 static const unsigned int hscif4_data_d_pins[] = {
2153 /* RX, TX */
2154 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2155 };
2156
2157 static const unsigned int hscif4_data_d_mux[] = {
2158 HRX4_D_MARK, HTX4_D_MARK,
2159 };
2160
2161 static const unsigned int hscif4_data_e_pins[] = {
2162 /* RX, TX */
2163 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2164 };
2165
2166 static const unsigned int hscif4_data_e_mux[] = {
2167 HRX4_E_MARK, HTX4_E_MARK,
2168 };
2169
2170 /* - I2C -------------------------------------------------------------------- */
2171 static const unsigned int i2c1_a_pins[] = {
2172 /* SCL, SDA */
2173 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2174 };
2175
2176 static const unsigned int i2c1_a_mux[] = {
2177 SCL1_A_MARK, SDA1_A_MARK,
2178 };
2179
2180 static const unsigned int i2c1_b_pins[] = {
2181 /* SCL, SDA */
2182 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2183 };
2184
2185 static const unsigned int i2c1_b_mux[] = {
2186 SCL1_B_MARK, SDA1_B_MARK,
2187 };
2188
2189 static const unsigned int i2c1_c_pins[] = {
2190 /* SCL, SDA */
2191 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2192 };
2193
2194 static const unsigned int i2c1_c_mux[] = {
2195 SCL1_C_MARK, SDA1_C_MARK,
2196 };
2197
2198 static const unsigned int i2c1_d_pins[] = {
2199 /* SCL, SDA */
2200 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2201 };
2202
2203 static const unsigned int i2c1_d_mux[] = {
2204 SCL1_D_MARK, SDA1_D_MARK,
2205 };
2206
2207 static const unsigned int i2c2_a_pins[] = {
2208 /* SCL, SDA */
2209 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2210 };
2211
2212 static const unsigned int i2c2_a_mux[] = {
2213 SCL2_A_MARK, SDA2_A_MARK,
2214 };
2215
2216 static const unsigned int i2c2_b_pins[] = {
2217 /* SCL, SDA */
2218 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2219 };
2220
2221 static const unsigned int i2c2_b_mux[] = {
2222 SCL2_B_MARK, SDA2_B_MARK,
2223 };
2224
2225 static const unsigned int i2c2_c_pins[] = {
2226 /* SCL, SDA */
2227 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2228 };
2229
2230 static const unsigned int i2c2_c_mux[] = {
2231 SCL2_C_MARK, SDA2_C_MARK,
2232 };
2233
2234 static const unsigned int i2c2_d_pins[] = {
2235 /* SCL, SDA */
2236 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2237 };
2238
2239 static const unsigned int i2c2_d_mux[] = {
2240 SCL2_D_MARK, SDA2_D_MARK,
2241 };
2242
2243 static const unsigned int i2c2_e_pins[] = {
2244 /* SCL, SDA */
2245 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2246 };
2247
2248 static const unsigned int i2c2_e_mux[] = {
2249 SCL2_E_MARK, SDA2_E_MARK,
2250 };
2251
2252 static const unsigned int i2c4_pins[] = {
2253 /* SCL, SDA */
2254 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2255 };
2256
2257 static const unsigned int i2c4_mux[] = {
2258 SCL4_MARK, SDA4_MARK,
2259 };
2260
2261 static const unsigned int i2c5_pins[] = {
2262 /* SCL, SDA */
2263 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2264 };
2265
2266 static const unsigned int i2c5_mux[] = {
2267 SCL5_MARK, SDA5_MARK,
2268 };
2269
2270 static const unsigned int i2c6_a_pins[] = {
2271 /* SCL, SDA */
2272 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2273 };
2274
2275 static const unsigned int i2c6_a_mux[] = {
2276 SCL6_A_MARK, SDA6_A_MARK,
2277 };
2278
2279 static const unsigned int i2c6_b_pins[] = {
2280 /* SCL, SDA */
2281 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2282 };
2283
2284 static const unsigned int i2c6_b_mux[] = {
2285 SCL6_B_MARK, SDA6_B_MARK,
2286 };
2287
2288 static const unsigned int i2c7_a_pins[] = {
2289 /* SCL, SDA */
2290 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2291 };
2292
2293 static const unsigned int i2c7_a_mux[] = {
2294 SCL7_A_MARK, SDA7_A_MARK,
2295 };
2296
2297 static const unsigned int i2c7_b_pins[] = {
2298 /* SCL, SDA */
2299 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2300 };
2301
2302 static const unsigned int i2c7_b_mux[] = {
2303 SCL7_B_MARK, SDA7_B_MARK,
2304 };
2305
2306 /* - INTC-EX ---------------------------------------------------------------- */
2307 static const unsigned int intc_ex_irq0_pins[] = {
2308 /* IRQ0 */
2309 RCAR_GP_PIN(1, 0),
2310 };
2311 static const unsigned int intc_ex_irq0_mux[] = {
2312 IRQ0_MARK,
2313 };
2314 static const unsigned int intc_ex_irq1_pins[] = {
2315 /* IRQ1 */
2316 RCAR_GP_PIN(1, 1),
2317 };
2318 static const unsigned int intc_ex_irq1_mux[] = {
2319 IRQ1_MARK,
2320 };
2321 static const unsigned int intc_ex_irq2_pins[] = {
2322 /* IRQ2 */
2323 RCAR_GP_PIN(1, 2),
2324 };
2325 static const unsigned int intc_ex_irq2_mux[] = {
2326 IRQ2_MARK,
2327 };
2328 static const unsigned int intc_ex_irq3_pins[] = {
2329 /* IRQ3 */
2330 RCAR_GP_PIN(1, 9),
2331 };
2332 static const unsigned int intc_ex_irq3_mux[] = {
2333 IRQ3_MARK,
2334 };
2335 static const unsigned int intc_ex_irq4_pins[] = {
2336 /* IRQ4 */
2337 RCAR_GP_PIN(1, 10),
2338 };
2339 static const unsigned int intc_ex_irq4_mux[] = {
2340 IRQ4_MARK,
2341 };
2342 static const unsigned int intc_ex_irq5_pins[] = {
2343 /* IRQ5 */
2344 RCAR_GP_PIN(0, 7),
2345 };
2346 static const unsigned int intc_ex_irq5_mux[] = {
2347 IRQ5_MARK,
2348 };
2349
2350 /* - MSIOF0 ----------------------------------------------------------------- */
2351 static const unsigned int msiof0_clk_pins[] = {
2352 /* SCK */
2353 RCAR_GP_PIN(5, 10),
2354 };
2355
2356 static const unsigned int msiof0_clk_mux[] = {
2357 MSIOF0_SCK_MARK,
2358 };
2359
2360 static const unsigned int msiof0_sync_pins[] = {
2361 /* SYNC */
2362 RCAR_GP_PIN(5, 13),
2363 };
2364
2365 static const unsigned int msiof0_sync_mux[] = {
2366 MSIOF0_SYNC_MARK,
2367 };
2368
2369 static const unsigned int msiof0_ss1_pins[] = {
2370 /* SS1 */
2371 RCAR_GP_PIN(5, 14),
2372 };
2373
2374 static const unsigned int msiof0_ss1_mux[] = {
2375 MSIOF0_SS1_MARK,
2376 };
2377
2378 static const unsigned int msiof0_ss2_pins[] = {
2379 /* SS2 */
2380 RCAR_GP_PIN(5, 15),
2381 };
2382
2383 static const unsigned int msiof0_ss2_mux[] = {
2384 MSIOF0_SS2_MARK,
2385 };
2386
2387 static const unsigned int msiof0_txd_pins[] = {
2388 /* TXD */
2389 RCAR_GP_PIN(5, 12),
2390 };
2391
2392 static const unsigned int msiof0_txd_mux[] = {
2393 MSIOF0_TXD_MARK,
2394 };
2395
2396 static const unsigned int msiof0_rxd_pins[] = {
2397 /* RXD */
2398 RCAR_GP_PIN(5, 11),
2399 };
2400
2401 static const unsigned int msiof0_rxd_mux[] = {
2402 MSIOF0_RXD_MARK,
2403 };
2404
2405 /* - MSIOF1 ----------------------------------------------------------------- */
2406 static const unsigned int msiof1_clk_pins[] = {
2407 /* SCK */
2408 RCAR_GP_PIN(1, 19),
2409 };
2410
2411 static const unsigned int msiof1_clk_mux[] = {
2412 MSIOF1_SCK_MARK,
2413 };
2414
2415 static const unsigned int msiof1_sync_pins[] = {
2416 /* SYNC */
2417 RCAR_GP_PIN(1, 16),
2418 };
2419
2420 static const unsigned int msiof1_sync_mux[] = {
2421 MSIOF1_SYNC_MARK,
2422 };
2423
2424 static const unsigned int msiof1_ss1_pins[] = {
2425 /* SS1 */
2426 RCAR_GP_PIN(1, 14),
2427 };
2428
2429 static const unsigned int msiof1_ss1_mux[] = {
2430 MSIOF1_SS1_MARK,
2431 };
2432
2433 static const unsigned int msiof1_ss2_pins[] = {
2434 /* SS2 */
2435 RCAR_GP_PIN(1, 15),
2436 };
2437
2438 static const unsigned int msiof1_ss2_mux[] = {
2439 MSIOF1_SS2_MARK,
2440 };
2441
2442 static const unsigned int msiof1_txd_pins[] = {
2443 /* TXD */
2444 RCAR_GP_PIN(1, 18),
2445 };
2446
2447 static const unsigned int msiof1_txd_mux[] = {
2448 MSIOF1_TXD_MARK,
2449 };
2450
2451 static const unsigned int msiof1_rxd_pins[] = {
2452 /* RXD */
2453 RCAR_GP_PIN(1, 17),
2454 };
2455
2456 static const unsigned int msiof1_rxd_mux[] = {
2457 MSIOF1_RXD_MARK,
2458 };
2459
2460 /* - MSIOF2 ----------------------------------------------------------------- */
2461 static const unsigned int msiof2_clk_a_pins[] = {
2462 /* SCK */
2463 RCAR_GP_PIN(0, 8),
2464 };
2465
2466 static const unsigned int msiof2_clk_a_mux[] = {
2467 MSIOF2_SCK_A_MARK,
2468 };
2469
2470 static const unsigned int msiof2_sync_a_pins[] = {
2471 /* SYNC */
2472 RCAR_GP_PIN(0, 9),
2473 };
2474
2475 static const unsigned int msiof2_sync_a_mux[] = {
2476 MSIOF2_SYNC_A_MARK,
2477 };
2478
2479 static const unsigned int msiof2_ss1_a_pins[] = {
2480 /* SS1 */
2481 RCAR_GP_PIN(0, 15),
2482 };
2483
2484 static const unsigned int msiof2_ss1_a_mux[] = {
2485 MSIOF2_SS1_A_MARK,
2486 };
2487
2488 static const unsigned int msiof2_ss2_a_pins[] = {
2489 /* SS2 */
2490 RCAR_GP_PIN(0, 14),
2491 };
2492
2493 static const unsigned int msiof2_ss2_a_mux[] = {
2494 MSIOF2_SS2_A_MARK,
2495 };
2496
2497 static const unsigned int msiof2_txd_a_pins[] = {
2498 /* TXD */
2499 RCAR_GP_PIN(0, 11),
2500 };
2501
2502 static const unsigned int msiof2_txd_a_mux[] = {
2503 MSIOF2_TXD_A_MARK,
2504 };
2505
2506 static const unsigned int msiof2_rxd_a_pins[] = {
2507 /* RXD */
2508 RCAR_GP_PIN(0, 10),
2509 };
2510
2511 static const unsigned int msiof2_rxd_a_mux[] = {
2512 MSIOF2_RXD_A_MARK,
2513 };
2514
2515 static const unsigned int msiof2_clk_b_pins[] = {
2516 /* SCK */
2517 RCAR_GP_PIN(1, 13),
2518 };
2519
2520 static const unsigned int msiof2_clk_b_mux[] = {
2521 MSIOF2_SCK_B_MARK,
2522 };
2523
2524 static const unsigned int msiof2_sync_b_pins[] = {
2525 /* SYNC */
2526 RCAR_GP_PIN(1, 10),
2527 };
2528
2529 static const unsigned int msiof2_sync_b_mux[] = {
2530 MSIOF2_SYNC_B_MARK,
2531 };
2532
2533 static const unsigned int msiof2_ss1_b_pins[] = {
2534 /* SS1 */
2535 RCAR_GP_PIN(1, 16),
2536 };
2537
2538 static const unsigned int msiof2_ss1_b_mux[] = {
2539 MSIOF2_SS1_B_MARK,
2540 };
2541
2542 static const unsigned int msiof2_ss2_b_pins[] = {
2543 /* SS2 */
2544 RCAR_GP_PIN(1, 12),
2545 };
2546
2547 static const unsigned int msiof2_ss2_b_mux[] = {
2548 MSIOF2_SS2_B_MARK,
2549 };
2550
2551 static const unsigned int msiof2_txd_b_pins[] = {
2552 /* TXD */
2553 RCAR_GP_PIN(1, 15),
2554 };
2555
2556 static const unsigned int msiof2_txd_b_mux[] = {
2557 MSIOF2_TXD_B_MARK,
2558 };
2559
2560 static const unsigned int msiof2_rxd_b_pins[] = {
2561 /* RXD */
2562 RCAR_GP_PIN(1, 14),
2563 };
2564
2565 static const unsigned int msiof2_rxd_b_mux[] = {
2566 MSIOF2_RXD_B_MARK,
2567 };
2568
2569 /* - MSIOF3 ----------------------------------------------------------------- */
2570 static const unsigned int msiof3_clk_a_pins[] = {
2571 /* SCK */
2572 RCAR_GP_PIN(0, 0),
2573 };
2574
2575 static const unsigned int msiof3_clk_a_mux[] = {
2576 MSIOF3_SCK_A_MARK,
2577 };
2578
2579 static const unsigned int msiof3_sync_a_pins[] = {
2580 /* SYNC */
2581 RCAR_GP_PIN(0, 1),
2582 };
2583
2584 static const unsigned int msiof3_sync_a_mux[] = {
2585 MSIOF3_SYNC_A_MARK,
2586 };
2587
2588 static const unsigned int msiof3_ss1_a_pins[] = {
2589 /* SS1 */
2590 RCAR_GP_PIN(0, 15),
2591 };
2592
2593 static const unsigned int msiof3_ss1_a_mux[] = {
2594 MSIOF3_SS1_A_MARK,
2595 };
2596
2597 static const unsigned int msiof3_ss2_a_pins[] = {
2598 /* SS2 */
2599 RCAR_GP_PIN(0, 4),
2600 };
2601
2602 static const unsigned int msiof3_ss2_a_mux[] = {
2603 MSIOF3_SS2_A_MARK,
2604 };
2605
2606 static const unsigned int msiof3_txd_a_pins[] = {
2607 /* TXD */
2608 RCAR_GP_PIN(0, 3),
2609 };
2610
2611 static const unsigned int msiof3_txd_a_mux[] = {
2612 MSIOF3_TXD_A_MARK,
2613 };
2614
2615 static const unsigned int msiof3_rxd_a_pins[] = {
2616 /* RXD */
2617 RCAR_GP_PIN(0, 2),
2618 };
2619
2620 static const unsigned int msiof3_rxd_a_mux[] = {
2621 MSIOF3_RXD_A_MARK,
2622 };
2623
2624 static const unsigned int msiof3_clk_b_pins[] = {
2625 /* SCK */
2626 RCAR_GP_PIN(1, 5),
2627 };
2628
2629 static const unsigned int msiof3_clk_b_mux[] = {
2630 MSIOF3_SCK_B_MARK,
2631 };
2632
2633 static const unsigned int msiof3_sync_b_pins[] = {
2634 /* SYNC */
2635 RCAR_GP_PIN(1, 4),
2636 };
2637
2638 static const unsigned int msiof3_sync_b_mux[] = {
2639 MSIOF3_SYNC_B_MARK,
2640 };
2641
2642 static const unsigned int msiof3_ss1_b_pins[] = {
2643 /* SS1 */
2644 RCAR_GP_PIN(1, 0),
2645 };
2646
2647 static const unsigned int msiof3_ss1_b_mux[] = {
2648 MSIOF3_SS1_B_MARK,
2649 };
2650
2651 static const unsigned int msiof3_txd_b_pins[] = {
2652 /* TXD */
2653 RCAR_GP_PIN(1, 7),
2654 };
2655
2656 static const unsigned int msiof3_txd_b_mux[] = {
2657 MSIOF3_TXD_B_MARK,
2658 };
2659
2660 static const unsigned int msiof3_rxd_b_pins[] = {
2661 /* RXD */
2662 RCAR_GP_PIN(1, 6),
2663 };
2664
2665 static const unsigned int msiof3_rxd_b_mux[] = {
2666 MSIOF3_RXD_B_MARK,
2667 };
2668
2669 /* - PWM0 --------------------------------------------------------------------*/
2670 static const unsigned int pwm0_a_pins[] = {
2671 /* PWM */
2672 RCAR_GP_PIN(2, 22),
2673 };
2674
2675 static const unsigned int pwm0_a_mux[] = {
2676 PWM0_A_MARK,
2677 };
2678
2679 static const unsigned int pwm0_b_pins[] = {
2680 /* PWM */
2681 RCAR_GP_PIN(6, 3),
2682 };
2683
2684 static const unsigned int pwm0_b_mux[] = {
2685 PWM0_B_MARK,
2686 };
2687
2688 /* - PWM1 --------------------------------------------------------------------*/
2689 static const unsigned int pwm1_a_pins[] = {
2690 /* PWM */
2691 RCAR_GP_PIN(2, 23),
2692 };
2693
2694 static const unsigned int pwm1_a_mux[] = {
2695 PWM1_A_MARK,
2696 };
2697
2698 static const unsigned int pwm1_b_pins[] = {
2699 /* PWM */
2700 RCAR_GP_PIN(6, 4),
2701 };
2702
2703 static const unsigned int pwm1_b_mux[] = {
2704 PWM1_B_MARK,
2705 };
2706
2707 /* - PWM2 --------------------------------------------------------------------*/
2708 static const unsigned int pwm2_a_pins[] = {
2709 /* PWM */
2710 RCAR_GP_PIN(1, 0),
2711 };
2712
2713 static const unsigned int pwm2_a_mux[] = {
2714 PWM2_A_MARK,
2715 };
2716
2717 static const unsigned int pwm2_b_pins[] = {
2718 /* PWM */
2719 RCAR_GP_PIN(1, 4),
2720 };
2721
2722 static const unsigned int pwm2_b_mux[] = {
2723 PWM2_B_MARK,
2724 };
2725
2726 static const unsigned int pwm2_c_pins[] = {
2727 /* PWM */
2728 RCAR_GP_PIN(6, 5),
2729 };
2730
2731 static const unsigned int pwm2_c_mux[] = {
2732 PWM2_C_MARK,
2733 };
2734
2735 /* - PWM3 --------------------------------------------------------------------*/
2736 static const unsigned int pwm3_a_pins[] = {
2737 /* PWM */
2738 RCAR_GP_PIN(1, 1),
2739 };
2740
2741 static const unsigned int pwm3_a_mux[] = {
2742 PWM3_A_MARK,
2743 };
2744
2745 static const unsigned int pwm3_b_pins[] = {
2746 /* PWM */
2747 RCAR_GP_PIN(1, 5),
2748 };
2749
2750 static const unsigned int pwm3_b_mux[] = {
2751 PWM3_B_MARK,
2752 };
2753
2754 static const unsigned int pwm3_c_pins[] = {
2755 /* PWM */
2756 RCAR_GP_PIN(6, 6),
2757 };
2758
2759 static const unsigned int pwm3_c_mux[] = {
2760 PWM3_C_MARK,
2761 };
2762
2763 /* - PWM4 --------------------------------------------------------------------*/
2764 static const unsigned int pwm4_a_pins[] = {
2765 /* PWM */
2766 RCAR_GP_PIN(1, 3),
2767 };
2768
2769 static const unsigned int pwm4_a_mux[] = {
2770 PWM4_A_MARK,
2771 };
2772
2773 static const unsigned int pwm4_b_pins[] = {
2774 /* PWM */
2775 RCAR_GP_PIN(6, 7),
2776 };
2777
2778 static const unsigned int pwm4_b_mux[] = {
2779 PWM4_B_MARK,
2780 };
2781
2782 /* - PWM5 --------------------------------------------------------------------*/
2783 static const unsigned int pwm5_a_pins[] = {
2784 /* PWM */
2785 RCAR_GP_PIN(2, 24),
2786 };
2787
2788 static const unsigned int pwm5_a_mux[] = {
2789 PWM5_A_MARK,
2790 };
2791
2792 static const unsigned int pwm5_b_pins[] = {
2793 /* PWM */
2794 RCAR_GP_PIN(6, 10),
2795 };
2796
2797 static const unsigned int pwm5_b_mux[] = {
2798 PWM5_B_MARK,
2799 };
2800
2801 /* - PWM6 --------------------------------------------------------------------*/
2802 static const unsigned int pwm6_a_pins[] = {
2803 /* PWM */
2804 RCAR_GP_PIN(2, 25),
2805 };
2806
2807 static const unsigned int pwm6_a_mux[] = {
2808 PWM6_A_MARK,
2809 };
2810
2811 static const unsigned int pwm6_b_pins[] = {
2812 /* PWM */
2813 RCAR_GP_PIN(6, 11),
2814 };
2815
2816 static const unsigned int pwm6_b_mux[] = {
2817 PWM6_B_MARK,
2818 };
2819
2820 /* - SCIF0 ------------------------------------------------------------------ */
2821 static const unsigned int scif0_data_a_pins[] = {
2822 /* RX, TX */
2823 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2824 };
2825
2826 static const unsigned int scif0_data_a_mux[] = {
2827 RX0_A_MARK, TX0_A_MARK,
2828 };
2829
2830 static const unsigned int scif0_clk_a_pins[] = {
2831 /* SCK */
2832 RCAR_GP_PIN(5, 0),
2833 };
2834
2835 static const unsigned int scif0_clk_a_mux[] = {
2836 SCK0_A_MARK,
2837 };
2838
2839 static const unsigned int scif0_ctrl_a_pins[] = {
2840 /* RTS, CTS */
2841 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2842 };
2843
2844 static const unsigned int scif0_ctrl_a_mux[] = {
2845 RTS0_N_TANS_A_MARK, CTS0_N_A_MARK,
2846 };
2847
2848 static const unsigned int scif0_data_b_pins[] = {
2849 /* RX, TX */
2850 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2851 };
2852
2853 static const unsigned int scif0_data_b_mux[] = {
2854 RX0_B_MARK, TX0_B_MARK,
2855 };
2856
2857 static const unsigned int scif0_clk_b_pins[] = {
2858 /* SCK */
2859 RCAR_GP_PIN(5, 18),
2860 };
2861
2862 static const unsigned int scif0_clk_b_mux[] = {
2863 SCK0_B_MARK,
2864 };
2865
2866 /* - SCIF1 ------------------------------------------------------------------ */
2867 static const unsigned int scif1_data_pins[] = {
2868 /* RX, TX */
2869 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2870 };
2871
2872 static const unsigned int scif1_data_mux[] = {
2873 RX1_MARK, TX1_MARK,
2874 };
2875
2876 static const unsigned int scif1_clk_pins[] = {
2877 /* SCK */
2878 RCAR_GP_PIN(5, 16),
2879 };
2880
2881 static const unsigned int scif1_clk_mux[] = {
2882 SCK1_MARK,
2883 };
2884
2885 static const unsigned int scif1_ctrl_pins[] = {
2886 /* RTS, CTS */
2887 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2888 };
2889
2890 static const unsigned int scif1_ctrl_mux[] = {
2891 RTS1_N_TANS_MARK, CTS1_N_MARK,
2892 };
2893
2894 /* - SCIF2 ------------------------------------------------------------------ */
2895 static const unsigned int scif2_data_a_pins[] = {
2896 /* RX, TX */
2897 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2898 };
2899
2900 static const unsigned int scif2_data_a_mux[] = {
2901 RX2_A_MARK, TX2_A_MARK,
2902 };
2903
2904 static const unsigned int scif2_clk_a_pins[] = {
2905 /* SCK */
2906 RCAR_GP_PIN(5, 7),
2907 };
2908
2909 static const unsigned int scif2_clk_a_mux[] = {
2910 SCK2_A_MARK,
2911 };
2912
2913 static const unsigned int scif2_data_b_pins[] = {
2914 /* RX, TX */
2915 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2916 };
2917
2918 static const unsigned int scif2_data_b_mux[] = {
2919 RX2_B_MARK, TX2_B_MARK,
2920 };
2921
2922 /* - SCIF3 ------------------------------------------------------------------ */
2923 static const unsigned int scif3_data_a_pins[] = {
2924 /* RX, TX */
2925 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2926 };
2927
2928 static const unsigned int scif3_data_a_mux[] = {
2929 RX3_A_MARK, TX3_A_MARK,
2930 };
2931
2932 static const unsigned int scif3_clk_a_pins[] = {
2933 /* SCK */
2934 RCAR_GP_PIN(0, 1),
2935 };
2936
2937 static const unsigned int scif3_clk_a_mux[] = {
2938 SCK3_A_MARK,
2939 };
2940
2941 static const unsigned int scif3_ctrl_a_pins[] = {
2942 /* RTS, CTS */
2943 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
2944 };
2945
2946 static const unsigned int scif3_ctrl_a_mux[] = {
2947 RTS3_N_TANS_A_MARK, CTS3_N_A_MARK,
2948 };
2949
2950 static const unsigned int scif3_data_b_pins[] = {
2951 /* RX, TX */
2952 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2953 };
2954
2955 static const unsigned int scif3_data_b_mux[] = {
2956 RX3_B_MARK, TX3_B_MARK,
2957 };
2958
2959 static const unsigned int scif3_data_c_pins[] = {
2960 /* RX, TX */
2961 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2962 };
2963
2964 static const unsigned int scif3_data_c_mux[] = {
2965 RX3_C_MARK, TX3_C_MARK,
2966 };
2967
2968 static const unsigned int scif3_clk_c_pins[] = {
2969 /* SCK */
2970 RCAR_GP_PIN(2, 24),
2971 };
2972
2973 static const unsigned int scif3_clk_c_mux[] = {
2974 SCK3_C_MARK,
2975 };
2976
2977 /* - SCIF4 ------------------------------------------------------------------ */
2978 static const unsigned int scif4_data_a_pins[] = {
2979 /* RX, TX */
2980 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2981 };
2982
2983 static const unsigned int scif4_data_a_mux[] = {
2984 RX4_A_MARK, TX4_A_MARK,
2985 };
2986
2987 static const unsigned int scif4_clk_a_pins[] = {
2988 /* SCK */
2989 RCAR_GP_PIN(1, 5),
2990 };
2991
2992 static const unsigned int scif4_clk_a_mux[] = {
2993 SCK4_A_MARK,
2994 };
2995
2996 static const unsigned int scif4_ctrl_a_pins[] = {
2997 /* RTS, CTS */
2998 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
2999 };
3000
3001 static const unsigned int scif4_ctrl_a_mux[] = {
3002 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3003 };
3004
3005 static const unsigned int scif4_data_b_pins[] = {
3006 /* RX, TX */
3007 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
3008 };
3009
3010 static const unsigned int scif4_data_b_mux[] = {
3011 RX4_B_MARK, TX4_B_MARK,
3012 };
3013
3014 static const unsigned int scif4_clk_b_pins[] = {
3015 /* SCK */
3016 RCAR_GP_PIN(0, 8),
3017 };
3018
3019 static const unsigned int scif4_clk_b_mux[] = {
3020 SCK4_B_MARK,
3021 };
3022
3023 static const unsigned int scif4_data_c_pins[] = {
3024 /* RX, TX */
3025 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3026 };
3027
3028 static const unsigned int scif4_data_c_mux[] = {
3029 RX4_C_MARK, TX4_C_MARK,
3030 };
3031
3032 static const unsigned int scif4_ctrl_c_pins[] = {
3033 /* RTS, CTS */
3034 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3035 };
3036
3037 static const unsigned int scif4_ctrl_c_mux[] = {
3038 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3039 };
3040
3041 /* - SCIF5 ------------------------------------------------------------------ */
3042 static const unsigned int scif5_data_a_pins[] = {
3043 /* RX, TX */
3044 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3045 };
3046
3047 static const unsigned int scif5_data_a_mux[] = {
3048 RX5_A_MARK, TX5_A_MARK,
3049 };
3050
3051 static const unsigned int scif5_clk_a_pins[] = {
3052 /* SCK */
3053 RCAR_GP_PIN(1, 13),
3054 };
3055
3056 static const unsigned int scif5_clk_a_mux[] = {
3057 SCK5_A_MARK,
3058 };
3059
3060 static const unsigned int scif5_data_b_pins[] = {
3061 /* RX, TX */
3062 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3063 };
3064
3065 static const unsigned int scif5_data_b_mux[] = {
3066 RX5_B_MARK, TX5_B_MARK,
3067 };
3068
3069 static const unsigned int scif5_data_c_pins[] = {
3070 /* RX, TX */
3071 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3072 };
3073
3074 static const unsigned int scif5_data_c_mux[] = {
3075 RX5_C_MARK, TX5_C_MARK,
3076 };
3077
3078 /* - SCIF Clock ------------------------------------------------------------- */
3079 static const unsigned int scif_clk_a_pins[] = {
3080 /* SCIF_CLK */
3081 RCAR_GP_PIN(5, 3),
3082 };
3083
3084 static const unsigned int scif_clk_a_mux[] = {
3085 SCIF_CLK_A_MARK,
3086 };
3087
3088 static const unsigned int scif_clk_b_pins[] = {
3089 /* SCIF_CLK */
3090 RCAR_GP_PIN(5, 7),
3091 };
3092
3093 static const unsigned int scif_clk_b_mux[] = {
3094 SCIF_CLK_B_MARK,
3095 };
3096
3097 /* - SDHI0 ------------------------------------------------------------------ */
3098 static const unsigned int sdhi0_data1_pins[] = {
3099 /* D0 */
3100 RCAR_GP_PIN(3, 2),
3101 };
3102
3103 static const unsigned int sdhi0_data1_mux[] = {
3104 SD0_DAT0_MARK,
3105 };
3106
3107 static const unsigned int sdhi0_data4_pins[] = {
3108 /* D[0:3] */
3109 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3110 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3111 };
3112
3113 static const unsigned int sdhi0_data4_mux[] = {
3114 SD0_DAT0_MARK, SD0_DAT1_MARK,
3115 SD0_DAT2_MARK, SD0_DAT3_MARK,
3116 };
3117
3118 static const unsigned int sdhi0_ctrl_pins[] = {
3119 /* CLK, CMD */
3120 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3121 };
3122
3123 static const unsigned int sdhi0_ctrl_mux[] = {
3124 SD0_CLK_MARK, SD0_CMD_MARK,
3125 };
3126
3127 static const unsigned int sdhi0_cd_pins[] = {
3128 /* CD */
3129 RCAR_GP_PIN(3, 12),
3130 };
3131
3132 static const unsigned int sdhi0_cd_mux[] = {
3133 SD0_CD_MARK,
3134 };
3135
3136 static const unsigned int sdhi0_wp_pins[] = {
3137 /* WP */
3138 RCAR_GP_PIN(3, 13),
3139 };
3140
3141 static const unsigned int sdhi0_wp_mux[] = {
3142 SD0_WP_MARK,
3143 };
3144
3145 /* - SDHI1 ------------------------------------------------------------------ */
3146 static const unsigned int sdhi1_data1_pins[] = {
3147 /* D0 */
3148 RCAR_GP_PIN(3, 8),
3149 };
3150
3151 static const unsigned int sdhi1_data1_mux[] = {
3152 SD1_DAT0_MARK,
3153 };
3154
3155 static const unsigned int sdhi1_data4_pins[] = {
3156 /* D[0:3] */
3157 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3158 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3159 };
3160
3161 static const unsigned int sdhi1_data4_mux[] = {
3162 SD1_DAT0_MARK, SD1_DAT1_MARK,
3163 SD1_DAT2_MARK, SD1_DAT3_MARK,
3164 };
3165
3166 static const unsigned int sdhi1_ctrl_pins[] = {
3167 /* CLK, CMD */
3168 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3169 };
3170
3171 static const unsigned int sdhi1_ctrl_mux[] = {
3172 SD1_CLK_MARK, SD1_CMD_MARK,
3173 };
3174
3175 static const unsigned int sdhi1_cd_pins[] = {
3176 /* CD */
3177 RCAR_GP_PIN(3, 14),
3178 };
3179
3180 static const unsigned int sdhi1_cd_mux[] = {
3181 SD1_CD_MARK,
3182 };
3183
3184 static const unsigned int sdhi1_wp_pins[] = {
3185 /* WP */
3186 RCAR_GP_PIN(3, 15),
3187 };
3188
3189 static const unsigned int sdhi1_wp_mux[] = {
3190 SD1_WP_MARK,
3191 };
3192
3193 /* - SDHI3 ------------------------------------------------------------------ */
3194 static const unsigned int sdhi3_data1_pins[] = {
3195 /* D0 */
3196 RCAR_GP_PIN(4, 2),
3197 };
3198
3199 static const unsigned int sdhi3_data1_mux[] = {
3200 SD3_DAT0_MARK,
3201 };
3202
3203 static const unsigned int sdhi3_data4_pins[] = {
3204 /* D[0:3] */
3205 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3206 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3207 };
3208
3209 static const unsigned int sdhi3_data4_mux[] = {
3210 SD3_DAT0_MARK, SD3_DAT1_MARK,
3211 SD3_DAT2_MARK, SD3_DAT3_MARK,
3212 };
3213
3214 static const unsigned int sdhi3_data8_pins[] = {
3215 /* D[0:7] */
3216 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3217 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3218 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3219 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3220 };
3221
3222 static const unsigned int sdhi3_data8_mux[] = {
3223 SD3_DAT0_MARK, SD3_DAT1_MARK,
3224 SD3_DAT2_MARK, SD3_DAT3_MARK,
3225 SD3_DAT4_MARK, SD3_DAT5_MARK,
3226 SD3_DAT6_MARK, SD3_DAT7_MARK,
3227 };
3228
3229 static const unsigned int sdhi3_ctrl_pins[] = {
3230 /* CLK, CMD */
3231 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3232 };
3233
3234 static const unsigned int sdhi3_ctrl_mux[] = {
3235 SD3_CLK_MARK, SD3_CMD_MARK,
3236 };
3237
3238 static const unsigned int sdhi3_cd_pins[] = {
3239 /* CD */
3240 RCAR_GP_PIN(3, 12),
3241 };
3242
3243 static const unsigned int sdhi3_cd_mux[] = {
3244 SD3_CD_MARK,
3245 };
3246
3247 static const unsigned int sdhi3_wp_pins[] = {
3248 /* WP */
3249 RCAR_GP_PIN(3, 13),
3250 };
3251
3252 static const unsigned int sdhi3_wp_mux[] = {
3253 SD3_WP_MARK,
3254 };
3255
3256 static const unsigned int sdhi3_ds_pins[] = {
3257 /* DS */
3258 RCAR_GP_PIN(4, 10),
3259 };
3260
3261 static const unsigned int sdhi3_ds_mux[] = {
3262 SD3_DS_MARK,
3263 };
3264
3265 /* - SSI -------------------------------------------------------------------- */
3266 static const unsigned int ssi0_data_pins[] = {
3267 /* SDATA */
3268 RCAR_GP_PIN(6, 2),
3269 };
3270
3271 static const unsigned int ssi0_data_mux[] = {
3272 SSI_SDATA0_MARK,
3273 };
3274
3275 static const unsigned int ssi01239_ctrl_pins[] = {
3276 /* SCK, WS */
3277 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3278 };
3279
3280 static const unsigned int ssi01239_ctrl_mux[] = {
3281 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3282 };
3283
3284 static const unsigned int ssi1_data_pins[] = {
3285 /* SDATA */
3286 RCAR_GP_PIN(6, 3),
3287 };
3288
3289 static const unsigned int ssi1_data_mux[] = {
3290 SSI_SDATA1_MARK,
3291 };
3292
3293 static const unsigned int ssi1_ctrl_pins[] = {
3294 /* SCK, WS */
3295 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3296 };
3297
3298 static const unsigned int ssi1_ctrl_mux[] = {
3299 SSI_SCK1_MARK, SSI_WS1_MARK,
3300 };
3301
3302 static const unsigned int ssi2_data_pins[] = {
3303 /* SDATA */
3304 RCAR_GP_PIN(6, 4),
3305 };
3306
3307 static const unsigned int ssi2_data_mux[] = {
3308 SSI_SDATA2_MARK,
3309 };
3310
3311 static const unsigned int ssi2_ctrl_a_pins[] = {
3312 /* SCK, WS */
3313 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3314 };
3315
3316 static const unsigned int ssi2_ctrl_a_mux[] = {
3317 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3318 };
3319
3320 static const unsigned int ssi2_ctrl_b_pins[] = {
3321 /* SCK, WS */
3322 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3323 };
3324
3325 static const unsigned int ssi2_ctrl_b_mux[] = {
3326 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3327 };
3328
3329 static const unsigned int ssi3_data_pins[] = {
3330 /* SDATA */
3331 RCAR_GP_PIN(6, 7),
3332 };
3333
3334 static const unsigned int ssi3_data_mux[] = {
3335 SSI_SDATA3_MARK,
3336 };
3337
3338 static const unsigned int ssi349_ctrl_pins[] = {
3339 /* SCK, WS */
3340 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3341 };
3342
3343 static const unsigned int ssi349_ctrl_mux[] = {
3344 SSI_SCK349_MARK, SSI_WS349_MARK,
3345 };
3346
3347 static const unsigned int ssi4_data_pins[] = {
3348 /* SDATA */
3349 RCAR_GP_PIN(6, 10),
3350 };
3351
3352 static const unsigned int ssi4_data_mux[] = {
3353 SSI_SDATA4_MARK,
3354 };
3355
3356 static const unsigned int ssi4_ctrl_pins[] = {
3357 /* SCK, WS */
3358 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3359 };
3360
3361 static const unsigned int ssi4_ctrl_mux[] = {
3362 SSI_SCK4_MARK, SSI_WS4_MARK,
3363 };
3364
3365 static const unsigned int ssi5_data_pins[] = {
3366 /* SDATA */
3367 RCAR_GP_PIN(6, 13),
3368 };
3369
3370 static const unsigned int ssi5_data_mux[] = {
3371 SSI_SDATA5_MARK,
3372 };
3373
3374 static const unsigned int ssi5_ctrl_pins[] = {
3375 /* SCK, WS */
3376 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3377 };
3378
3379 static const unsigned int ssi5_ctrl_mux[] = {
3380 SSI_SCK5_MARK, SSI_WS5_MARK,
3381 };
3382
3383 static const unsigned int ssi6_data_pins[] = {
3384 /* SDATA */
3385 RCAR_GP_PIN(6, 16),
3386 };
3387
3388 static const unsigned int ssi6_data_mux[] = {
3389 SSI_SDATA6_MARK,
3390 };
3391
3392 static const unsigned int ssi6_ctrl_pins[] = {
3393 /* SCK, WS */
3394 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3395 };
3396
3397 static const unsigned int ssi6_ctrl_mux[] = {
3398 SSI_SCK6_MARK, SSI_WS6_MARK,
3399 };
3400
3401 static const unsigned int ssi7_data_pins[] = {
3402 /* SDATA */
3403 RCAR_GP_PIN(5, 12),
3404 };
3405
3406 static const unsigned int ssi7_data_mux[] = {
3407 SSI_SDATA7_MARK,
3408 };
3409
3410 static const unsigned int ssi78_ctrl_pins[] = {
3411 /* SCK, WS */
3412 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3413 };
3414
3415 static const unsigned int ssi78_ctrl_mux[] = {
3416 SSI_SCK78_MARK, SSI_WS78_MARK,
3417 };
3418
3419 static const unsigned int ssi8_data_pins[] = {
3420 /* SDATA */
3421 RCAR_GP_PIN(5, 13),
3422 };
3423
3424 static const unsigned int ssi8_data_mux[] = {
3425 SSI_SDATA8_MARK,
3426 };
3427
3428 static const unsigned int ssi9_data_pins[] = {
3429 /* SDATA */
3430 RCAR_GP_PIN(5, 16),
3431 };
3432
3433 static const unsigned int ssi9_data_mux[] = {
3434 SSI_SDATA9_MARK,
3435 };
3436
3437 static const unsigned int ssi9_ctrl_a_pins[] = {
3438 /* SCK, WS */
3439 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3440 };
3441
3442 static const unsigned int ssi9_ctrl_a_mux[] = {
3443 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3444 };
3445
3446 static const unsigned int ssi9_ctrl_b_pins[] = {
3447 /* SCK, WS */
3448 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3449 };
3450
3451 static const unsigned int ssi9_ctrl_b_mux[] = {
3452 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3453 };
3454
3455 /* - TMU -------------------------------------------------------------------- */
3456 static const unsigned int tmu_tclk1_a_pins[] = {
3457 /* TCLK */
3458 RCAR_GP_PIN(3, 12),
3459 };
3460
3461 static const unsigned int tmu_tclk1_a_mux[] = {
3462 TCLK1_A_MARK,
3463 };
3464
3465 static const unsigned int tmu_tclk1_b_pins[] = {
3466 /* TCLK */
3467 RCAR_GP_PIN(5, 17),
3468 };
3469
3470 static const unsigned int tmu_tclk1_b_mux[] = {
3471 TCLK1_B_MARK,
3472 };
3473
3474 static const unsigned int tmu_tclk2_a_pins[] = {
3475 /* TCLK */
3476 RCAR_GP_PIN(3, 13),
3477 };
3478
3479 static const unsigned int tmu_tclk2_a_mux[] = {
3480 TCLK2_A_MARK,
3481 };
3482
3483 static const unsigned int tmu_tclk2_b_pins[] = {
3484 /* TCLK */
3485 RCAR_GP_PIN(5, 18),
3486 };
3487
3488 static const unsigned int tmu_tclk2_b_mux[] = {
3489 TCLK2_B_MARK,
3490 };
3491
3492 /* - USB0 ------------------------------------------------------------------- */
3493 static const unsigned int usb0_a_pins[] = {
3494 /* PWEN, OVC */
3495 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3496 };
3497
3498 static const unsigned int usb0_a_mux[] = {
3499 USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3500 };
3501
3502 static const unsigned int usb0_b_pins[] = {
3503 /* PWEN, OVC */
3504 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3505 };
3506
3507 static const unsigned int usb0_b_mux[] = {
3508 USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3509 };
3510
3511 static const unsigned int usb0_id_pins[] = {
3512 /* ID */
3513 RCAR_GP_PIN(5, 0)
3514 };
3515
3516 static const unsigned int usb0_id_mux[] = {
3517 USB0_ID_MARK,
3518 };
3519
3520 /* - USB30 ------------------------------------------------------------------ */
3521 static const unsigned int usb30_pins[] = {
3522 /* PWEN, OVC */
3523 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3524 };
3525
3526 static const unsigned int usb30_mux[] = {
3527 USB30_PWEN_MARK, USB30_OVC_MARK,
3528 };
3529
3530 static const unsigned int usb30_id_pins[] = {
3531 /* ID */
3532 RCAR_GP_PIN(5, 0),
3533 };
3534
3535 static const unsigned int usb30_id_mux[] = {
3536 USB3HS0_ID_MARK,
3537 };
3538
3539 /* - VIN4 ------------------------------------------------------------------- */
3540 static const unsigned int vin4_data18_a_pins[] = {
3541 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3542 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3543 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3544 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3545 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3546 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3547 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3548 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3549 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3550 };
3551
3552 static const unsigned int vin4_data18_a_mux[] = {
3553 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3554 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3555 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3556 VI4_DATA10_MARK, VI4_DATA11_MARK,
3557 VI4_DATA12_MARK, VI4_DATA13_MARK,
3558 VI4_DATA14_MARK, VI4_DATA15_MARK,
3559 VI4_DATA18_MARK, VI4_DATA19_MARK,
3560 VI4_DATA20_MARK, VI4_DATA21_MARK,
3561 VI4_DATA22_MARK, VI4_DATA23_MARK,
3562 };
3563
3564 static const union vin_data vin4_data_a_pins = {
3565 .data24 = {
3566 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3567 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
3568 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3569 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3570 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3571 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3572 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3573 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3574 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3575 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3576 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3577 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3578 },
3579 };
3580
3581 static const union vin_data vin4_data_a_mux = {
3582 .data24 = {
3583 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3584 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3585 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3586 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3587 VI4_DATA8_MARK, VI4_DATA9_MARK,
3588 VI4_DATA10_MARK, VI4_DATA11_MARK,
3589 VI4_DATA12_MARK, VI4_DATA13_MARK,
3590 VI4_DATA14_MARK, VI4_DATA15_MARK,
3591 VI4_DATA16_MARK, VI4_DATA17_MARK,
3592 VI4_DATA18_MARK, VI4_DATA19_MARK,
3593 VI4_DATA20_MARK, VI4_DATA21_MARK,
3594 VI4_DATA22_MARK, VI4_DATA23_MARK,
3595 },
3596 };
3597
3598 static const unsigned int vin4_data18_b_pins[] = {
3599 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3600 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3601 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3602 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3603 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3604 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3605 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3606 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3607 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3608 };
3609
3610 static const unsigned int vin4_data18_b_mux[] = {
3611 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3612 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3613 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3614 VI4_DATA10_MARK, VI4_DATA11_MARK,
3615 VI4_DATA12_MARK, VI4_DATA13_MARK,
3616 VI4_DATA14_MARK, VI4_DATA15_MARK,
3617 VI4_DATA18_MARK, VI4_DATA19_MARK,
3618 VI4_DATA20_MARK, VI4_DATA21_MARK,
3619 VI4_DATA22_MARK, VI4_DATA23_MARK,
3620 };
3621
3622 static const union vin_data vin4_data_b_pins = {
3623 .data24 = {
3624 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3625 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3626 RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3627 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3628 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3629 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3630 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
3631 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3632 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
3633 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3634 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3635 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3636 },
3637 };
3638
3639 static const union vin_data vin4_data_b_mux = {
3640 .data24 = {
3641 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3642 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3643 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3644 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3645 VI4_DATA8_MARK, VI4_DATA9_MARK,
3646 VI4_DATA10_MARK, VI4_DATA11_MARK,
3647 VI4_DATA12_MARK, VI4_DATA13_MARK,
3648 VI4_DATA14_MARK, VI4_DATA15_MARK,
3649 VI4_DATA16_MARK, VI4_DATA17_MARK,
3650 VI4_DATA18_MARK, VI4_DATA19_MARK,
3651 VI4_DATA20_MARK, VI4_DATA21_MARK,
3652 VI4_DATA22_MARK, VI4_DATA23_MARK,
3653 },
3654 };
3655
3656 static const unsigned int vin4_sync_pins[] = {
3657 /* HSYNC, VSYNC */
3658 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3659 };
3660
3661 static const unsigned int vin4_sync_mux[] = {
3662 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3663 };
3664
3665 static const unsigned int vin4_field_pins[] = {
3666 RCAR_GP_PIN(2, 23),
3667 };
3668
3669 static const unsigned int vin4_field_mux[] = {
3670 VI4_FIELD_MARK,
3671 };
3672
3673 static const unsigned int vin4_clkenb_pins[] = {
3674 RCAR_GP_PIN(1, 2),
3675 };
3676
3677 static const unsigned int vin4_clkenb_mux[] = {
3678 VI4_CLKENB_MARK,
3679 };
3680
3681 static const unsigned int vin4_clk_pins[] = {
3682 RCAR_GP_PIN(2, 22),
3683 };
3684
3685 static const unsigned int vin4_clk_mux[] = {
3686 VI4_CLK_MARK,
3687 };
3688
3689 /* - VIN5 ------------------------------------------------------------------- */
3690 static const union vin_data16 vin5_data_a_pins = {
3691 .data16 = {
3692 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
3693 RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3694 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3695 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3696 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3697 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
3698 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
3699 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3700 },
3701 };
3702
3703 static const union vin_data16 vin5_data_a_mux = {
3704 .data16 = {
3705 VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
3706 VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
3707 VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
3708 VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
3709 VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
3710 VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3711 VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3712 VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3713 },
3714 };
3715
3716 static const unsigned int vin5_data8_b_pins[] = {
3717 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3718 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
3719 RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3720 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3721 };
3722
3723 static const unsigned int vin5_data8_b_mux[] = {
3724 VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
3725 VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
3726 VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
3727 VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
3728 };
3729
3730 static const unsigned int vin5_sync_a_pins[] = {
3731 /* HSYNC_N, VSYNC_N */
3732 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3733 };
3734
3735 static const unsigned int vin5_sync_a_mux[] = {
3736 VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3737 };
3738
3739 static const unsigned int vin5_field_a_pins[] = {
3740 RCAR_GP_PIN(1, 10),
3741 };
3742
3743 static const unsigned int vin5_field_a_mux[] = {
3744 VI5_FIELD_A_MARK,
3745 };
3746
3747 static const unsigned int vin5_clkenb_a_pins[] = {
3748 RCAR_GP_PIN(0, 1),
3749 };
3750
3751 static const unsigned int vin5_clkenb_a_mux[] = {
3752 VI5_CLKENB_A_MARK,
3753 };
3754
3755 static const unsigned int vin5_clk_a_pins[] = {
3756 RCAR_GP_PIN(1, 0),
3757 };
3758
3759 static const unsigned int vin5_clk_a_mux[] = {
3760 VI5_CLK_A_MARK,
3761 };
3762
3763 static const unsigned int vin5_clk_b_pins[] = {
3764 RCAR_GP_PIN(2, 22),
3765 };
3766
3767 static const unsigned int vin5_clk_b_mux[] = {
3768 VI5_CLK_B_MARK,
3769 };
3770
3771 static const struct {
3772 struct sh_pfc_pin_group common[245];
3773 struct sh_pfc_pin_group automotive[23];
3774 } pinmux_groups = {
3775 .common = {
3776 SH_PFC_PIN_GROUP(audio_clk_a),
3777 SH_PFC_PIN_GROUP(audio_clk_b_a),
3778 SH_PFC_PIN_GROUP(audio_clk_b_b),
3779 SH_PFC_PIN_GROUP(audio_clk_b_c),
3780 SH_PFC_PIN_GROUP(audio_clk_c_a),
3781 SH_PFC_PIN_GROUP(audio_clk_c_b),
3782 SH_PFC_PIN_GROUP(audio_clk_c_c),
3783 SH_PFC_PIN_GROUP(audio_clkout_a),
3784 SH_PFC_PIN_GROUP(audio_clkout_b),
3785 SH_PFC_PIN_GROUP(audio_clkout1_a),
3786 SH_PFC_PIN_GROUP(audio_clkout1_b),
3787 SH_PFC_PIN_GROUP(audio_clkout1_c),
3788 SH_PFC_PIN_GROUP(audio_clkout2_a),
3789 SH_PFC_PIN_GROUP(audio_clkout2_b),
3790 SH_PFC_PIN_GROUP(audio_clkout2_c),
3791 SH_PFC_PIN_GROUP(audio_clkout3_a),
3792 SH_PFC_PIN_GROUP(audio_clkout3_b),
3793 SH_PFC_PIN_GROUP(audio_clkout3_c),
3794 SH_PFC_PIN_GROUP(avb_link),
3795 SH_PFC_PIN_GROUP(avb_magic),
3796 SH_PFC_PIN_GROUP(avb_phy_int),
3797 SH_PFC_PIN_GROUP(avb_mii),
3798 SH_PFC_PIN_GROUP(avb_avtp_pps),
3799 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3800 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3801 SH_PFC_PIN_GROUP(can0_data),
3802 SH_PFC_PIN_GROUP(can1_data),
3803 SH_PFC_PIN_GROUP(can_clk),
3804 SH_PFC_PIN_GROUP(du_rgb666),
3805 SH_PFC_PIN_GROUP(du_rgb888),
3806 SH_PFC_PIN_GROUP(du_clk_in_0),
3807 SH_PFC_PIN_GROUP(du_clk_in_1),
3808 SH_PFC_PIN_GROUP(du_clk_out_0),
3809 SH_PFC_PIN_GROUP(du_sync),
3810 SH_PFC_PIN_GROUP(du_disp_cde),
3811 SH_PFC_PIN_GROUP(du_cde),
3812 SH_PFC_PIN_GROUP(du_disp),
3813 SH_PFC_PIN_GROUP(hscif0_data_a),
3814 SH_PFC_PIN_GROUP(hscif0_clk_a),
3815 SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3816 SH_PFC_PIN_GROUP(hscif0_data_b),
3817 SH_PFC_PIN_GROUP(hscif0_clk_b),
3818 SH_PFC_PIN_GROUP(hscif1_data_a),
3819 SH_PFC_PIN_GROUP(hscif1_clk_a),
3820 SH_PFC_PIN_GROUP(hscif1_data_b),
3821 SH_PFC_PIN_GROUP(hscif1_clk_b),
3822 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3823 SH_PFC_PIN_GROUP(hscif2_data_a),
3824 SH_PFC_PIN_GROUP(hscif2_clk_a),
3825 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3826 SH_PFC_PIN_GROUP(hscif2_data_b),
3827 SH_PFC_PIN_GROUP(hscif3_data_a),
3828 SH_PFC_PIN_GROUP(hscif3_data_b),
3829 SH_PFC_PIN_GROUP(hscif3_clk_b),
3830 SH_PFC_PIN_GROUP(hscif3_data_c),
3831 SH_PFC_PIN_GROUP(hscif3_clk_c),
3832 SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3833 SH_PFC_PIN_GROUP(hscif3_data_d),
3834 SH_PFC_PIN_GROUP(hscif3_data_e),
3835 SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3836 SH_PFC_PIN_GROUP(hscif4_data_a),
3837 SH_PFC_PIN_GROUP(hscif4_clk_a),
3838 SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3839 SH_PFC_PIN_GROUP(hscif4_data_b),
3840 SH_PFC_PIN_GROUP(hscif4_clk_b),
3841 SH_PFC_PIN_GROUP(hscif4_data_c),
3842 SH_PFC_PIN_GROUP(hscif4_data_d),
3843 SH_PFC_PIN_GROUP(hscif4_data_e),
3844 SH_PFC_PIN_GROUP(i2c1_a),
3845 SH_PFC_PIN_GROUP(i2c1_b),
3846 SH_PFC_PIN_GROUP(i2c1_c),
3847 SH_PFC_PIN_GROUP(i2c1_d),
3848 SH_PFC_PIN_GROUP(i2c2_a),
3849 SH_PFC_PIN_GROUP(i2c2_b),
3850 SH_PFC_PIN_GROUP(i2c2_c),
3851 SH_PFC_PIN_GROUP(i2c2_d),
3852 SH_PFC_PIN_GROUP(i2c2_e),
3853 SH_PFC_PIN_GROUP(i2c4),
3854 SH_PFC_PIN_GROUP(i2c5),
3855 SH_PFC_PIN_GROUP(i2c6_a),
3856 SH_PFC_PIN_GROUP(i2c6_b),
3857 SH_PFC_PIN_GROUP(i2c7_a),
3858 SH_PFC_PIN_GROUP(i2c7_b),
3859 SH_PFC_PIN_GROUP(intc_ex_irq0),
3860 SH_PFC_PIN_GROUP(intc_ex_irq1),
3861 SH_PFC_PIN_GROUP(intc_ex_irq2),
3862 SH_PFC_PIN_GROUP(intc_ex_irq3),
3863 SH_PFC_PIN_GROUP(intc_ex_irq4),
3864 SH_PFC_PIN_GROUP(intc_ex_irq5),
3865 SH_PFC_PIN_GROUP(msiof0_clk),
3866 SH_PFC_PIN_GROUP(msiof0_sync),
3867 SH_PFC_PIN_GROUP(msiof0_ss1),
3868 SH_PFC_PIN_GROUP(msiof0_ss2),
3869 SH_PFC_PIN_GROUP(msiof0_txd),
3870 SH_PFC_PIN_GROUP(msiof0_rxd),
3871 SH_PFC_PIN_GROUP(msiof1_clk),
3872 SH_PFC_PIN_GROUP(msiof1_sync),
3873 SH_PFC_PIN_GROUP(msiof1_ss1),
3874 SH_PFC_PIN_GROUP(msiof1_ss2),
3875 SH_PFC_PIN_GROUP(msiof1_txd),
3876 SH_PFC_PIN_GROUP(msiof1_rxd),
3877 SH_PFC_PIN_GROUP(msiof2_clk_a),
3878 SH_PFC_PIN_GROUP(msiof2_sync_a),
3879 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3880 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3881 SH_PFC_PIN_GROUP(msiof2_txd_a),
3882 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3883 SH_PFC_PIN_GROUP(msiof2_clk_b),
3884 SH_PFC_PIN_GROUP(msiof2_sync_b),
3885 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3886 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3887 SH_PFC_PIN_GROUP(msiof2_txd_b),
3888 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3889 SH_PFC_PIN_GROUP(msiof3_clk_a),
3890 SH_PFC_PIN_GROUP(msiof3_sync_a),
3891 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3892 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3893 SH_PFC_PIN_GROUP(msiof3_txd_a),
3894 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3895 SH_PFC_PIN_GROUP(msiof3_clk_b),
3896 SH_PFC_PIN_GROUP(msiof3_sync_b),
3897 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3898 SH_PFC_PIN_GROUP(msiof3_txd_b),
3899 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3900 SH_PFC_PIN_GROUP(pwm0_a),
3901 SH_PFC_PIN_GROUP(pwm0_b),
3902 SH_PFC_PIN_GROUP(pwm1_a),
3903 SH_PFC_PIN_GROUP(pwm1_b),
3904 SH_PFC_PIN_GROUP(pwm2_a),
3905 SH_PFC_PIN_GROUP(pwm2_b),
3906 SH_PFC_PIN_GROUP(pwm2_c),
3907 SH_PFC_PIN_GROUP(pwm3_a),
3908 SH_PFC_PIN_GROUP(pwm3_b),
3909 SH_PFC_PIN_GROUP(pwm3_c),
3910 SH_PFC_PIN_GROUP(pwm4_a),
3911 SH_PFC_PIN_GROUP(pwm4_b),
3912 SH_PFC_PIN_GROUP(pwm5_a),
3913 SH_PFC_PIN_GROUP(pwm5_b),
3914 SH_PFC_PIN_GROUP(pwm6_a),
3915 SH_PFC_PIN_GROUP(pwm6_b),
3916 SH_PFC_PIN_GROUP(scif0_data_a),
3917 SH_PFC_PIN_GROUP(scif0_clk_a),
3918 SH_PFC_PIN_GROUP(scif0_ctrl_a),
3919 SH_PFC_PIN_GROUP(scif0_data_b),
3920 SH_PFC_PIN_GROUP(scif0_clk_b),
3921 SH_PFC_PIN_GROUP(scif1_data),
3922 SH_PFC_PIN_GROUP(scif1_clk),
3923 SH_PFC_PIN_GROUP(scif1_ctrl),
3924 SH_PFC_PIN_GROUP(scif2_data_a),
3925 SH_PFC_PIN_GROUP(scif2_clk_a),
3926 SH_PFC_PIN_GROUP(scif2_data_b),
3927 SH_PFC_PIN_GROUP(scif3_data_a),
3928 SH_PFC_PIN_GROUP(scif3_clk_a),
3929 SH_PFC_PIN_GROUP(scif3_ctrl_a),
3930 SH_PFC_PIN_GROUP(scif3_data_b),
3931 SH_PFC_PIN_GROUP(scif3_data_c),
3932 SH_PFC_PIN_GROUP(scif3_clk_c),
3933 SH_PFC_PIN_GROUP(scif4_data_a),
3934 SH_PFC_PIN_GROUP(scif4_clk_a),
3935 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3936 SH_PFC_PIN_GROUP(scif4_data_b),
3937 SH_PFC_PIN_GROUP(scif4_clk_b),
3938 SH_PFC_PIN_GROUP(scif4_data_c),
3939 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3940 SH_PFC_PIN_GROUP(scif5_data_a),
3941 SH_PFC_PIN_GROUP(scif5_clk_a),
3942 SH_PFC_PIN_GROUP(scif5_data_b),
3943 SH_PFC_PIN_GROUP(scif5_data_c),
3944 SH_PFC_PIN_GROUP(scif_clk_a),
3945 SH_PFC_PIN_GROUP(scif_clk_b),
3946 SH_PFC_PIN_GROUP(sdhi0_data1),
3947 SH_PFC_PIN_GROUP(sdhi0_data4),
3948 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3949 SH_PFC_PIN_GROUP(sdhi0_cd),
3950 SH_PFC_PIN_GROUP(sdhi0_wp),
3951 SH_PFC_PIN_GROUP(sdhi1_data1),
3952 SH_PFC_PIN_GROUP(sdhi1_data4),
3953 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3954 SH_PFC_PIN_GROUP(sdhi1_cd),
3955 SH_PFC_PIN_GROUP(sdhi1_wp),
3956 SH_PFC_PIN_GROUP(sdhi3_data1),
3957 SH_PFC_PIN_GROUP(sdhi3_data4),
3958 SH_PFC_PIN_GROUP(sdhi3_data8),
3959 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3960 SH_PFC_PIN_GROUP(sdhi3_cd),
3961 SH_PFC_PIN_GROUP(sdhi3_wp),
3962 SH_PFC_PIN_GROUP(sdhi3_ds),
3963 SH_PFC_PIN_GROUP(ssi0_data),
3964 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3965 SH_PFC_PIN_GROUP(ssi1_data),
3966 SH_PFC_PIN_GROUP(ssi1_ctrl),
3967 SH_PFC_PIN_GROUP(ssi2_data),
3968 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3969 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3970 SH_PFC_PIN_GROUP(ssi3_data),
3971 SH_PFC_PIN_GROUP(ssi349_ctrl),
3972 SH_PFC_PIN_GROUP(ssi4_data),
3973 SH_PFC_PIN_GROUP(ssi4_ctrl),
3974 SH_PFC_PIN_GROUP(ssi5_data),
3975 SH_PFC_PIN_GROUP(ssi5_ctrl),
3976 SH_PFC_PIN_GROUP(ssi6_data),
3977 SH_PFC_PIN_GROUP(ssi6_ctrl),
3978 SH_PFC_PIN_GROUP(ssi7_data),
3979 SH_PFC_PIN_GROUP(ssi78_ctrl),
3980 SH_PFC_PIN_GROUP(ssi8_data),
3981 SH_PFC_PIN_GROUP(ssi9_data),
3982 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3983 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3984 SH_PFC_PIN_GROUP(tmu_tclk1_a),
3985 SH_PFC_PIN_GROUP(tmu_tclk1_b),
3986 SH_PFC_PIN_GROUP(tmu_tclk2_a),
3987 SH_PFC_PIN_GROUP(tmu_tclk2_b),
3988 SH_PFC_PIN_GROUP(usb0_a),
3989 SH_PFC_PIN_GROUP(usb0_b),
3990 SH_PFC_PIN_GROUP(usb0_id),
3991 SH_PFC_PIN_GROUP(usb30),
3992 SH_PFC_PIN_GROUP(usb30_id),
3993 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
3994 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
3995 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
3996 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
3997 SH_PFC_PIN_GROUP(vin4_data18_a),
3998 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
3999 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4000 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4001 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4002 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4003 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
4004 SH_PFC_PIN_GROUP(vin4_data18_b),
4005 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4006 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
4007 SH_PFC_PIN_GROUP(vin4_sync),
4008 SH_PFC_PIN_GROUP(vin4_field),
4009 SH_PFC_PIN_GROUP(vin4_clkenb),
4010 SH_PFC_PIN_GROUP(vin4_clk),
4011 VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
4012 VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
4013 VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
4014 VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
4015 SH_PFC_PIN_GROUP(vin5_data8_b),
4016 SH_PFC_PIN_GROUP(vin5_sync_a),
4017 SH_PFC_PIN_GROUP(vin5_field_a),
4018 SH_PFC_PIN_GROUP(vin5_clkenb_a),
4019 SH_PFC_PIN_GROUP(vin5_clk_a),
4020 SH_PFC_PIN_GROUP(vin5_clk_b),
4021 },
4022 .automotive = {
4023 SH_PFC_PIN_GROUP(canfd0_data),
4024 SH_PFC_PIN_GROUP(canfd1_data),
4025 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4026 SH_PFC_PIN_GROUP(drif0_data0_a),
4027 SH_PFC_PIN_GROUP(drif0_data1_a),
4028 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4029 SH_PFC_PIN_GROUP(drif0_data0_b),
4030 SH_PFC_PIN_GROUP(drif0_data1_b),
4031 SH_PFC_PIN_GROUP(drif1_ctrl),
4032 SH_PFC_PIN_GROUP(drif1_data0),
4033 SH_PFC_PIN_GROUP(drif1_data1),
4034 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4035 SH_PFC_PIN_GROUP(drif2_data0_a),
4036 SH_PFC_PIN_GROUP(drif2_data1_a),
4037 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4038 SH_PFC_PIN_GROUP(drif2_data0_b),
4039 SH_PFC_PIN_GROUP(drif2_data1_b),
4040 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4041 SH_PFC_PIN_GROUP(drif3_data0_a),
4042 SH_PFC_PIN_GROUP(drif3_data1_a),
4043 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4044 SH_PFC_PIN_GROUP(drif3_data0_b),
4045 SH_PFC_PIN_GROUP(drif3_data1_b),
4046 }
4047 };
4048
4049 static const char * const audio_clk_groups[] = {
4050 "audio_clk_a",
4051 "audio_clk_b_a",
4052 "audio_clk_b_b",
4053 "audio_clk_b_c",
4054 "audio_clk_c_a",
4055 "audio_clk_c_b",
4056 "audio_clk_c_c",
4057 "audio_clkout_a",
4058 "audio_clkout_b",
4059 "audio_clkout1_a",
4060 "audio_clkout1_b",
4061 "audio_clkout1_c",
4062 "audio_clkout2_a",
4063 "audio_clkout2_b",
4064 "audio_clkout2_c",
4065 "audio_clkout3_a",
4066 "audio_clkout3_b",
4067 "audio_clkout3_c",
4068 };
4069
4070 static const char * const avb_groups[] = {
4071 "avb_link",
4072 "avb_magic",
4073 "avb_phy_int",
4074 "avb_mii",
4075 "avb_avtp_pps",
4076 "avb_avtp_match_a",
4077 "avb_avtp_capture_a",
4078 };
4079
4080 static const char * const can0_groups[] = {
4081 "can0_data",
4082 };
4083
4084 static const char * const can1_groups[] = {
4085 "can1_data",
4086 };
4087
4088 static const char * const can_clk_groups[] = {
4089 "can_clk",
4090 };
4091
4092 static const char * const canfd0_groups[] = {
4093 "canfd0_data",
4094 };
4095
4096 static const char * const canfd1_groups[] = {
4097 "canfd1_data",
4098 };
4099
4100 static const char * const drif0_groups[] = {
4101 "drif0_ctrl_a",
4102 "drif0_data0_a",
4103 "drif0_data1_a",
4104 "drif0_ctrl_b",
4105 "drif0_data0_b",
4106 "drif0_data1_b",
4107 };
4108
4109 static const char * const drif1_groups[] = {
4110 "drif1_ctrl",
4111 "drif1_data0",
4112 "drif1_data1",
4113 };
4114
4115 static const char * const drif2_groups[] = {
4116 "drif2_ctrl_a",
4117 "drif2_data0_a",
4118 "drif2_data1_a",
4119 "drif2_ctrl_b",
4120 "drif2_data0_b",
4121 "drif2_data1_b",
4122 };
4123
4124 static const char * const drif3_groups[] = {
4125 "drif3_ctrl_a",
4126 "drif3_data0_a",
4127 "drif3_data1_a",
4128 "drif3_ctrl_b",
4129 "drif3_data0_b",
4130 "drif3_data1_b",
4131 };
4132
4133 static const char * const du_groups[] = {
4134 "du_rgb666",
4135 "du_rgb888",
4136 "du_clk_in_0",
4137 "du_clk_in_1",
4138 "du_clk_out_0",
4139 "du_sync",
4140 "du_disp_cde",
4141 "du_cde",
4142 "du_disp",
4143 };
4144
4145 static const char * const hscif0_groups[] = {
4146 "hscif0_data_a",
4147 "hscif0_clk_a",
4148 "hscif0_ctrl_a",
4149 "hscif0_data_b",
4150 "hscif0_clk_b",
4151 };
4152
4153 static const char * const hscif1_groups[] = {
4154 "hscif1_data_a",
4155 "hscif1_clk_a",
4156 "hscif1_data_b",
4157 "hscif1_clk_b",
4158 "hscif1_ctrl_b",
4159 };
4160
4161 static const char * const hscif2_groups[] = {
4162 "hscif2_data_a",
4163 "hscif2_clk_a",
4164 "hscif2_ctrl_a",
4165 "hscif2_data_b",
4166 };
4167
4168 static const char * const hscif3_groups[] = {
4169 "hscif3_data_a",
4170 "hscif3_data_b",
4171 "hscif3_clk_b",
4172 "hscif3_data_c",
4173 "hscif3_clk_c",
4174 "hscif3_ctrl_c",
4175 "hscif3_data_d",
4176 "hscif3_data_e",
4177 "hscif3_ctrl_e",
4178 };
4179
4180 static const char * const hscif4_groups[] = {
4181 "hscif4_data_a",
4182 "hscif4_clk_a",
4183 "hscif4_ctrl_a",
4184 "hscif4_data_b",
4185 "hscif4_clk_b",
4186 "hscif4_data_c",
4187 "hscif4_data_d",
4188 "hscif4_data_e",
4189 };
4190
4191 static const char * const i2c1_groups[] = {
4192 "i2c1_a",
4193 "i2c1_b",
4194 "i2c1_c",
4195 "i2c1_d",
4196 };
4197
4198 static const char * const i2c2_groups[] = {
4199 "i2c2_a",
4200 "i2c2_b",
4201 "i2c2_c",
4202 "i2c2_d",
4203 "i2c2_e",
4204 };
4205
4206 static const char * const i2c4_groups[] = {
4207 "i2c4",
4208 };
4209
4210 static const char * const i2c5_groups[] = {
4211 "i2c5",
4212 };
4213
4214 static const char * const i2c6_groups[] = {
4215 "i2c6_a",
4216 "i2c6_b",
4217 };
4218
4219 static const char * const i2c7_groups[] = {
4220 "i2c7_a",
4221 "i2c7_b",
4222 };
4223
4224 static const char * const intc_ex_groups[] = {
4225 "intc_ex_irq0",
4226 "intc_ex_irq1",
4227 "intc_ex_irq2",
4228 "intc_ex_irq3",
4229 "intc_ex_irq4",
4230 "intc_ex_irq5",
4231 };
4232
4233 static const char * const msiof0_groups[] = {
4234 "msiof0_clk",
4235 "msiof0_sync",
4236 "msiof0_ss1",
4237 "msiof0_ss2",
4238 "msiof0_txd",
4239 "msiof0_rxd",
4240 };
4241
4242 static const char * const msiof1_groups[] = {
4243 "msiof1_clk",
4244 "msiof1_sync",
4245 "msiof1_ss1",
4246 "msiof1_ss2",
4247 "msiof1_txd",
4248 "msiof1_rxd",
4249 };
4250
4251 static const char * const msiof2_groups[] = {
4252 "msiof2_clk_a",
4253 "msiof2_sync_a",
4254 "msiof2_ss1_a",
4255 "msiof2_ss2_a",
4256 "msiof2_txd_a",
4257 "msiof2_rxd_a",
4258 "msiof2_clk_b",
4259 "msiof2_sync_b",
4260 "msiof2_ss1_b",
4261 "msiof2_ss2_b",
4262 "msiof2_txd_b",
4263 "msiof2_rxd_b",
4264 };
4265
4266 static const char * const msiof3_groups[] = {
4267 "msiof3_clk_a",
4268 "msiof3_sync_a",
4269 "msiof3_ss1_a",
4270 "msiof3_ss2_a",
4271 "msiof3_txd_a",
4272 "msiof3_rxd_a",
4273 "msiof3_clk_b",
4274 "msiof3_sync_b",
4275 "msiof3_ss1_b",
4276 "msiof3_txd_b",
4277 "msiof3_rxd_b",
4278 };
4279
4280 static const char * const pwm0_groups[] = {
4281 "pwm0_a",
4282 "pwm0_b",
4283 };
4284
4285 static const char * const pwm1_groups[] = {
4286 "pwm1_a",
4287 "pwm1_b",
4288 };
4289
4290 static const char * const pwm2_groups[] = {
4291 "pwm2_a",
4292 "pwm2_b",
4293 "pwm2_c",
4294 };
4295
4296 static const char * const pwm3_groups[] = {
4297 "pwm3_a",
4298 "pwm3_b",
4299 "pwm3_c",
4300 };
4301
4302 static const char * const pwm4_groups[] = {
4303 "pwm4_a",
4304 "pwm4_b",
4305 };
4306
4307 static const char * const pwm5_groups[] = {
4308 "pwm5_a",
4309 "pwm5_b",
4310 };
4311
4312 static const char * const pwm6_groups[] = {
4313 "pwm6_a",
4314 "pwm6_b",
4315 };
4316
4317 static const char * const scif0_groups[] = {
4318 "scif0_data_a",
4319 "scif0_clk_a",
4320 "scif0_ctrl_a",
4321 "scif0_data_b",
4322 "scif0_clk_b",
4323 };
4324
4325 static const char * const scif1_groups[] = {
4326 "scif1_data",
4327 "scif1_clk",
4328 "scif1_ctrl",
4329 };
4330
4331 static const char * const scif2_groups[] = {
4332 "scif2_data_a",
4333 "scif2_clk_a",
4334 "scif2_data_b",
4335 };
4336
4337 static const char * const scif3_groups[] = {
4338 "scif3_data_a",
4339 "scif3_clk_a",
4340 "scif3_ctrl_a",
4341 "scif3_data_b",
4342 "scif3_data_c",
4343 "scif3_clk_c",
4344 };
4345
4346 static const char * const scif4_groups[] = {
4347 "scif4_data_a",
4348 "scif4_clk_a",
4349 "scif4_ctrl_a",
4350 "scif4_data_b",
4351 "scif4_clk_b",
4352 "scif4_data_c",
4353 "scif4_ctrl_c",
4354 };
4355
4356 static const char * const scif5_groups[] = {
4357 "scif5_data_a",
4358 "scif5_clk_a",
4359 "scif5_data_b",
4360 "scif5_data_c",
4361 };
4362
4363 static const char * const scif_clk_groups[] = {
4364 "scif_clk_a",
4365 "scif_clk_b",
4366 };
4367
4368 static const char * const sdhi0_groups[] = {
4369 "sdhi0_data1",
4370 "sdhi0_data4",
4371 "sdhi0_ctrl",
4372 "sdhi0_cd",
4373 "sdhi0_wp",
4374 };
4375
4376 static const char * const sdhi1_groups[] = {
4377 "sdhi1_data1",
4378 "sdhi1_data4",
4379 "sdhi1_ctrl",
4380 "sdhi1_cd",
4381 "sdhi1_wp",
4382 };
4383
4384 static const char * const sdhi3_groups[] = {
4385 "sdhi3_data1",
4386 "sdhi3_data4",
4387 "sdhi3_data8",
4388 "sdhi3_ctrl",
4389 "sdhi3_cd",
4390 "sdhi3_wp",
4391 "sdhi3_ds",
4392 };
4393
4394 static const char * const ssi_groups[] = {
4395 "ssi0_data",
4396 "ssi01239_ctrl",
4397 "ssi1_data",
4398 "ssi1_ctrl",
4399 "ssi2_data",
4400 "ssi2_ctrl_a",
4401 "ssi2_ctrl_b",
4402 "ssi3_data",
4403 "ssi349_ctrl",
4404 "ssi4_data",
4405 "ssi4_ctrl",
4406 "ssi5_data",
4407 "ssi5_ctrl",
4408 "ssi6_data",
4409 "ssi6_ctrl",
4410 "ssi7_data",
4411 "ssi78_ctrl",
4412 "ssi8_data",
4413 "ssi9_data",
4414 "ssi9_ctrl_a",
4415 "ssi9_ctrl_b",
4416 };
4417
4418 static const char * const tmu_groups[] = {
4419 "tmu_tclk1_a",
4420 "tmu_tclk1_b",
4421 "tmu_tclk2_a",
4422 "tmu_tclk2_b",
4423 };
4424
4425 static const char * const usb0_groups[] = {
4426 "usb0_a",
4427 "usb0_b",
4428 "usb0_id",
4429 };
4430
4431 static const char * const usb30_groups[] = {
4432 "usb30",
4433 "usb30_id",
4434 };
4435
4436 static const char * const vin4_groups[] = {
4437 "vin4_data8_a",
4438 "vin4_data10_a",
4439 "vin4_data12_a",
4440 "vin4_data16_a",
4441 "vin4_data18_a",
4442 "vin4_data20_a",
4443 "vin4_data24_a",
4444 "vin4_data8_b",
4445 "vin4_data10_b",
4446 "vin4_data12_b",
4447 "vin4_data16_b",
4448 "vin4_data18_b",
4449 "vin4_data20_b",
4450 "vin4_data24_b",
4451 "vin4_sync",
4452 "vin4_field",
4453 "vin4_clkenb",
4454 "vin4_clk",
4455 };
4456
4457 static const char * const vin5_groups[] = {
4458 "vin5_data8_a",
4459 "vin5_data10_a",
4460 "vin5_data12_a",
4461 "vin5_data16_a",
4462 "vin5_data8_b",
4463 "vin5_sync_a",
4464 "vin5_field_a",
4465 "vin5_clkenb_a",
4466 "vin5_clk_a",
4467 "vin5_clk_b",
4468 };
4469
4470 static const struct {
4471 struct sh_pfc_function common[45];
4472 struct sh_pfc_function automotive[6];
4473 } pinmux_functions = {
4474 .common = {
4475 SH_PFC_FUNCTION(audio_clk),
4476 SH_PFC_FUNCTION(avb),
4477 SH_PFC_FUNCTION(can0),
4478 SH_PFC_FUNCTION(can1),
4479 SH_PFC_FUNCTION(can_clk),
4480 SH_PFC_FUNCTION(du),
4481 SH_PFC_FUNCTION(hscif0),
4482 SH_PFC_FUNCTION(hscif1),
4483 SH_PFC_FUNCTION(hscif2),
4484 SH_PFC_FUNCTION(hscif3),
4485 SH_PFC_FUNCTION(hscif4),
4486 SH_PFC_FUNCTION(i2c1),
4487 SH_PFC_FUNCTION(i2c2),
4488 SH_PFC_FUNCTION(i2c4),
4489 SH_PFC_FUNCTION(i2c5),
4490 SH_PFC_FUNCTION(i2c6),
4491 SH_PFC_FUNCTION(i2c7),
4492 SH_PFC_FUNCTION(intc_ex),
4493 SH_PFC_FUNCTION(msiof0),
4494 SH_PFC_FUNCTION(msiof1),
4495 SH_PFC_FUNCTION(msiof2),
4496 SH_PFC_FUNCTION(msiof3),
4497 SH_PFC_FUNCTION(pwm0),
4498 SH_PFC_FUNCTION(pwm1),
4499 SH_PFC_FUNCTION(pwm2),
4500 SH_PFC_FUNCTION(pwm3),
4501 SH_PFC_FUNCTION(pwm4),
4502 SH_PFC_FUNCTION(pwm5),
4503 SH_PFC_FUNCTION(pwm6),
4504 SH_PFC_FUNCTION(scif0),
4505 SH_PFC_FUNCTION(scif1),
4506 SH_PFC_FUNCTION(scif2),
4507 SH_PFC_FUNCTION(scif3),
4508 SH_PFC_FUNCTION(scif4),
4509 SH_PFC_FUNCTION(scif5),
4510 SH_PFC_FUNCTION(scif_clk),
4511 SH_PFC_FUNCTION(sdhi0),
4512 SH_PFC_FUNCTION(sdhi1),
4513 SH_PFC_FUNCTION(sdhi3),
4514 SH_PFC_FUNCTION(ssi),
4515 SH_PFC_FUNCTION(tmu),
4516 SH_PFC_FUNCTION(usb0),
4517 SH_PFC_FUNCTION(usb30),
4518 SH_PFC_FUNCTION(vin4),
4519 SH_PFC_FUNCTION(vin5),
4520 },
4521 .automotive = {
4522 SH_PFC_FUNCTION(canfd0),
4523 SH_PFC_FUNCTION(canfd1),
4524 SH_PFC_FUNCTION(drif0),
4525 SH_PFC_FUNCTION(drif1),
4526 SH_PFC_FUNCTION(drif2),
4527 SH_PFC_FUNCTION(drif3),
4528 }
4529 };
4530
4531 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4532 #define F_(x, y) FN_##y
4533 #define FM(x) FN_##x
4534 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4535 0, 0,
4536 0, 0,
4537 0, 0,
4538 0, 0,
4539 0, 0,
4540 0, 0,
4541 0, 0,
4542 0, 0,
4543 0, 0,
4544 0, 0,
4545 0, 0,
4546 0, 0,
4547 0, 0,
4548 0, 0,
4549 GP_0_17_FN, GPSR0_17,
4550 GP_0_16_FN, GPSR0_16,
4551 GP_0_15_FN, GPSR0_15,
4552 GP_0_14_FN, GPSR0_14,
4553 GP_0_13_FN, GPSR0_13,
4554 GP_0_12_FN, GPSR0_12,
4555 GP_0_11_FN, GPSR0_11,
4556 GP_0_10_FN, GPSR0_10,
4557 GP_0_9_FN, GPSR0_9,
4558 GP_0_8_FN, GPSR0_8,
4559 GP_0_7_FN, GPSR0_7,
4560 GP_0_6_FN, GPSR0_6,
4561 GP_0_5_FN, GPSR0_5,
4562 GP_0_4_FN, GPSR0_4,
4563 GP_0_3_FN, GPSR0_3,
4564 GP_0_2_FN, GPSR0_2,
4565 GP_0_1_FN, GPSR0_1,
4566 GP_0_0_FN, GPSR0_0, }
4567 },
4568 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4569 0, 0,
4570 0, 0,
4571 0, 0,
4572 0, 0,
4573 0, 0,
4574 0, 0,
4575 0, 0,
4576 0, 0,
4577 0, 0,
4578 GP_1_22_FN, GPSR1_22,
4579 GP_1_21_FN, GPSR1_21,
4580 GP_1_20_FN, GPSR1_20,
4581 GP_1_19_FN, GPSR1_19,
4582 GP_1_18_FN, GPSR1_18,
4583 GP_1_17_FN, GPSR1_17,
4584 GP_1_16_FN, GPSR1_16,
4585 GP_1_15_FN, GPSR1_15,
4586 GP_1_14_FN, GPSR1_14,
4587 GP_1_13_FN, GPSR1_13,
4588 GP_1_12_FN, GPSR1_12,
4589 GP_1_11_FN, GPSR1_11,
4590 GP_1_10_FN, GPSR1_10,
4591 GP_1_9_FN, GPSR1_9,
4592 GP_1_8_FN, GPSR1_8,
4593 GP_1_7_FN, GPSR1_7,
4594 GP_1_6_FN, GPSR1_6,
4595 GP_1_5_FN, GPSR1_5,
4596 GP_1_4_FN, GPSR1_4,
4597 GP_1_3_FN, GPSR1_3,
4598 GP_1_2_FN, GPSR1_2,
4599 GP_1_1_FN, GPSR1_1,
4600 GP_1_0_FN, GPSR1_0, }
4601 },
4602 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4603 0, 0,
4604 0, 0,
4605 0, 0,
4606 0, 0,
4607 0, 0,
4608 0, 0,
4609 GP_2_25_FN, GPSR2_25,
4610 GP_2_24_FN, GPSR2_24,
4611 GP_2_23_FN, GPSR2_23,
4612 GP_2_22_FN, GPSR2_22,
4613 GP_2_21_FN, GPSR2_21,
4614 GP_2_20_FN, GPSR2_20,
4615 GP_2_19_FN, GPSR2_19,
4616 GP_2_18_FN, GPSR2_18,
4617 GP_2_17_FN, GPSR2_17,
4618 GP_2_16_FN, GPSR2_16,
4619 GP_2_15_FN, GPSR2_15,
4620 GP_2_14_FN, GPSR2_14,
4621 GP_2_13_FN, GPSR2_13,
4622 GP_2_12_FN, GPSR2_12,
4623 GP_2_11_FN, GPSR2_11,
4624 GP_2_10_FN, GPSR2_10,
4625 GP_2_9_FN, GPSR2_9,
4626 GP_2_8_FN, GPSR2_8,
4627 GP_2_7_FN, GPSR2_7,
4628 GP_2_6_FN, GPSR2_6,
4629 GP_2_5_FN, GPSR2_5,
4630 GP_2_4_FN, GPSR2_4,
4631 GP_2_3_FN, GPSR2_3,
4632 GP_2_2_FN, GPSR2_2,
4633 GP_2_1_FN, GPSR2_1,
4634 GP_2_0_FN, GPSR2_0, }
4635 },
4636 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4637 0, 0,
4638 0, 0,
4639 0, 0,
4640 0, 0,
4641 0, 0,
4642 0, 0,
4643 0, 0,
4644 0, 0,
4645 0, 0,
4646 0, 0,
4647 0, 0,
4648 0, 0,
4649 0, 0,
4650 0, 0,
4651 0, 0,
4652 0, 0,
4653 GP_3_15_FN, GPSR3_15,
4654 GP_3_14_FN, GPSR3_14,
4655 GP_3_13_FN, GPSR3_13,
4656 GP_3_12_FN, GPSR3_12,
4657 GP_3_11_FN, GPSR3_11,
4658 GP_3_10_FN, GPSR3_10,
4659 GP_3_9_FN, GPSR3_9,
4660 GP_3_8_FN, GPSR3_8,
4661 GP_3_7_FN, GPSR3_7,
4662 GP_3_6_FN, GPSR3_6,
4663 GP_3_5_FN, GPSR3_5,
4664 GP_3_4_FN, GPSR3_4,
4665 GP_3_3_FN, GPSR3_3,
4666 GP_3_2_FN, GPSR3_2,
4667 GP_3_1_FN, GPSR3_1,
4668 GP_3_0_FN, GPSR3_0, }
4669 },
4670 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4671 0, 0,
4672 0, 0,
4673 0, 0,
4674 0, 0,
4675 0, 0,
4676 0, 0,
4677 0, 0,
4678 0, 0,
4679 0, 0,
4680 0, 0,
4681 0, 0,
4682 0, 0,
4683 0, 0,
4684 0, 0,
4685 0, 0,
4686 0, 0,
4687 0, 0,
4688 0, 0,
4689 0, 0,
4690 0, 0,
4691 0, 0,
4692 GP_4_10_FN, GPSR4_10,
4693 GP_4_9_FN, GPSR4_9,
4694 GP_4_8_FN, GPSR4_8,
4695 GP_4_7_FN, GPSR4_7,
4696 GP_4_6_FN, GPSR4_6,
4697 GP_4_5_FN, GPSR4_5,
4698 GP_4_4_FN, GPSR4_4,
4699 GP_4_3_FN, GPSR4_3,
4700 GP_4_2_FN, GPSR4_2,
4701 GP_4_1_FN, GPSR4_1,
4702 GP_4_0_FN, GPSR4_0, }
4703 },
4704 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4705 0, 0,
4706 0, 0,
4707 0, 0,
4708 0, 0,
4709 0, 0,
4710 0, 0,
4711 0, 0,
4712 0, 0,
4713 0, 0,
4714 0, 0,
4715 0, 0,
4716 0, 0,
4717 GP_5_19_FN, GPSR5_19,
4718 GP_5_18_FN, GPSR5_18,
4719 GP_5_17_FN, GPSR5_17,
4720 GP_5_16_FN, GPSR5_16,
4721 GP_5_15_FN, GPSR5_15,
4722 GP_5_14_FN, GPSR5_14,
4723 GP_5_13_FN, GPSR5_13,
4724 GP_5_12_FN, GPSR5_12,
4725 GP_5_11_FN, GPSR5_11,
4726 GP_5_10_FN, GPSR5_10,
4727 GP_5_9_FN, GPSR5_9,
4728 GP_5_8_FN, GPSR5_8,
4729 GP_5_7_FN, GPSR5_7,
4730 GP_5_6_FN, GPSR5_6,
4731 GP_5_5_FN, GPSR5_5,
4732 GP_5_4_FN, GPSR5_4,
4733 GP_5_3_FN, GPSR5_3,
4734 GP_5_2_FN, GPSR5_2,
4735 GP_5_1_FN, GPSR5_1,
4736 GP_5_0_FN, GPSR5_0, }
4737 },
4738 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4739 0, 0,
4740 0, 0,
4741 0, 0,
4742 0, 0,
4743 0, 0,
4744 0, 0,
4745 0, 0,
4746 0, 0,
4747 0, 0,
4748 0, 0,
4749 0, 0,
4750 0, 0,
4751 0, 0,
4752 0, 0,
4753 GP_6_17_FN, GPSR6_17,
4754 GP_6_16_FN, GPSR6_16,
4755 GP_6_15_FN, GPSR6_15,
4756 GP_6_14_FN, GPSR6_14,
4757 GP_6_13_FN, GPSR6_13,
4758 GP_6_12_FN, GPSR6_12,
4759 GP_6_11_FN, GPSR6_11,
4760 GP_6_10_FN, GPSR6_10,
4761 GP_6_9_FN, GPSR6_9,
4762 GP_6_8_FN, GPSR6_8,
4763 GP_6_7_FN, GPSR6_7,
4764 GP_6_6_FN, GPSR6_6,
4765 GP_6_5_FN, GPSR6_5,
4766 GP_6_4_FN, GPSR6_4,
4767 GP_6_3_FN, GPSR6_3,
4768 GP_6_2_FN, GPSR6_2,
4769 GP_6_1_FN, GPSR6_1,
4770 GP_6_0_FN, GPSR6_0, }
4771 },
4772 #undef F_
4773 #undef FM
4774
4775 #define F_(x, y) x,
4776 #define FM(x) FN_##x,
4777 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4778 IP0_31_28
4779 IP0_27_24
4780 IP0_23_20
4781 IP0_19_16
4782 IP0_15_12
4783 IP0_11_8
4784 IP0_7_4
4785 IP0_3_0 }
4786 },
4787 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4788 IP1_31_28
4789 IP1_27_24
4790 IP1_23_20
4791 IP1_19_16
4792 IP1_15_12
4793 IP1_11_8
4794 IP1_7_4
4795 IP1_3_0 }
4796 },
4797 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4798 IP2_31_28
4799 IP2_27_24
4800 IP2_23_20
4801 IP2_19_16
4802 IP2_15_12
4803 IP2_11_8
4804 IP2_7_4
4805 IP2_3_0 }
4806 },
4807 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4808 IP3_31_28
4809 IP3_27_24
4810 IP3_23_20
4811 IP3_19_16
4812 IP3_15_12
4813 IP3_11_8
4814 IP3_7_4
4815 IP3_3_0 }
4816 },
4817 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4818 IP4_31_28
4819 IP4_27_24
4820 IP4_23_20
4821 IP4_19_16
4822 IP4_15_12
4823 IP4_11_8
4824 IP4_7_4
4825 IP4_3_0 }
4826 },
4827 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4828 IP5_31_28
4829 IP5_27_24
4830 IP5_23_20
4831 IP5_19_16
4832 IP5_15_12
4833 IP5_11_8
4834 IP5_7_4
4835 IP5_3_0 }
4836 },
4837 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4838 IP6_31_28
4839 IP6_27_24
4840 IP6_23_20
4841 IP6_19_16
4842 IP6_15_12
4843 IP6_11_8
4844 IP6_7_4
4845 IP6_3_0 }
4846 },
4847 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4848 IP7_31_28
4849 IP7_27_24
4850 IP7_23_20
4851 IP7_19_16
4852 IP7_15_12
4853 IP7_11_8
4854 IP7_7_4
4855 IP7_3_0 }
4856 },
4857 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4858 IP8_31_28
4859 IP8_27_24
4860 IP8_23_20
4861 IP8_19_16
4862 IP8_15_12
4863 IP8_11_8
4864 IP8_7_4
4865 IP8_3_0 }
4866 },
4867 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4868 IP9_31_28
4869 IP9_27_24
4870 IP9_23_20
4871 IP9_19_16
4872 IP9_15_12
4873 IP9_11_8
4874 IP9_7_4
4875 IP9_3_0 }
4876 },
4877 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4878 IP10_31_28
4879 IP10_27_24
4880 IP10_23_20
4881 IP10_19_16
4882 IP10_15_12
4883 IP10_11_8
4884 IP10_7_4
4885 IP10_3_0 }
4886 },
4887 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4888 IP11_31_28
4889 IP11_27_24
4890 IP11_23_20
4891 IP11_19_16
4892 IP11_15_12
4893 IP11_11_8
4894 IP11_7_4
4895 IP11_3_0 }
4896 },
4897 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4898 IP12_31_28
4899 IP12_27_24
4900 IP12_23_20
4901 IP12_19_16
4902 IP12_15_12
4903 IP12_11_8
4904 IP12_7_4
4905 IP12_3_0 }
4906 },
4907 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4908 IP13_31_28
4909 IP13_27_24
4910 IP13_23_20
4911 IP13_19_16
4912 IP13_15_12
4913 IP13_11_8
4914 IP13_7_4
4915 IP13_3_0 }
4916 },
4917 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4918 IP14_31_28
4919 IP14_27_24
4920 IP14_23_20
4921 IP14_19_16
4922 IP14_15_12
4923 IP14_11_8
4924 IP14_7_4
4925 IP14_3_0 }
4926 },
4927 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4928 IP15_31_28
4929 IP15_27_24
4930 IP15_23_20
4931 IP15_19_16
4932 IP15_15_12
4933 IP15_11_8
4934 IP15_7_4
4935 IP15_3_0 }
4936 },
4937 #undef F_
4938 #undef FM
4939
4940 #define F_(x, y) x,
4941 #define FM(x) FN_##x,
4942 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4943 1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1,
4944 1, 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2) {
4945 /* RESERVED 31 */
4946 0, 0,
4947 MOD_SEL0_30_29
4948 MOD_SEL0_28
4949 MOD_SEL0_27_26
4950 MOD_SEL0_25
4951 MOD_SEL0_24
4952 MOD_SEL0_23
4953 MOD_SEL0_22
4954 MOD_SEL0_21_20
4955 MOD_SEL0_19_18_17
4956 MOD_SEL0_16
4957 MOD_SEL0_15
4958 MOD_SEL0_14
4959 MOD_SEL0_13_12
4960 MOD_SEL0_11_10
4961 MOD_SEL0_9
4962 MOD_SEL0_8
4963 MOD_SEL0_7
4964 MOD_SEL0_6_5
4965 MOD_SEL0_4
4966 MOD_SEL0_3
4967 MOD_SEL0_2
4968 MOD_SEL0_1_0 }
4969 },
4970 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4971 1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
4972 1, 2, 2, 2, 1, 1, 2, 1, 4) {
4973 MOD_SEL1_31
4974 MOD_SEL1_30
4975 MOD_SEL1_29
4976 MOD_SEL1_28
4977 /* RESERVED 27 */
4978 0, 0,
4979 MOD_SEL1_26
4980 MOD_SEL1_25
4981 MOD_SEL1_24_23_22
4982 MOD_SEL1_21_20_19
4983 MOD_SEL1_18
4984 MOD_SEL1_17
4985 MOD_SEL1_16
4986 MOD_SEL1_15
4987 MOD_SEL1_14_13
4988 MOD_SEL1_12_11
4989 MOD_SEL1_10_9
4990 MOD_SEL1_8
4991 MOD_SEL1_7
4992 MOD_SEL1_6_5
4993 MOD_SEL1_4
4994 /* RESERVED 3, 2, 1, 0 */
4995 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
4996 },
4997 { },
4998 };
4999
5000 enum ioctrl_regs {
5001 IOCTRL30,
5002 };
5003
5004 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5005 [IOCTRL30] = { 0xe6060380, },
5006 { /* sentinel */ },
5007 };
5008
5009 static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
5010 u32 *pocctrl)
5011 {
5012 int bit = -EINVAL;
5013
5014 *pocctrl = pinmux_ioctrl_regs[IOCTRL30].reg;
5015
5016 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5017 bit = pin & 0x1f;
5018
5019 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5020 bit = (pin & 0x1f) + 19;
5021
5022 return bit;
5023 }
5024
5025 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5026 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5027 [0] = RCAR_GP_PIN(2, 23), /* RD# */
5028 [1] = RCAR_GP_PIN(2, 22), /* BS# */
5029 [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
5030 [3] = PIN_NUMBER('P', 5), /* AVB_MDC */
5031 [4] = PIN_NUMBER('P', 4), /* AVB_MDIO */
5032 [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
5033 [6] = PIN_NUMBER('N', 6), /* AVB_TD3 */
5034 [7] = PIN_NUMBER('N', 5), /* AVB_TD2 */
5035 [8] = PIN_NUMBER('N', 3), /* AVB_TD1 */
5036 [9] = PIN_NUMBER('N', 2), /* AVB_TD0 */
5037 [10] = PIN_NUMBER('N', 1), /* AVB_TXC */
5038 [11] = PIN_NUMBER('P', 3), /* AVB_TX_CTL */
5039 [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
5040 [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
5041 [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
5042 [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
5043 [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
5044 [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
5045 [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
5046 [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
5047 [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
5048 [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
5049 [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
5050 [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
5051 [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
5052 [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
5053 [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
5054 [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
5055 [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
5056 [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
5057 [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
5058 [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
5059 } },
5060 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5061 [0] = RCAR_GP_PIN(0, 4), /* D4 */
5062 [1] = RCAR_GP_PIN(0, 3), /* D3 */
5063 [2] = RCAR_GP_PIN(0, 2), /* D2 */
5064 [3] = RCAR_GP_PIN(0, 1), /* D1 */
5065 [4] = RCAR_GP_PIN(0, 0), /* D0 */
5066 [5] = RCAR_GP_PIN(1, 22), /* WE0# */
5067 [6] = RCAR_GP_PIN(1, 21), /* CS0# */
5068 [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
5069 [8] = RCAR_GP_PIN(1, 19), /* A19 */
5070 [9] = RCAR_GP_PIN(1, 18), /* A18 */
5071 [10] = RCAR_GP_PIN(1, 17), /* A17 */
5072 [11] = RCAR_GP_PIN(1, 16), /* A16 */
5073 [12] = RCAR_GP_PIN(1, 15), /* A15 */
5074 [13] = RCAR_GP_PIN(1, 14), /* A14 */
5075 [14] = RCAR_GP_PIN(1, 13), /* A13 */
5076 [15] = RCAR_GP_PIN(1, 12), /* A12 */
5077 [16] = RCAR_GP_PIN(1, 11), /* A11 */
5078 [17] = RCAR_GP_PIN(1, 10), /* A10 */
5079 [18] = RCAR_GP_PIN(1, 9), /* A9 */
5080 [19] = RCAR_GP_PIN(1, 8), /* A8 */
5081 [20] = RCAR_GP_PIN(1, 7), /* A7 */
5082 [21] = RCAR_GP_PIN(1, 6), /* A6 */
5083 [22] = RCAR_GP_PIN(1, 5), /* A5 */
5084 [23] = RCAR_GP_PIN(1, 4), /* A4 */
5085 [24] = RCAR_GP_PIN(1, 3), /* A3 */
5086 [25] = RCAR_GP_PIN(1, 2), /* A2 */
5087 [26] = RCAR_GP_PIN(1, 1), /* A1 */
5088 [27] = RCAR_GP_PIN(1, 0), /* A0 */
5089 [28] = PIN_NONE,
5090 [29] = PIN_NONE,
5091 [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
5092 [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
5093 } },
5094 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5095 [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5096 [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5097 [2] = PIN_NUMBER('H', 1), /* ASEBRK */
5098 [3] = PIN_NONE,
5099 [4] = PIN_NUMBER('G', 2), /* TDI */
5100 [5] = PIN_NUMBER('F', 3), /* TMS */
5101 [6] = PIN_NUMBER('F', 4), /* TCK */
5102 [7] = PIN_NUMBER('F', 1), /* TRST# */
5103 [8] = PIN_NONE,
5104 [9] = PIN_NONE,
5105 [10] = PIN_NONE,
5106 [11] = PIN_NONE,
5107 [12] = PIN_NONE,
5108 [13] = PIN_NONE,
5109 [14] = PIN_NONE,
5110 [15] = PIN_NUMBER('G', 3), /* FSCLKST# */
5111 [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
5112 [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
5113 [18] = PIN_NONE,
5114 [19] = PIN_NONE,
5115 [20] = PIN_A_NUMBER('D', 3), /* PRESETOUT# */
5116 [21] = RCAR_GP_PIN(0, 15), /* D15 */
5117 [22] = RCAR_GP_PIN(0, 14), /* D14 */
5118 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5119 [24] = RCAR_GP_PIN(0, 12), /* D12 */
5120 [25] = RCAR_GP_PIN(0, 11), /* D11 */
5121 [26] = RCAR_GP_PIN(0, 10), /* D10 */
5122 [27] = RCAR_GP_PIN(0, 9), /* D9 */
5123 [28] = RCAR_GP_PIN(0, 8), /* D8 */
5124 [29] = RCAR_GP_PIN(0, 7), /* D7 */
5125 [30] = RCAR_GP_PIN(0, 6), /* D6 */
5126 [31] = RCAR_GP_PIN(0, 5), /* D5 */
5127 } },
5128 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5129 [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
5130 [1] = RCAR_GP_PIN(5, 4), /* RTS0#/TANS_A */
5131 [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
5132 [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
5133 [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
5134 [5] = PIN_NONE,
5135 [6] = PIN_NONE,
5136 [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5137 [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5138 [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5139 [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5140 [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
5141 [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
5142 [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
5143 [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
5144 [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
5145 [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
5146 [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
5147 [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
5148 [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
5149 [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
5150 [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
5151 [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5152 [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5153 [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5154 [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5155 [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5156 [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5157 [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5158 [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5159 [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5160 [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5161 } },
5162 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5163 [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
5164 [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5165 [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5166 [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5167 [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5168 [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5169 [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5170 [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5171 [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5172 [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5173 [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5174 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
5175 [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
5176 [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5177 [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5178 [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5179 [16] = PIN_NUMBER('T', 21), /* MLB_REF */
5180 [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
5181 [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
5182 [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
5183 [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
5184 [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
5185 [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
5186 [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
5187 [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
5188 [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
5189 [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
5190 [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
5191 [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
5192 [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
5193 [30] = RCAR_GP_PIN(5, 6), /* TX1 */
5194 [31] = RCAR_GP_PIN(5, 5), /* RX1 */
5195 } },
5196 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5197 [0] = PIN_NONE,
5198 [1] = PIN_NONE,
5199 [2] = PIN_NONE,
5200 [3] = PIN_NONE,
5201 [4] = PIN_NONE,
5202 [5] = PIN_NONE,
5203 [6] = PIN_NONE,
5204 [7] = PIN_NONE,
5205 [8] = PIN_NONE,
5206 [9] = PIN_NONE,
5207 [10] = PIN_NONE,
5208 [11] = PIN_NONE,
5209 [12] = PIN_NONE,
5210 [13] = PIN_NONE,
5211 [14] = PIN_NONE,
5212 [15] = PIN_NONE,
5213 [16] = PIN_NONE,
5214 [17] = PIN_NONE,
5215 [18] = PIN_NONE,
5216 [19] = PIN_NONE,
5217 [20] = PIN_NONE,
5218 [21] = PIN_NONE,
5219 [22] = PIN_NONE,
5220 [23] = PIN_NONE,
5221 [24] = PIN_NONE,
5222 [25] = PIN_NONE,
5223 [26] = PIN_NONE,
5224 [27] = PIN_NONE,
5225 [28] = PIN_NONE,
5226 [29] = PIN_NONE,
5227 [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
5228 [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
5229 } },
5230 { /* sentinel */ },
5231 };
5232
5233 static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
5234 unsigned int pin)
5235 {
5236 const struct pinmux_bias_reg *reg;
5237 unsigned int bit;
5238
5239 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5240 if (!reg)
5241 return PIN_CONFIG_BIAS_DISABLE;
5242
5243 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
5244 return PIN_CONFIG_BIAS_DISABLE;
5245 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
5246 return PIN_CONFIG_BIAS_PULL_UP;
5247 else
5248 return PIN_CONFIG_BIAS_PULL_DOWN;
5249 }
5250
5251 static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5252 unsigned int bias)
5253 {
5254 const struct pinmux_bias_reg *reg;
5255 u32 enable, updown;
5256 unsigned int bit;
5257
5258 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5259 if (!reg)
5260 return;
5261
5262 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
5263 if (bias != PIN_CONFIG_BIAS_DISABLE)
5264 enable |= BIT(bit);
5265
5266 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
5267 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5268 updown |= BIT(bit);
5269
5270 sh_pfc_write(pfc, reg->pud, updown);
5271 sh_pfc_write(pfc, reg->puen, enable);
5272 }
5273
5274 static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
5275 .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5276 .get_bias = r8a77990_pinmux_get_bias,
5277 .set_bias = r8a77990_pinmux_set_bias,
5278 };
5279
5280 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5281 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5282 .name = "r8a774c0_pfc",
5283 .ops = &r8a77990_pinmux_ops,
5284 .unlock_reg = 0xe6060000, /* PMMR */
5285
5286 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5287
5288 .pins = pinmux_pins,
5289 .nr_pins = ARRAY_SIZE(pinmux_pins),
5290 .groups = pinmux_groups.common,
5291 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5292 .functions = pinmux_functions.common,
5293 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5294
5295 .cfg_regs = pinmux_config_regs,
5296 .bias_regs = pinmux_bias_regs,
5297 .ioctrl_regs = pinmux_ioctrl_regs,
5298
5299 .pinmux_data = pinmux_data,
5300 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5301 };
5302 #endif
5303
5304 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5305 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5306 .name = "r8a77990_pfc",
5307 .ops = &r8a77990_pinmux_ops,
5308 .unlock_reg = 0xe6060000, /* PMMR */
5309
5310 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5311
5312 .pins = pinmux_pins,
5313 .nr_pins = ARRAY_SIZE(pinmux_pins),
5314 .groups = pinmux_groups.common,
5315 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5316 ARRAY_SIZE(pinmux_groups.automotive),
5317 .functions = pinmux_functions.common,
5318 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5319 ARRAY_SIZE(pinmux_functions.automotive),
5320
5321 .cfg_regs = pinmux_config_regs,
5322 .bias_regs = pinmux_bias_regs,
5323 .ioctrl_regs = pinmux_ioctrl_regs,
5324
5325 .pinmux_data = pinmux_data,
5326 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5327 };
5328 #endif
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