2 * Pin Control driver for SuperH Pin Function Controller.
4 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 * Copyright (C) 2008 Magnus Damm
7 * Copyright (C) 2009 - 2012 Paul Mundt
8 * Copyright (C) 2017 Marek Vasut
10 * SPDX-License-Identifier: GPL-2.0
13 #define DRV_NAME "sh-pfc"
18 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR
;
32 struct sh_pfc_pin_config
{
36 struct sh_pfc_pinctrl
{
39 struct sh_pfc_pin_config
*configs
;
41 const char *func_prop_name
;
42 const char *groups_prop_name
;
43 const char *pins_prop_name
;
46 struct sh_pfc_pin_range
{
51 struct sh_pfc_pinctrl_priv
{
53 struct sh_pfc_pinctrl pmx
;
56 int sh_pfc_get_pin_index(struct sh_pfc
*pfc
, unsigned int pin
)
61 for (i
= 0, offset
= 0; i
< pfc
->nr_ranges
; ++i
) {
62 const struct sh_pfc_pin_range
*range
= &pfc
->ranges
[i
];
64 if (pin
<= range
->end
)
65 return pin
>= range
->start
66 ? offset
+ pin
- range
->start
: -1;
68 offset
+= range
->end
- range
->start
+ 1;
74 static int sh_pfc_enum_in_range(u16 enum_id
, const struct pinmux_range
*r
)
76 if (enum_id
< r
->begin
)
85 u32
sh_pfc_read_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
)
89 return readb(mapped_reg
);
91 return readw(mapped_reg
);
93 return readl(mapped_reg
);
100 void sh_pfc_write_raw_reg(void __iomem
*mapped_reg
, unsigned int reg_width
,
105 writeb(data
, mapped_reg
);
108 writew(data
, mapped_reg
);
111 writel(data
, mapped_reg
);
118 u32
sh_pfc_read_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
)
120 return sh_pfc_read_raw_reg(pfc
->regs
+ reg
, width
);
123 void sh_pfc_write_reg(struct sh_pfc
*pfc
, u32 reg
, unsigned int width
, u32 data
)
125 void __iomem
*unlock_reg
=
126 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
128 if (pfc
->info
->unlock_reg
)
129 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
131 sh_pfc_write_raw_reg(pfc
->regs
+ reg
, width
, data
);
134 static void sh_pfc_config_reg_helper(struct sh_pfc
*pfc
,
135 const struct pinmux_cfg_reg
*crp
,
137 void __iomem
**mapped_regp
, u32
*maskp
,
142 *mapped_regp
= (void __iomem
*)(uintptr_t)crp
->reg
;
144 if (crp
->field_width
) {
145 *maskp
= (1 << crp
->field_width
) - 1;
146 *posp
= crp
->reg_width
- ((in_pos
+ 1) * crp
->field_width
);
148 *maskp
= (1 << crp
->var_field_width
[in_pos
]) - 1;
149 *posp
= crp
->reg_width
;
150 for (k
= 0; k
<= in_pos
; k
++)
151 *posp
-= crp
->var_field_width
[k
];
155 static void sh_pfc_write_config_reg(struct sh_pfc
*pfc
,
156 const struct pinmux_cfg_reg
*crp
,
157 unsigned int field
, u32 value
)
159 void __iomem
*mapped_reg
;
160 void __iomem
*unlock_reg
=
161 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
165 sh_pfc_config_reg_helper(pfc
, crp
, field
, &mapped_reg
, &mask
, &pos
);
167 dev_dbg(pfc
->dev
, "write_reg addr = %x, value = 0x%x, field = %u, "
168 "r_width = %u, f_width = %u\n",
169 crp
->reg
, value
, field
, crp
->reg_width
, crp
->field_width
);
171 mask
= ~(mask
<< pos
);
172 value
= value
<< pos
;
174 data
= sh_pfc_read_raw_reg(mapped_reg
, crp
->reg_width
);
178 if (pfc
->info
->unlock_reg
)
179 sh_pfc_write_raw_reg(unlock_reg
, 32, ~data
);
181 sh_pfc_write_raw_reg(mapped_reg
, crp
->reg_width
, data
);
184 static int sh_pfc_get_config_reg(struct sh_pfc
*pfc
, u16 enum_id
,
185 const struct pinmux_cfg_reg
**crp
,
186 unsigned int *fieldp
, u32
*valuep
)
191 const struct pinmux_cfg_reg
*config_reg
=
192 pfc
->info
->cfg_regs
+ k
;
193 unsigned int r_width
= config_reg
->reg_width
;
194 unsigned int f_width
= config_reg
->field_width
;
195 unsigned int curr_width
;
196 unsigned int bit_pos
;
197 unsigned int pos
= 0;
203 for (bit_pos
= 0; bit_pos
< r_width
; bit_pos
+= curr_width
) {
208 curr_width
= f_width
;
210 curr_width
= config_reg
->var_field_width
[m
];
212 ncomb
= 1 << curr_width
;
213 for (n
= 0; n
< ncomb
; n
++) {
214 if (config_reg
->enum_ids
[pos
+ n
] == enum_id
) {
230 static int sh_pfc_mark_to_enum(struct sh_pfc
*pfc
, u16 mark
, int pos
,
233 const u16
*data
= pfc
->info
->pinmux_data
;
237 *enum_idp
= data
[pos
+ 1];
241 for (k
= 0; k
< pfc
->info
->pinmux_data_size
; k
++) {
242 if (data
[k
] == mark
) {
243 *enum_idp
= data
[k
+ 1];
248 dev_err(pfc
->dev
, "cannot locate data/mark enum_id for mark %d\n",
253 int sh_pfc_config_mux(struct sh_pfc
*pfc
, unsigned mark
, int pinmux_type
)
255 const struct pinmux_range
*range
;
258 switch (pinmux_type
) {
259 case PINMUX_TYPE_GPIO
:
260 case PINMUX_TYPE_FUNCTION
:
264 case PINMUX_TYPE_OUTPUT
:
265 range
= &pfc
->info
->output
;
268 case PINMUX_TYPE_INPUT
:
269 range
= &pfc
->info
->input
;
276 /* Iterate over all the configuration fields we need to update. */
278 const struct pinmux_cfg_reg
*cr
;
285 pos
= sh_pfc_mark_to_enum(pfc
, mark
, pos
, &enum_id
);
292 /* Check if the configuration field selects a function. If it
293 * doesn't, skip the field if it's not applicable to the
294 * requested pinmux type.
296 in_range
= sh_pfc_enum_in_range(enum_id
, &pfc
->info
->function
);
298 if (pinmux_type
== PINMUX_TYPE_FUNCTION
) {
299 /* Functions are allowed to modify all
303 } else if (pinmux_type
!= PINMUX_TYPE_GPIO
) {
304 /* Input/output types can only modify fields
305 * that correspond to their respective ranges.
307 in_range
= sh_pfc_enum_in_range(enum_id
, range
);
310 * special case pass through for fixed
311 * input-only or output-only pins without
312 * function enum register association.
314 if (in_range
&& enum_id
== range
->force
)
317 /* GPIOs are only allowed to modify function fields. */
323 ret
= sh_pfc_get_config_reg(pfc
, enum_id
, &cr
, &field
, &value
);
327 sh_pfc_write_config_reg(pfc
, cr
, field
, value
);
333 const struct sh_pfc_bias_info
*
334 sh_pfc_pin_to_bias_info(const struct sh_pfc_bias_info
*info
,
335 unsigned int num
, unsigned int pin
)
339 for (i
= 0; i
< num
; i
++)
340 if (info
[i
].pin
== pin
)
343 printf("Pin %u is not in bias info list\n", pin
);
348 static int sh_pfc_init_ranges(struct sh_pfc
*pfc
)
350 struct sh_pfc_pin_range
*range
;
351 unsigned int nr_ranges
;
354 if (pfc
->info
->pins
[0].pin
== (u16
)-1) {
355 /* Pin number -1 denotes that the SoC doesn't report pin numbers
356 * in its pin arrays yet. Consider the pin numbers range as
357 * continuous and allocate a single range.
360 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
), GFP_KERNEL
);
361 if (pfc
->ranges
== NULL
)
364 pfc
->ranges
->start
= 0;
365 pfc
->ranges
->end
= pfc
->info
->nr_pins
- 1;
366 pfc
->nr_gpio_pins
= pfc
->info
->nr_pins
;
371 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
372 * be sorted by pin numbers, and pins without a GPIO port must come
375 for (i
= 1, nr_ranges
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
376 if (pfc
->info
->pins
[i
-1].pin
!= pfc
->info
->pins
[i
].pin
- 1)
380 pfc
->nr_ranges
= nr_ranges
;
381 pfc
->ranges
= kzalloc(sizeof(*pfc
->ranges
) * nr_ranges
, GFP_KERNEL
);
382 if (pfc
->ranges
== NULL
)
386 range
->start
= pfc
->info
->pins
[0].pin
;
388 for (i
= 1; i
< pfc
->info
->nr_pins
; ++i
) {
389 if (pfc
->info
->pins
[i
-1].pin
== pfc
->info
->pins
[i
].pin
- 1)
392 range
->end
= pfc
->info
->pins
[i
-1].pin
;
393 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
394 pfc
->nr_gpio_pins
= range
->end
+ 1;
397 range
->start
= pfc
->info
->pins
[i
].pin
;
400 range
->end
= pfc
->info
->pins
[i
-1].pin
;
401 if (!(pfc
->info
->pins
[i
-1].configs
& SH_PFC_PIN_CFG_NO_GPIO
))
402 pfc
->nr_gpio_pins
= range
->end
+ 1;
407 static int sh_pfc_pinctrl_get_pins_count(struct udevice
*dev
)
409 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
411 return priv
->pfc
.info
->nr_pins
;
414 static const char *sh_pfc_pinctrl_get_pin_name(struct udevice
*dev
,
417 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
419 return priv
->pfc
.info
->pins
[selector
].name
;
422 static int sh_pfc_pinctrl_get_groups_count(struct udevice
*dev
)
424 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
426 return priv
->pfc
.info
->nr_groups
;
429 static const char *sh_pfc_pinctrl_get_group_name(struct udevice
*dev
,
432 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
434 return priv
->pfc
.info
->groups
[selector
].name
;
437 static int sh_pfc_pinctrl_get_functions_count(struct udevice
*dev
)
439 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
441 return priv
->pfc
.info
->nr_functions
;
444 static const char *sh_pfc_pinctrl_get_function_name(struct udevice
*dev
,
447 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
449 return priv
->pfc
.info
->functions
[selector
].name
;
452 int sh_pfc_config_mux_for_gpio(struct udevice
*dev
, unsigned pin_selector
)
454 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
455 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
456 struct sh_pfc
*pfc
= &priv
->pfc
;
457 struct sh_pfc_pin_config
*cfg
;
458 const struct sh_pfc_pin
*pin
= NULL
;
461 for (i
= 1; i
< pfc
->info
->nr_pins
; i
++) {
462 if (priv
->pfc
.info
->pins
[i
].pin
!= pin_selector
)
465 pin
= &priv
->pfc
.info
->pins
[i
];
472 idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
473 cfg
= &pmx
->configs
[idx
];
475 if (cfg
->type
!= PINMUX_TYPE_NONE
)
478 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_GPIO
);
481 static int sh_pfc_pinctrl_pin_set(struct udevice
*dev
, unsigned pin_selector
,
482 unsigned func_selector
)
484 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
485 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
486 struct sh_pfc
*pfc
= &priv
->pfc
;
487 const struct sh_pfc_pin
*pin
= &priv
->pfc
.info
->pins
[pin_selector
];
488 int idx
= sh_pfc_get_pin_index(pfc
, pin
->pin
);
489 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
491 if (cfg
->type
!= PINMUX_TYPE_NONE
)
494 return sh_pfc_config_mux(pfc
, pin
->enum_id
, PINMUX_TYPE_FUNCTION
);
497 static int sh_pfc_pinctrl_group_set(struct udevice
*dev
, unsigned group_selector
,
498 unsigned func_selector
)
500 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
501 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
502 struct sh_pfc
*pfc
= &priv
->pfc
;
503 const struct sh_pfc_pin_group
*grp
= &priv
->pfc
.info
->groups
[group_selector
];
507 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
508 int idx
= sh_pfc_get_pin_index(pfc
, grp
->pins
[i
]);
509 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[idx
];
511 if (cfg
->type
!= PINMUX_TYPE_NONE
) {
517 for (i
= 0; i
< grp
->nr_pins
; ++i
) {
518 ret
= sh_pfc_config_mux(pfc
, grp
->mux
[i
], PINMUX_TYPE_FUNCTION
);
526 #if CONFIG_IS_ENABLED(PINCONF)
527 static const struct pinconf_param sh_pfc_pinconf_params
[] = {
528 { "bias-disable", PIN_CONFIG_BIAS_DISABLE
, 0 },
529 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP
, 1 },
530 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN
, 1 },
531 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH
, 0 },
532 { "power-source", PIN_CONFIG_POWER_SOURCE
, 3300 },
535 static void __iomem
*
536 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc
*pfc
, unsigned int pin
,
537 unsigned int *offset
, unsigned int *size
)
539 const struct pinmux_drive_reg_field
*field
;
540 const struct pinmux_drive_reg
*reg
;
543 for (reg
= pfc
->info
->drive_regs
; reg
->reg
; ++reg
) {
544 for (i
= 0; i
< ARRAY_SIZE(reg
->fields
); ++i
) {
545 field
= ®
->fields
[i
];
547 if (field
->size
&& field
->pin
== pin
) {
548 *offset
= field
->offset
;
551 return (void __iomem
*)(uintptr_t)reg
->reg
;
559 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc
*pfc
,
560 unsigned int pin
, u16 strength
)
566 void __iomem
*unlock_reg
=
567 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
570 reg
= sh_pfc_pinconf_find_drive_strength_reg(pfc
, pin
, &offset
, &size
);
574 step
= size
== 2 ? 6 : 3;
576 if (strength
< step
|| strength
> 24)
579 /* Convert the value from mA based on a full drive strength value of
580 * 24mA. We can make the full value configurable later if needed.
582 strength
= strength
/ step
- 1;
584 val
= sh_pfc_read_raw_reg(reg
, 32);
585 val
&= ~GENMASK(offset
+ size
- 1, offset
);
586 val
|= strength
<< offset
;
589 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
591 sh_pfc_write_raw_reg(reg
, 32, val
);
596 /* Check whether the requested parameter is supported for a pin. */
597 static bool sh_pfc_pinconf_validate(struct sh_pfc
*pfc
, unsigned int _pin
,
600 int idx
= sh_pfc_get_pin_index(pfc
, _pin
);
601 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[idx
];
604 case PIN_CONFIG_BIAS_DISABLE
:
605 return pin
->configs
&
606 (SH_PFC_PIN_CFG_PULL_UP
| SH_PFC_PIN_CFG_PULL_DOWN
);
608 case PIN_CONFIG_BIAS_PULL_UP
:
609 return pin
->configs
& SH_PFC_PIN_CFG_PULL_UP
;
611 case PIN_CONFIG_BIAS_PULL_DOWN
:
612 return pin
->configs
& SH_PFC_PIN_CFG_PULL_DOWN
;
614 case PIN_CONFIG_DRIVE_STRENGTH
:
615 return pin
->configs
& SH_PFC_PIN_CFG_DRIVE_STRENGTH
;
617 case PIN_CONFIG_POWER_SOURCE
:
618 return pin
->configs
& SH_PFC_PIN_CFG_IO_VOLTAGE
;
625 static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl
*pmx
, unsigned _pin
,
626 unsigned int param
, unsigned int arg
)
628 struct sh_pfc
*pfc
= pmx
->pfc
;
629 void __iomem
*pocctrl
;
630 void __iomem
*unlock_reg
=
631 (void __iomem
*)(uintptr_t)pfc
->info
->unlock_reg
;
635 if (!sh_pfc_pinconf_validate(pfc
, _pin
, param
))
639 case PIN_CONFIG_BIAS_PULL_UP
:
640 case PIN_CONFIG_BIAS_PULL_DOWN
:
641 case PIN_CONFIG_BIAS_DISABLE
:
642 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->set_bias
)
645 pfc
->info
->ops
->set_bias(pfc
, _pin
, param
);
649 case PIN_CONFIG_DRIVE_STRENGTH
:
650 ret
= sh_pfc_pinconf_set_drive_strength(pfc
, _pin
, arg
);
656 case PIN_CONFIG_POWER_SOURCE
:
657 if (!pfc
->info
->ops
|| !pfc
->info
->ops
->pin_to_pocctrl
)
660 bit
= pfc
->info
->ops
->pin_to_pocctrl(pfc
, _pin
, &addr
);
662 printf("invalid pin %#x", _pin
);
666 if (arg
!= 1800 && arg
!= 3300)
669 pocctrl
= (void __iomem
*)(uintptr_t)addr
;
671 val
= sh_pfc_read_raw_reg(pocctrl
, 32);
678 sh_pfc_write_raw_reg(unlock_reg
, 32, ~val
);
680 sh_pfc_write_raw_reg(pocctrl
, 32, val
);
691 static int sh_pfc_pinconf_pin_set(struct udevice
*dev
,
692 unsigned int pin_selector
,
693 unsigned int param
, unsigned int arg
)
695 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
696 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
697 struct sh_pfc
*pfc
= &priv
->pfc
;
698 const struct sh_pfc_pin
*pin
= &pfc
->info
->pins
[pin_selector
];
700 sh_pfc_pinconf_set(pmx
, pin
->pin
, param
, arg
);
705 static int sh_pfc_pinconf_group_set(struct udevice
*dev
,
706 unsigned int group_selector
,
707 unsigned int param
, unsigned int arg
)
709 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
710 struct sh_pfc_pinctrl
*pmx
= &priv
->pmx
;
711 struct sh_pfc
*pfc
= &priv
->pfc
;
712 const struct sh_pfc_pin_group
*grp
= &pfc
->info
->groups
[group_selector
];
715 for (i
= 0; i
< grp
->nr_pins
; i
++)
716 sh_pfc_pinconf_set(pmx
, grp
->pins
[i
], param
, arg
);
722 static struct pinctrl_ops sh_pfc_pinctrl_ops
= {
723 .get_pins_count
= sh_pfc_pinctrl_get_pins_count
,
724 .get_pin_name
= sh_pfc_pinctrl_get_pin_name
,
725 .get_groups_count
= sh_pfc_pinctrl_get_groups_count
,
726 .get_group_name
= sh_pfc_pinctrl_get_group_name
,
727 .get_functions_count
= sh_pfc_pinctrl_get_functions_count
,
728 .get_function_name
= sh_pfc_pinctrl_get_function_name
,
730 #if CONFIG_IS_ENABLED(PINCONF)
731 .pinconf_num_params
= ARRAY_SIZE(sh_pfc_pinconf_params
),
732 .pinconf_params
= sh_pfc_pinconf_params
,
733 .pinconf_set
= sh_pfc_pinconf_pin_set
,
734 .pinconf_group_set
= sh_pfc_pinconf_group_set
,
736 .pinmux_set
= sh_pfc_pinctrl_pin_set
,
737 .pinmux_group_set
= sh_pfc_pinctrl_group_set
,
738 .set_state
= pinctrl_generic_set_state
,
741 static int sh_pfc_map_pins(struct sh_pfc
*pfc
, struct sh_pfc_pinctrl
*pmx
)
745 /* Allocate and initialize the pins and configs arrays. */
746 pmx
->configs
= kzalloc(sizeof(*pmx
->configs
) * pfc
->info
->nr_pins
,
748 if (unlikely(!pmx
->configs
))
751 for (i
= 0; i
< pfc
->info
->nr_pins
; ++i
) {
752 struct sh_pfc_pin_config
*cfg
= &pmx
->configs
[i
];
753 cfg
->type
= PINMUX_TYPE_NONE
;
760 static int sh_pfc_pinctrl_probe(struct udevice
*dev
)
762 struct sh_pfc_pinctrl_priv
*priv
= dev_get_priv(dev
);
763 enum sh_pfc_model model
= dev_get_driver_data(dev
);
766 base
= devfdt_get_addr(dev
);
767 if (base
== FDT_ADDR_T_NONE
)
770 priv
->pfc
.regs
= devm_ioremap(dev
, base
, SZ_2K
);
774 #ifdef CONFIG_PINCTRL_PFC_R8A7795
775 if (model
== SH_PFC_R8A7795
)
776 priv
->pfc
.info
= &r8a7795_pinmux_info
;
778 #ifdef CONFIG_PINCTRL_PFC_R8A7796
779 if (model
== SH_PFC_R8A7796
)
780 priv
->pfc
.info
= &r8a7796_pinmux_info
;
782 #ifdef CONFIG_PINCTRL_PFC_R8A77970
783 if (model
== SH_PFC_R8A77970
)
784 priv
->pfc
.info
= &r8a77970_pinmux_info
;
787 priv
->pmx
.pfc
= &priv
->pfc
;
788 sh_pfc_init_ranges(&priv
->pfc
);
789 sh_pfc_map_pins(&priv
->pfc
, &priv
->pmx
);
794 static const struct udevice_id sh_pfc_pinctrl_ids
[] = {
795 #ifdef CONFIG_PINCTRL_PFC_R8A7795
797 .compatible
= "renesas,pfc-r8a7795",
798 .data
= SH_PFC_R8A7795
,
801 #ifdef CONFIG_PINCTRL_PFC_R8A7796
803 .compatible
= "renesas,pfc-r8a7796",
804 .data
= SH_PFC_R8A7796
,
807 #ifdef CONFIG_PINCTRL_PFC_R8A77970
809 .compatible
= "renesas,pfc-r8a77970",
810 .data
= SH_PFC_R8A77970
,
816 U_BOOT_DRIVER(pinctrl_sh_pfc
) = {
817 .name
= "sh_pfc_pinctrl",
818 .id
= UCLASS_PINCTRL
,
819 .of_match
= sh_pfc_pinctrl_ids
,
820 .priv_auto_alloc_size
= sizeof(struct sh_pfc_pinctrl_priv
),
821 .ops
= &sh_pfc_pinctrl_ops
,
822 .probe
= sh_pfc_pinctrl_probe
,