2 * Pinctrl driver for Rockchip SoCs
3 * Copyright (c) 2015 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
6 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/grf_rk3288.h>
16 #include <asm/arch/hardware.h>
17 #include <asm/arch/periph.h>
18 #include <asm/arch/pmu_rk3288.h>
19 #include <dm/pinctrl.h>
21 DECLARE_GLOBAL_DATA_PTR
;
23 struct rk3288_pinctrl_priv
{
24 struct rk3288_grf
*grf
;
25 struct rk3288_pmu
*pmu
;
28 static void pinctrl_rk3288_pwm_config(struct rk3288_grf
*grf
, int pwm_id
)
32 rk_clrsetreg(&grf
->gpio7a_iomux
, GPIO7A0_MASK
<< GPIO7A0_SHIFT
,
33 GPIO7A0_PWM_0
<< GPIO7A0_SHIFT
);
36 rk_clrsetreg(&grf
->gpio7a_iomux
, GPIO7A1_MASK
<< GPIO7A1_SHIFT
,
37 GPIO7A1_PWM_1
<< GPIO7A1_SHIFT
);
40 rk_clrsetreg(&grf
->gpio7a_iomux
, GPIO7C6_MASK
<< GPIO7C6_SHIFT
,
41 GPIO7C6_PWM_2
<< GPIO7C6_SHIFT
);
44 rk_clrsetreg(&grf
->gpio7a_iomux
, GPIO7C7_MASK
<< GPIO7C6_SHIFT
,
45 GPIO7C7_PWM_3
<< GPIO7C7_SHIFT
);
48 debug("pwm id = %d iomux error!\n", pwm_id
);
53 static void pinctrl_rk3288_i2c_config(struct rk3288_grf
*grf
,
54 struct rk3288_pmu
*pmu
, int i2c_id
)
58 clrsetbits_le32(&pmu
->gpio0b_iomux
,
59 GPIO0_B7_MASK
<< GPIO0_B7_SHIFT
,
60 GPIO0_B7_I2C0PMU_SDA
<< GPIO0_B7_SHIFT
);
61 clrsetbits_le32(&pmu
->gpio0b_iomux
,
62 GPIO0_C0_MASK
<< GPIO0_C0_SHIFT
,
63 GPIO0_C0_I2C0PMU_SCL
<< GPIO0_C0_SHIFT
);
66 rk_clrsetreg(&grf
->gpio8a_iomux
,
67 GPIO8A4_MASK
<< GPIO8A4_SHIFT
|
68 GPIO8A5_MASK
<< GPIO8A5_SHIFT
,
69 GPIO8A4_I2C2SENSOR_SDA
<< GPIO8A4_SHIFT
|
70 GPIO8A5_I2C2SENSOR_SCL
<< GPIO8A5_SHIFT
);
73 rk_clrsetreg(&grf
->gpio6b_iomux
,
74 GPIO6B1_MASK
<< GPIO6B1_SHIFT
|
75 GPIO6B2_MASK
<< GPIO6B2_SHIFT
,
76 GPIO6B1_I2C1AUDIO_SDA
<< GPIO6B1_SHIFT
|
77 GPIO6B2_I2C1AUDIO_SCL
<< GPIO6B2_SHIFT
);
80 rk_clrsetreg(&grf
->gpio2c_iomux
,
81 GPIO2C1_MASK
<< GPIO2C1_SHIFT
|
82 GPIO2C0_MASK
<< GPIO2C0_SHIFT
,
83 GPIO2C1_I2C3CAM_SDA
<< GPIO2C1_SHIFT
|
84 GPIO2C0_I2C3CAM_SCL
<< GPIO2C0_SHIFT
);
87 rk_clrsetreg(&grf
->gpio7cl_iomux
,
88 GPIO7C1_MASK
<< GPIO7C1_SHIFT
|
89 GPIO7C2_MASK
<< GPIO7C2_SHIFT
,
90 GPIO7C1_I2C4TP_SDA
<< GPIO7C1_SHIFT
|
91 GPIO7C2_I2C4TP_SCL
<< GPIO7C2_SHIFT
);
94 rk_clrsetreg(&grf
->gpio7cl_iomux
,
95 GPIO7C3_MASK
<< GPIO7C3_SHIFT
,
96 GPIO7C3_I2C5HDMI_SDA
<< GPIO7C3_SHIFT
);
97 rk_clrsetreg(&grf
->gpio7ch_iomux
,
98 GPIO7C4_MASK
<< GPIO7C4_SHIFT
,
99 GPIO7C4_I2C5HDMI_SCL
<< GPIO7C4_SHIFT
);
102 debug("i2c id = %d iomux error!\n", i2c_id
);
107 static void pinctrl_rk3288_lcdc_config(struct rk3288_grf
*grf
, int lcd_id
)
110 case PERIPH_ID_LCDC0
:
111 rk_clrsetreg(&grf
->gpio1d_iomux
,
112 GPIO1D3_MASK
<< GPIO1D0_SHIFT
|
113 GPIO1D2_MASK
<< GPIO1D2_SHIFT
|
114 GPIO1D1_MASK
<< GPIO1D1_SHIFT
|
115 GPIO1D0_MASK
<< GPIO1D0_SHIFT
,
116 GPIO1D3_LCDC0_DCLK
<< GPIO1D3_SHIFT
|
117 GPIO1D2_LCDC0_DEN
<< GPIO1D2_SHIFT
|
118 GPIO1D1_LCDC0_VSYNC
<< GPIO1D1_SHIFT
|
119 GPIO1D0_LCDC0_HSYNC
<< GPIO1D0_SHIFT
);
122 debug("lcdc id = %d iomux error!\n", lcd_id
);
127 static int pinctrl_rk3288_spi_config(struct rk3288_grf
*grf
,
128 enum periph_id spi_id
, int cs
)
134 rk_clrsetreg(&grf
->gpio5b_iomux
,
135 GPIO5B5_MASK
<< GPIO5B5_SHIFT
,
136 GPIO5B5_SPI0_CSN0
<< GPIO5B5_SHIFT
);
139 rk_clrsetreg(&grf
->gpio5c_iomux
,
140 GPIO5C0_MASK
<< GPIO5C0_SHIFT
,
141 GPIO5C0_SPI0_CSN1
<< GPIO5C0_SHIFT
);
146 rk_clrsetreg(&grf
->gpio5b_iomux
,
147 GPIO5B7_MASK
<< GPIO5B7_SHIFT
|
148 GPIO5B6_MASK
<< GPIO5B6_SHIFT
|
149 GPIO5B4_MASK
<< GPIO5B4_SHIFT
,
150 GPIO5B7_SPI0_RXD
<< GPIO5B7_SHIFT
|
151 GPIO5B6_SPI0_TXD
<< GPIO5B6_SHIFT
|
152 GPIO5B4_SPI0_CLK
<< GPIO5B4_SHIFT
);
157 rk_clrsetreg(&grf
->gpio7b_iomux
,
158 GPIO7B6_MASK
<< GPIO7B6_SHIFT
|
159 GPIO7B7_MASK
<< GPIO7B7_SHIFT
|
160 GPIO7B5_MASK
<< GPIO7B5_SHIFT
|
161 GPIO7B4_MASK
<< GPIO7B4_SHIFT
,
162 GPIO7B6_SPI1_RXD
<< GPIO7B6_SHIFT
|
163 GPIO7B7_SPI1_TXD
<< GPIO7B7_SHIFT
|
164 GPIO7B5_SPI1_CSN0
<< GPIO7B5_SHIFT
|
165 GPIO7B4_SPI1_CLK
<< GPIO7B4_SHIFT
);
170 rk_clrsetreg(&grf
->gpio8a_iomux
,
171 GPIO8A7_MASK
<< GPIO8A7_SHIFT
,
172 GPIO8A7_SPI2_CSN0
<< GPIO8A7_SHIFT
);
175 rk_clrsetreg(&grf
->gpio8a_iomux
,
176 GPIO8A3_MASK
<< GPIO8A3_SHIFT
,
177 GPIO8A3_SPI2_CSN1
<< GPIO8A3_SHIFT
);
182 rk_clrsetreg(&grf
->gpio8b_iomux
,
183 GPIO8B1_MASK
<< GPIO8B1_SHIFT
|
184 GPIO8B0_MASK
<< GPIO8B0_SHIFT
,
185 GPIO8B1_SPI2_TXD
<< GPIO8B1_SHIFT
|
186 GPIO8B0_SPI2_RXD
<< GPIO8B0_SHIFT
);
187 rk_clrsetreg(&grf
->gpio8a_iomux
,
188 GPIO8A6_MASK
<< GPIO8A6_SHIFT
,
189 GPIO8A6_SPI2_CLK
<< GPIO8A6_SHIFT
);
197 debug("rkspi: periph%d cs=%d not supported", spi_id
, cs
);
201 static void pinctrl_rk3288_uart_config(struct rk3288_grf
*grf
, int uart_id
)
204 case PERIPH_ID_UART_BT
:
205 rk_clrsetreg(&grf
->gpio4c_iomux
,
206 GPIO4C3_MASK
<< GPIO4C3_SHIFT
|
207 GPIO4C2_MASK
<< GPIO4C2_SHIFT
|
208 GPIO4C1_MASK
<< GPIO4C1_SHIFT
|
209 GPIO4C0_MASK
<< GPIO4C0_SHIFT
,
210 GPIO4C3_UART0BT_RTSN
<< GPIO4C3_SHIFT
|
211 GPIO4C2_UART0BT_CTSN
<< GPIO4C2_SHIFT
|
212 GPIO4C1_UART0BT_SOUT
<< GPIO4C1_SHIFT
|
213 GPIO4C0_UART0BT_SIN
<< GPIO4C0_SHIFT
);
215 case PERIPH_ID_UART_BB
:
216 rk_clrsetreg(&grf
->gpio5b_iomux
,
217 GPIO5B3_MASK
<< GPIO5B3_SHIFT
|
218 GPIO5B2_MASK
<< GPIO5B2_SHIFT
|
219 GPIO5B1_MASK
<< GPIO5B1_SHIFT
|
220 GPIO5B0_MASK
<< GPIO5B0_SHIFT
,
221 GPIO5B3_UART1BB_RTSN
<< GPIO5B3_SHIFT
|
222 GPIO5B2_UART1BB_CTSN
<< GPIO5B2_SHIFT
|
223 GPIO5B1_UART1BB_SOUT
<< GPIO5B1_SHIFT
|
224 GPIO5B0_UART1BB_SIN
<< GPIO5B0_SHIFT
);
226 case PERIPH_ID_UART_DBG
:
227 rk_clrsetreg(&grf
->gpio7ch_iomux
,
228 GPIO7C7_MASK
<< GPIO7C7_SHIFT
|
229 GPIO7C6_MASK
<< GPIO7C6_SHIFT
,
230 GPIO7C7_UART2DBG_SOUT
<< GPIO7C7_SHIFT
|
231 GPIO7C6_UART2DBG_SIN
<< GPIO7C6_SHIFT
);
233 case PERIPH_ID_UART_GPS
:
234 rk_clrsetreg(&grf
->gpio7b_iomux
,
235 GPIO7B2_MASK
<< GPIO7B2_SHIFT
|
236 GPIO7B1_MASK
<< GPIO7B1_SHIFT
|
237 GPIO7B0_MASK
<< GPIO7B0_SHIFT
,
238 GPIO7B2_UART3GPS_RTSN
<< GPIO7B2_SHIFT
|
239 GPIO7B1_UART3GPS_CTSN
<< GPIO7B1_SHIFT
|
240 GPIO7B0_UART3GPS_SOUT
<< GPIO7B0_SHIFT
);
241 rk_clrsetreg(&grf
->gpio7a_iomux
,
242 GPIO7A7_MASK
<< GPIO7A7_SHIFT
,
243 GPIO7A7_UART3GPS_SIN
<< GPIO7A7_SHIFT
);
245 case PERIPH_ID_UART_EXP
:
246 rk_clrsetreg(&grf
->gpio5b_iomux
,
247 GPIO5B5_MASK
<< GPIO5B5_SHIFT
|
248 GPIO5B4_MASK
<< GPIO5B4_SHIFT
|
249 GPIO5B6_MASK
<< GPIO5B6_SHIFT
|
250 GPIO5B7_MASK
<< GPIO5B7_SHIFT
,
251 GPIO5B5_UART4EXP_RTSN
<< GPIO5B5_SHIFT
|
252 GPIO5B4_UART4EXP_CTSN
<< GPIO5B4_SHIFT
|
253 GPIO5B6_UART4EXP_SOUT
<< GPIO5B6_SHIFT
|
254 GPIO5B7_UART4EXP_SIN
<< GPIO5B7_SHIFT
);
257 debug("uart id = %d iomux error!\n", uart_id
);
262 static void pinctrl_rk3288_sdmmc_config(struct rk3288_grf
*grf
, int mmc_id
)
266 rk_clrsetreg(&grf
->gpio3a_iomux
, 0xffff,
267 GPIO3A7_EMMC_DATA7
<< GPIO3A7_SHIFT
|
268 GPIO3A6_EMMC_DATA6
<< GPIO3A6_SHIFT
|
269 GPIO3A5_EMMC_DATA5
<< GPIO3A5_SHIFT
|
270 GPIO3A4_EMMC_DATA4
<< GPIO3A4_SHIFT
|
271 GPIO3A3_EMMC_DATA3
<< GPIO3A3_SHIFT
|
272 GPIO3A2_EMMC_DATA2
<< GPIO3A2_SHIFT
|
273 GPIO3A1_EMMC_DATA1
<< GPIO3A1_SHIFT
|
274 GPIO3A0_EMMC_DATA0
<< GPIO3A0_SHIFT
);
275 rk_clrsetreg(&grf
->gpio3b_iomux
, GPIO3B1_MASK
<< GPIO3B1_SHIFT
,
276 GPIO3B1_EMMC_PWREN
<< GPIO3B1_SHIFT
);
277 rk_clrsetreg(&grf
->gpio3c_iomux
,
278 GPIO3C0_MASK
<< GPIO3C0_SHIFT
,
279 GPIO3C0_EMMC_CMD
<< GPIO3C0_SHIFT
);
281 case PERIPH_ID_SDCARD
:
282 rk_clrsetreg(&grf
->gpio6c_iomux
, 0xffff,
283 GPIO6C6_SDMMC0_DECTN
<< GPIO6C6_SHIFT
|
284 GPIO6C5_SDMMC0_CMD
<< GPIO6C5_SHIFT
|
285 GPIO6C4_SDMMC0_CLKOUT
<< GPIO6C4_SHIFT
|
286 GPIO6C3_SDMMC0_DATA3
<< GPIO6C3_SHIFT
|
287 GPIO6C2_SDMMC0_DATA2
<< GPIO6C2_SHIFT
|
288 GPIO6C1_SDMMC0_DATA1
<< GPIO6C1_SHIFT
|
289 GPIO6C0_SDMMC0_DATA0
<< GPIO6C0_SHIFT
);
291 /* use sdmmc0 io, disable JTAG function */
292 rk_clrsetreg(&grf
->soc_con0
, 1 << GRF_FORCE_JTAG_SHIFT
, 0);
295 debug("mmc id = %d iomux error!\n", mmc_id
);
300 static void pinctrl_rk3288_hdmi_config(struct rk3288_grf
*grf
, int hdmi_id
)
304 rk_clrsetreg(&grf
->gpio7cl_iomux
, GPIO7C3_MASK
<< GPIO7C3_SHIFT
,
305 GPIO7C3_EDPHDMII2C_SDA
<< GPIO7C3_SHIFT
);
306 rk_clrsetreg(&grf
->gpio7ch_iomux
, GPIO7C4_MASK
<< GPIO7C4_SHIFT
,
307 GPIO7C4_EDPHDMII2C_SCL
<< GPIO7C4_SHIFT
);
310 debug("hdmi id = %d iomux error!\n", hdmi_id
);
315 static int rk3288_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
317 struct rk3288_pinctrl_priv
*priv
= dev_get_priv(dev
);
319 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
326 pinctrl_rk3288_pwm_config(priv
->grf
, func
);
334 pinctrl_rk3288_i2c_config(priv
->grf
, priv
->pmu
, func
);
339 pinctrl_rk3288_spi_config(priv
->grf
, func
, flags
);
341 case PERIPH_ID_UART0
:
342 case PERIPH_ID_UART1
:
343 case PERIPH_ID_UART2
:
344 case PERIPH_ID_UART3
:
345 case PERIPH_ID_UART4
:
346 pinctrl_rk3288_uart_config(priv
->grf
, func
);
348 case PERIPH_ID_LCDC0
:
349 case PERIPH_ID_LCDC1
:
350 pinctrl_rk3288_lcdc_config(priv
->grf
, func
);
352 case PERIPH_ID_SDMMC0
:
353 case PERIPH_ID_SDMMC1
:
354 pinctrl_rk3288_sdmmc_config(priv
->grf
, func
);
357 pinctrl_rk3288_hdmi_config(priv
->grf
, func
);
366 static int rk3288_pinctrl_get_periph_id(struct udevice
*dev
,
367 struct udevice
*periph
)
372 ret
= fdtdec_get_int_array(gd
->fdt_blob
, periph
->of_offset
,
373 "interrupts", cell
, ARRAY_SIZE(cell
));
379 return PERIPH_ID_SPI0
;
381 return PERIPH_ID_SPI1
;
383 return PERIPH_ID_SPI2
;
385 return PERIPH_ID_I2C0
;
386 case 62: /* Note strange order */
387 return PERIPH_ID_I2C1
;
389 return PERIPH_ID_I2C2
;
391 return PERIPH_ID_I2C3
;
393 return PERIPH_ID_I2C4
;
395 return PERIPH_ID_I2C5
;
401 static int rk3288_pinctrl_set_state_simple(struct udevice
*dev
,
402 struct udevice
*periph
)
406 func
= rk3288_pinctrl_get_periph_id(dev
, periph
);
409 return rk3288_pinctrl_request(dev
, func
, 0);
412 static struct pinctrl_ops rk3288_pinctrl_ops
= {
413 .set_state_simple
= rk3288_pinctrl_set_state_simple
,
414 .request
= rk3288_pinctrl_request
,
415 .get_periph_id
= rk3288_pinctrl_get_periph_id
,
418 static int rk3288_pinctrl_probe(struct udevice
*dev
)
420 struct rk3288_pinctrl_priv
*priv
= dev_get_priv(dev
);
422 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
423 priv
->pmu
= syscon_get_first_range(ROCKCHIP_SYSCON_PMU
);
424 debug("%s: grf=%p, pmu=%p\n", __func__
, priv
->grf
, priv
->pmu
);
429 static const struct udevice_id rk3288_pinctrl_ids
[] = {
430 { .compatible
= "rockchip,rk3288-pinctrl" },
434 U_BOOT_DRIVER(pinctrl_rk3288
) = {
435 .name
= "pinctrl_rk3288",
436 .id
= UCLASS_PINCTRL
,
437 .of_match
= rk3288_pinctrl_ids
,
438 .priv_auto_alloc_size
= sizeof(struct rk3288_pinctrl_priv
),
439 .ops
= &rk3288_pinctrl_ops
,
440 .probe
= rk3288_pinctrl_probe
,