2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/grf_rk3399.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct rk3399_pinctrl_priv
{
21 struct rk3399_grf_regs
*grf
;
22 struct rk3399_pmugrf_regs
*pmugrf
;
25 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs
*grf
,
26 struct rk3399_pmugrf_regs
*pmugrf
, int pwm_id
)
30 rk_clrsetreg(&grf
->gpio4c_iomux
,
32 GRF_PWM_0
<< GRF_GPIO4C2_SEL_SHIFT
);
35 rk_clrsetreg(&grf
->gpio4c_iomux
,
37 GRF_PWM_1
<< GRF_GPIO4C6_SEL_SHIFT
);
40 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
41 PMUGRF_GPIO1C3_SEL_MASK
,
42 PMUGRF_PWM_2
<< PMUGRF_GPIO1C3_SEL_SHIFT
);
45 if (readl(&pmugrf
->soc_con0
) & (1 << 5))
46 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
47 PMUGRF_GPIO1B6_SEL_MASK
,
48 PMUGRF_PWM_3B
<< PMUGRF_GPIO1B6_SEL_SHIFT
);
50 rk_clrsetreg(&pmugrf
->gpio0a_iomux
,
51 PMUGRF_GPIO0A6_SEL_MASK
,
52 PMUGRF_PWM_3A
<< PMUGRF_GPIO0A6_SEL_SHIFT
);
55 debug("pwm id = %d iomux error!\n", pwm_id
);
60 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs
*grf
,
61 struct rk3399_pmugrf_regs
*pmugrf
,
66 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
67 PMUGRF_GPIO1B7_SEL_MASK
,
68 PMUGRF_I2C0PMU_SDA
<< PMUGRF_GPIO1B7_SEL_SHIFT
);
69 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
70 PMUGRF_GPIO1C0_SEL_MASK
,
71 PMUGRF_I2C0PMU_SCL
<< PMUGRF_GPIO1C0_SEL_SHIFT
);
74 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
75 PMUGRF_GPIO1C4_SEL_MASK
,
76 PMUGRF_I2C8PMU_SDA
<< PMUGRF_GPIO1C4_SEL_SHIFT
);
77 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
78 PMUGRF_GPIO1C5_SEL_MASK
,
79 PMUGRF_I2C8PMU_SCL
<< PMUGRF_GPIO1C5_SEL_SHIFT
);
89 debug("i2c id = %d iomux error!\n", i2c_id
);
94 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs
*grf
, int lcd_id
)
100 debug("lcdc id = %d iomux error!\n", lcd_id
);
105 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs
*grf
,
106 struct rk3399_pmugrf_regs
*pmugrf
,
107 enum periph_id spi_id
, int cs
)
113 rk_clrsetreg(&grf
->gpio3a_iomux
,
114 GRF_GPIO3A7_SEL_MASK
,
115 GRF_SPI0NORCODEC_CSN0
116 << GRF_GPIO3A7_SEL_SHIFT
);
119 rk_clrsetreg(&grf
->gpio3b_iomux
,
120 GRF_GPIO3B0_SEL_MASK
,
121 GRF_SPI0NORCODEC_CSN1
122 << GRF_GPIO3B0_SEL_SHIFT
);
127 rk_clrsetreg(&grf
->gpio3a_iomux
,
128 GRF_GPIO3A4_SEL_MASK
| GRF_GPIO3A5_SEL_SHIFT
129 | GRF_GPIO3A6_SEL_SHIFT
,
130 GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A4_SEL_SHIFT
131 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A5_SEL_SHIFT
132 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A6_SEL_SHIFT
);
137 rk_clrsetreg(&pmugrf
->gpio1a_iomux
,
138 PMUGRF_GPIO1A7_SEL_MASK
,
139 PMUGRF_SPI1EC_RXD
<< PMUGRF_GPIO1A7_SEL_SHIFT
);
140 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
141 PMUGRF_GPIO1B0_SEL_MASK
| PMUGRF_GPIO1B1_SEL_MASK
142 | PMUGRF_GPIO1B2_SEL_MASK
,
143 PMUGRF_SPI1EC_TXD
<< PMUGRF_GPIO1B0_SEL_SHIFT
144 | PMUGRF_SPI1EC_CLK
<< PMUGRF_GPIO1B1_SEL_SHIFT
145 | PMUGRF_SPI1EC_CSN0
<< PMUGRF_GPIO1B2_SEL_SHIFT
);
150 rk_clrsetreg(&grf
->gpio2b_iomux
,
151 GRF_GPIO2B1_SEL_MASK
| GRF_GPIO2B2_SEL_MASK
152 | GRF_GPIO2B3_SEL_MASK
| GRF_GPIO2B4_SEL_MASK
,
153 GRF_SPI2TPM_RXD
<< GRF_GPIO2B1_SEL_SHIFT
154 | GRF_SPI2TPM_TXD
<< GRF_GPIO2B2_SEL_SHIFT
155 | GRF_SPI2TPM_CLK
<< GRF_GPIO2B3_SEL_SHIFT
156 | GRF_SPI2TPM_CSN0
<< GRF_GPIO2B4_SEL_SHIFT
);
161 rk_clrsetreg(&grf
->gpio2c_iomux
,
162 GRF_GPIO2C4_SEL_MASK
| GRF_GPIO2C5_SEL_MASK
163 | GRF_GPIO2C6_SEL_MASK
| GRF_GPIO2C7_SEL_MASK
,
164 GRF_SPI5EXPPLUS_RXD
<< GRF_GPIO2C4_SEL_SHIFT
165 | GRF_SPI5EXPPLUS_TXD
<< GRF_GPIO2C5_SEL_SHIFT
166 | GRF_SPI5EXPPLUS_CLK
<< GRF_GPIO2C6_SEL_SHIFT
167 | GRF_SPI5EXPPLUS_CSN0
<< GRF_GPIO2C7_SEL_SHIFT
);
170 printf("%s: spi_id %d is not supported.\n", __func__
, spi_id
);
176 debug("rkspi: periph%d cs=%d not supported", spi_id
, cs
);
180 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs
*grf
,
181 struct rk3399_pmugrf_regs
*pmugrf
,
185 case PERIPH_ID_UART2
:
186 /* Using channel-C by default */
187 rk_clrsetreg(&grf
->gpio4c_iomux
,
188 GRF_GPIO4C3_SEL_MASK
,
189 GRF_UART2DGBC_SIN
<< GRF_GPIO4C3_SEL_SHIFT
);
190 rk_clrsetreg(&grf
->gpio4c_iomux
,
191 GRF_GPIO4C4_SEL_MASK
,
192 GRF_UART2DBGC_SOUT
<< GRF_GPIO4C4_SEL_SHIFT
);
194 case PERIPH_ID_UART0
:
195 case PERIPH_ID_UART1
:
196 case PERIPH_ID_UART3
:
197 case PERIPH_ID_UART4
:
199 debug("uart id = %d iomux error!\n", uart_id
);
204 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs
*grf
, int mmc_id
)
209 case PERIPH_ID_SDCARD
:
210 rk_clrsetreg(&grf
->gpio4b_iomux
,
211 GRF_GPIO4B0_SEL_MASK
| GRF_GPIO4B1_SEL_MASK
212 | GRF_GPIO4B2_SEL_MASK
| GRF_GPIO4B3_SEL_MASK
213 | GRF_GPIO4B4_SEL_MASK
| GRF_GPIO4B5_SEL_MASK
,
214 GRF_SDMMC_DATA0
<< GRF_GPIO4B0_SEL_SHIFT
215 | GRF_SDMMC_DATA1
<< GRF_GPIO4B1_SEL_SHIFT
216 | GRF_SDMMC_DATA2
<< GRF_GPIO4B2_SEL_SHIFT
217 | GRF_SDMMC_DATA3
<< GRF_GPIO4B3_SEL_SHIFT
218 | GRF_SDMMC_CLKOUT
<< GRF_GPIO4B4_SEL_SHIFT
219 | GRF_SDMMC_CMD
<< GRF_GPIO4B5_SEL_SHIFT
);
222 debug("mmc id = %d iomux error!\n", mmc_id
);
227 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
228 static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs
*grf
, int mmc_id
)
230 rk_clrsetreg(&grf
->gpio3a_iomux
,
231 GRF_GPIO3A0_SEL_MASK
| GRF_GPIO3A1_SEL_MASK
|
232 GRF_GPIO3A2_SEL_MASK
| GRF_GPIO3A3_SEL_MASK
|
233 GRF_GPIO3A4_SEL_MASK
| GRF_GPIO3A5_SEL_MASK
|
234 GRF_GPIO3A6_SEL_MASK
| GRF_GPIO3A7_SEL_MASK
,
235 GRF_MAC_TXD2
<< GRF_GPIO3A0_SEL_SHIFT
|
236 GRF_MAC_TXD3
<< GRF_GPIO3A1_SEL_SHIFT
|
237 GRF_MAC_RXD2
<< GRF_GPIO3A2_SEL_SHIFT
|
238 GRF_MAC_RXD3
<< GRF_GPIO3A3_SEL_SHIFT
|
239 GRF_MAC_TXD0
<< GRF_GPIO3A4_SEL_SHIFT
|
240 GRF_MAC_TXD1
<< GRF_GPIO3A5_SEL_SHIFT
|
241 GRF_MAC_RXD0
<< GRF_GPIO3A6_SEL_SHIFT
|
242 GRF_MAC_RXD1
<< GRF_GPIO3A7_SEL_SHIFT
);
243 rk_clrsetreg(&grf
->gpio3b_iomux
,
244 GRF_GPIO3B0_SEL_MASK
| GRF_GPIO3B1_SEL_MASK
|
245 GRF_GPIO3B3_SEL_MASK
|
246 GRF_GPIO3B4_SEL_MASK
| GRF_GPIO3B5_SEL_MASK
|
247 GRF_GPIO3B6_SEL_MASK
,
248 GRF_MAC_MDC
<< GRF_GPIO3B0_SEL_SHIFT
|
249 GRF_MAC_RXDV
<< GRF_GPIO3B1_SEL_SHIFT
|
250 GRF_MAC_CLK
<< GRF_GPIO3B3_SEL_SHIFT
|
251 GRF_MAC_TXEN
<< GRF_GPIO3B4_SEL_SHIFT
|
252 GRF_MAC_MDIO
<< GRF_GPIO3B5_SEL_SHIFT
|
253 GRF_MAC_RXCLK
<< GRF_GPIO3B6_SEL_SHIFT
);
254 rk_clrsetreg(&grf
->gpio3c_iomux
,
255 GRF_GPIO3C1_SEL_MASK
,
256 GRF_MAC_TXCLK
<< GRF_GPIO3C1_SEL_SHIFT
);
258 /* Set drive strength for GMAC tx io, value 3 means 13mA */
259 rk_clrsetreg(&grf
->gpio3_e
[0],
260 GRF_GPIO3A0_E_MASK
| GRF_GPIO3A1_E_MASK
|
261 GRF_GPIO3A4_E_MASK
| GRF_GPIO3A5_E0_MASK
,
262 3 << GRF_GPIO3A0_E_SHIFT
|
263 3 << GRF_GPIO3A1_E_SHIFT
|
264 3 << GRF_GPIO3A4_E_SHIFT
|
265 1 << GRF_GPIO3A5_E0_SHIFT
);
266 rk_clrsetreg(&grf
->gpio3_e
[1],
267 GRF_GPIO3A5_E12_MASK
,
268 1 << GRF_GPIO3A5_E12_SHIFT
);
269 rk_clrsetreg(&grf
->gpio3_e
[2],
271 3 << GRF_GPIO3B4_E_SHIFT
);
272 rk_clrsetreg(&grf
->gpio3_e
[4],
274 3 << GRF_GPIO3C1_E_SHIFT
);
278 #if !defined(CONFIG_SPL_BUILD)
279 static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs
*grf
, int hdmi_id
)
283 rk_clrsetreg(&grf
->gpio4c_iomux
,
284 GRF_GPIO4C0_SEL_MASK
| GRF_GPIO4C1_SEL_MASK
,
285 (GRF_HDMII2C_SCL
<< GRF_GPIO4C0_SEL_SHIFT
) |
286 (GRF_HDMII2C_SDA
<< GRF_GPIO4C1_SEL_SHIFT
));
289 debug("%s: hdmi_id = %d unsupported\n", __func__
, hdmi_id
);
295 static int rk3399_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
297 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
299 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
306 pinctrl_rk3399_pwm_config(priv
->grf
, priv
->pmugrf
, func
);
317 pinctrl_rk3399_i2c_config(priv
->grf
, priv
->pmugrf
, func
);
325 pinctrl_rk3399_spi_config(priv
->grf
, priv
->pmugrf
, func
, flags
);
327 case PERIPH_ID_UART0
:
328 case PERIPH_ID_UART1
:
329 case PERIPH_ID_UART2
:
330 case PERIPH_ID_UART3
:
331 case PERIPH_ID_UART4
:
332 pinctrl_rk3399_uart_config(priv
->grf
, priv
->pmugrf
, func
);
334 case PERIPH_ID_LCDC0
:
335 case PERIPH_ID_LCDC1
:
336 pinctrl_rk3399_lcdc_config(priv
->grf
, func
);
338 case PERIPH_ID_SDMMC0
:
339 case PERIPH_ID_SDMMC1
:
340 pinctrl_rk3399_sdmmc_config(priv
->grf
, func
);
342 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
344 pinctrl_rk3399_gmac_config(priv
->grf
, func
);
347 #if !defined(CONFIG_SPL_BUILD)
349 pinctrl_rk3399_hdmi_config(priv
->grf
, func
);
359 static int rk3399_pinctrl_get_periph_id(struct udevice
*dev
,
360 struct udevice
*periph
)
362 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
366 ret
= dev_read_u32_array(periph
, "interrupts", cell
, ARRAY_SIZE(cell
));
372 return PERIPH_ID_SPI0
;
374 return PERIPH_ID_SPI1
;
376 return PERIPH_ID_SPI2
;
378 return PERIPH_ID_SPI5
;
380 return PERIPH_ID_I2C0
;
381 case 59: /* Note strange order */
382 return PERIPH_ID_I2C1
;
384 return PERIPH_ID_I2C2
;
386 return PERIPH_ID_I2C3
;
388 return PERIPH_ID_I2C4
;
390 return PERIPH_ID_I2C5
;
392 return PERIPH_ID_I2C6
;
394 return PERIPH_ID_I2C7
;
396 return PERIPH_ID_I2C8
;
398 return PERIPH_ID_SDMMC1
;
399 #if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
401 return PERIPH_ID_GMAC
;
403 #if !defined(CONFIG_SPL_BUILD)
405 return PERIPH_ID_HDMI
;
412 static int rk3399_pinctrl_set_state_simple(struct udevice
*dev
,
413 struct udevice
*periph
)
417 func
= rk3399_pinctrl_get_periph_id(dev
, periph
);
421 return rk3399_pinctrl_request(dev
, func
, 0);
424 static struct pinctrl_ops rk3399_pinctrl_ops
= {
425 .set_state_simple
= rk3399_pinctrl_set_state_simple
,
426 .request
= rk3399_pinctrl_request
,
427 .get_periph_id
= rk3399_pinctrl_get_periph_id
,
430 static int rk3399_pinctrl_probe(struct udevice
*dev
)
432 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
435 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
436 priv
->pmugrf
= syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF
);
437 debug("%s: grf=%p, pmugrf=%p\n", __func__
, priv
->grf
, priv
->pmugrf
);
442 static const struct udevice_id rk3399_pinctrl_ids
[] = {
443 { .compatible
= "rockchip,rk3399-pinctrl" },
447 U_BOOT_DRIVER(pinctrl_rk3399
) = {
448 .name
= "rockchip_rk3399_pinctrl",
449 .id
= UCLASS_PINCTRL
,
450 .of_match
= rk3399_pinctrl_ids
,
451 .priv_auto_alloc_size
= sizeof(struct rk3399_pinctrl_priv
),
452 .ops
= &rk3399_pinctrl_ops
,
453 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
454 .bind
= dm_scan_fdt_dev
,
456 .probe
= rk3399_pinctrl_probe
,