2 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
4 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/grf_rk3399.h>
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/periph.h>
15 #include <asm/arch/clock.h>
16 #include <dm/pinctrl.h>
18 DECLARE_GLOBAL_DATA_PTR
;
20 struct rk3399_pinctrl_priv
{
21 struct rk3399_grf_regs
*grf
;
22 struct rk3399_pmugrf_regs
*pmugrf
;
25 static void pinctrl_rk3399_pwm_config(struct rk3399_grf_regs
*grf
,
26 struct rk3399_pmugrf_regs
*pmugrf
, int pwm_id
)
30 rk_clrsetreg(&grf
->gpio4c_iomux
,
32 GRF_PWM_0
<< GRF_GPIO4C2_SEL_SHIFT
);
35 rk_clrsetreg(&grf
->gpio4c_iomux
,
37 GRF_PWM_1
<< GRF_GPIO4C6_SEL_SHIFT
);
40 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
41 PMUGRF_GPIO1C3_SEL_MASK
,
42 PMUGRF_PWM_2
<< PMUGRF_GPIO1C3_SEL_SHIFT
);
45 if (readl(&pmugrf
->soc_con0
) & (1 << 5))
46 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
47 PMUGRF_GPIO1B6_SEL_MASK
,
48 PMUGRF_PWM_3B
<< PMUGRF_GPIO1B6_SEL_SHIFT
);
50 rk_clrsetreg(&pmugrf
->gpio0a_iomux
,
51 PMUGRF_GPIO0A6_SEL_MASK
,
52 PMUGRF_PWM_3A
<< PMUGRF_GPIO0A6_SEL_SHIFT
);
55 debug("pwm id = %d iomux error!\n", pwm_id
);
60 static void pinctrl_rk3399_i2c_config(struct rk3399_grf_regs
*grf
,
61 struct rk3399_pmugrf_regs
*pmugrf
,
66 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
67 PMUGRF_GPIO1B7_SEL_MASK
,
68 PMUGRF_I2C0PMU_SDA
<< PMUGRF_GPIO1B7_SEL_SHIFT
);
69 rk_clrsetreg(&pmugrf
->gpio1c_iomux
,
70 PMUGRF_GPIO1C0_SEL_MASK
,
71 PMUGRF_I2C0PMU_SCL
<< PMUGRF_GPIO1C0_SEL_SHIFT
);
79 debug("i2c id = %d iomux error!\n", i2c_id
);
84 static void pinctrl_rk3399_lcdc_config(struct rk3399_grf_regs
*grf
, int lcd_id
)
90 debug("lcdc id = %d iomux error!\n", lcd_id
);
95 static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs
*grf
,
96 struct rk3399_pmugrf_regs
*pmugrf
,
97 enum periph_id spi_id
, int cs
)
103 rk_clrsetreg(&grf
->gpio3a_iomux
,
104 GRF_GPIO3A7_SEL_MASK
,
105 GRF_SPI0NORCODEC_CSN0
106 << GRF_GPIO3A7_SEL_SHIFT
);
109 rk_clrsetreg(&grf
->gpio3b_iomux
,
110 GRF_GPIO3B0_SEL_MASK
,
111 GRF_SPI0NORCODEC_CSN1
112 << GRF_GPIO3B0_SEL_SHIFT
);
117 rk_clrsetreg(&grf
->gpio3a_iomux
,
118 GRF_GPIO3A4_SEL_MASK
| GRF_GPIO3A5_SEL_SHIFT
119 | GRF_GPIO3A6_SEL_SHIFT
,
120 GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A4_SEL_SHIFT
121 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A5_SEL_SHIFT
122 | GRF_SPI0NORCODEC_RXD
<< GRF_GPIO3A6_SEL_SHIFT
);
127 rk_clrsetreg(&pmugrf
->gpio1a_iomux
,
128 PMUGRF_GPIO1A7_SEL_MASK
,
129 PMUGRF_SPI1EC_RXD
<< PMUGRF_GPIO1A7_SEL_SHIFT
);
130 rk_clrsetreg(&pmugrf
->gpio1b_iomux
,
131 PMUGRF_GPIO1B0_SEL_MASK
| PMUGRF_GPIO1B1_SEL_MASK
132 | PMUGRF_GPIO1B2_SEL_MASK
,
133 PMUGRF_SPI1EC_TXD
<< PMUGRF_GPIO1B0_SEL_SHIFT
134 | PMUGRF_SPI1EC_CLK
<< PMUGRF_GPIO1B1_SEL_SHIFT
135 | PMUGRF_SPI1EC_CSN0
<< PMUGRF_GPIO1B2_SEL_SHIFT
);
140 rk_clrsetreg(&grf
->gpio2b_iomux
,
141 GRF_GPIO2B1_SEL_MASK
| GRF_GPIO2B2_SEL_MASK
142 | GRF_GPIO2B3_SEL_MASK
| GRF_GPIO2B4_SEL_MASK
,
143 GRF_SPI2TPM_RXD
<< GRF_GPIO2B1_SEL_SHIFT
144 | GRF_SPI2TPM_TXD
<< GRF_GPIO2B2_SEL_SHIFT
145 | GRF_SPI2TPM_CLK
<< GRF_GPIO2B3_SEL_SHIFT
146 | GRF_SPI2TPM_CSN0
<< GRF_GPIO2B4_SEL_SHIFT
);
154 debug("rkspi: periph%d cs=%d not supported", spi_id
, cs
);
158 static void pinctrl_rk3399_uart_config(struct rk3399_grf_regs
*grf
,
159 struct rk3399_pmugrf_regs
*pmugrf
,
163 case PERIPH_ID_UART2
:
164 /* Using channel-C by default */
165 rk_clrsetreg(&grf
->gpio4c_iomux
,
166 GRF_GPIO4C3_SEL_MASK
,
167 GRF_UART2DGBC_SIN
<< GRF_GPIO4C3_SEL_SHIFT
);
168 rk_clrsetreg(&grf
->gpio4c_iomux
,
169 GRF_GPIO4C4_SEL_MASK
,
170 GRF_UART2DBGC_SOUT
<< GRF_GPIO4C4_SEL_SHIFT
);
172 case PERIPH_ID_UART0
:
173 case PERIPH_ID_UART1
:
174 case PERIPH_ID_UART3
:
175 case PERIPH_ID_UART4
:
177 debug("uart id = %d iomux error!\n", uart_id
);
182 static void pinctrl_rk3399_sdmmc_config(struct rk3399_grf_regs
*grf
, int mmc_id
)
187 case PERIPH_ID_SDCARD
:
188 rk_clrsetreg(&grf
->gpio4b_iomux
,
189 GRF_GPIO4B0_SEL_MASK
| GRF_GPIO4B1_SEL_MASK
190 | GRF_GPIO4B2_SEL_MASK
| GRF_GPIO4B3_SEL_MASK
191 | GRF_GPIO4B4_SEL_MASK
| GRF_GPIO4B5_SEL_MASK
,
192 GRF_SDMMC_DATA0
<< GRF_GPIO4B0_SEL_SHIFT
193 | GRF_SDMMC_DATA1
<< GRF_GPIO4B1_SEL_SHIFT
194 | GRF_SDMMC_DATA2
<< GRF_GPIO4B2_SEL_SHIFT
195 | GRF_SDMMC_DATA3
<< GRF_GPIO4B3_SEL_SHIFT
196 | GRF_SDMMC_CLKOUT
<< GRF_GPIO4B4_SEL_SHIFT
197 | GRF_SDMMC_CMD
<< GRF_GPIO4B5_SEL_SHIFT
);
200 debug("mmc id = %d iomux error!\n", mmc_id
);
205 static int rk3399_pinctrl_request(struct udevice
*dev
, int func
, int flags
)
207 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
209 debug("%s: func=%x, flags=%x\n", __func__
, func
, flags
);
216 pinctrl_rk3399_pwm_config(priv
->grf
, priv
->pmugrf
, func
);
224 pinctrl_rk3399_i2c_config(priv
->grf
, priv
->pmugrf
, func
);
229 pinctrl_rk3399_spi_config(priv
->grf
, priv
->pmugrf
, func
, flags
);
231 case PERIPH_ID_UART0
:
232 case PERIPH_ID_UART1
:
233 case PERIPH_ID_UART2
:
234 case PERIPH_ID_UART3
:
235 case PERIPH_ID_UART4
:
236 pinctrl_rk3399_uart_config(priv
->grf
, priv
->pmugrf
, func
);
238 case PERIPH_ID_LCDC0
:
239 case PERIPH_ID_LCDC1
:
240 pinctrl_rk3399_lcdc_config(priv
->grf
, func
);
242 case PERIPH_ID_SDMMC0
:
243 case PERIPH_ID_SDMMC1
:
244 pinctrl_rk3399_sdmmc_config(priv
->grf
, func
);
253 static int rk3399_pinctrl_get_periph_id(struct udevice
*dev
,
254 struct udevice
*periph
)
259 ret
= fdtdec_get_int_array(gd
->fdt_blob
, dev_of_offset(periph
),
260 "interrupts", cell
, ARRAY_SIZE(cell
));
266 return PERIPH_ID_SPI0
;
268 return PERIPH_ID_SPI1
;
270 return PERIPH_ID_SPI2
;
272 return PERIPH_ID_I2C0
;
273 case 59: /* Note strange order */
274 return PERIPH_ID_I2C1
;
276 return PERIPH_ID_I2C2
;
278 return PERIPH_ID_I2C3
;
280 return PERIPH_ID_I2C4
;
282 return PERIPH_ID_I2C5
;
284 return PERIPH_ID_SDMMC1
;
290 static int rk3399_pinctrl_set_state_simple(struct udevice
*dev
,
291 struct udevice
*periph
)
295 func
= rk3399_pinctrl_get_periph_id(dev
, periph
);
299 return rk3399_pinctrl_request(dev
, func
, 0);
302 static struct pinctrl_ops rk3399_pinctrl_ops
= {
303 .set_state_simple
= rk3399_pinctrl_set_state_simple
,
304 .request
= rk3399_pinctrl_request
,
305 .get_periph_id
= rk3399_pinctrl_get_periph_id
,
308 static int rk3399_pinctrl_probe(struct udevice
*dev
)
310 struct rk3399_pinctrl_priv
*priv
= dev_get_priv(dev
);
313 priv
->grf
= syscon_get_first_range(ROCKCHIP_SYSCON_GRF
);
314 priv
->pmugrf
= syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF
);
315 debug("%s: grf=%p, pmugrf=%p\n", __func__
, priv
->grf
, priv
->pmugrf
);
320 static const struct udevice_id rk3399_pinctrl_ids
[] = {
321 { .compatible
= "rockchip,rk3399-pinctrl" },
325 U_BOOT_DRIVER(pinctrl_rk3399
) = {
326 .name
= "rockchip_rk3399_pinctrl",
327 .id
= UCLASS_PINCTRL
,
328 .of_match
= rk3399_pinctrl_ids
,
329 .priv_auto_alloc_size
= sizeof(struct rk3399_pinctrl_priv
),
330 .ops
= &rk3399_pinctrl_ops
,
331 .bind
= dm_scan_fdt_dev
,
332 .probe
= rk3399_pinctrl_probe
,