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Merge tag 'kvm-x86-mmu-6.7' of https://github.com/kvm-x86/linux into HEAD
[thirdparty/kernel/stable.git] / drivers / pinctrl / starfive / pinctrl-starfive-jh7110.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
4 *
5 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
6 * Copyright (C) 2022 StarFive Technology Co., Ltd.
7 */
8
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/io.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/seq_file.h>
20 #include <linux/spinlock.h>
21
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26
27 #include <dt-bindings/pinctrl/starfive,jh7110-pinctrl.h>
28
29 #include "../core.h"
30 #include "../pinctrl-utils.h"
31 #include "../pinmux.h"
32 #include "../pinconf.h"
33 #include "pinctrl-starfive-jh7110.h"
34
35 /* pad control bits */
36 #define JH7110_PADCFG_POS BIT(7)
37 #define JH7110_PADCFG_SMT BIT(6)
38 #define JH7110_PADCFG_SLEW BIT(5)
39 #define JH7110_PADCFG_PD BIT(4)
40 #define JH7110_PADCFG_PU BIT(3)
41 #define JH7110_PADCFG_BIAS (JH7110_PADCFG_PD | JH7110_PADCFG_PU)
42 #define JH7110_PADCFG_DS_MASK GENMASK(2, 1)
43 #define JH7110_PADCFG_DS_2MA (0U << 1)
44 #define JH7110_PADCFG_DS_4MA BIT(1)
45 #define JH7110_PADCFG_DS_8MA (2U << 1)
46 #define JH7110_PADCFG_DS_12MA (3U << 1)
47 #define JH7110_PADCFG_IE BIT(0)
48
49 /*
50 * The packed pinmux values from the device tree look like this:
51 *
52 * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
53 * | din | dout | doen | function | pin |
54 */
55 static unsigned int jh7110_pinmux_din(u32 v)
56 {
57 return (v & GENMASK(31, 24)) >> 24;
58 }
59
60 static u32 jh7110_pinmux_dout(u32 v)
61 {
62 return (v & GENMASK(23, 16)) >> 16;
63 }
64
65 static u32 jh7110_pinmux_doen(u32 v)
66 {
67 return (v & GENMASK(15, 10)) >> 10;
68 }
69
70 static u32 jh7110_pinmux_function(u32 v)
71 {
72 return (v & GENMASK(9, 8)) >> 8;
73 }
74
75 static unsigned int jh7110_pinmux_pin(u32 v)
76 {
77 return v & GENMASK(7, 0);
78 }
79
80 static struct jh7110_pinctrl *jh7110_from_irq_data(struct irq_data *d)
81 {
82 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
83
84 return container_of(gc, struct jh7110_pinctrl, gc);
85 }
86
87 struct jh7110_pinctrl *jh7110_from_irq_desc(struct irq_desc *desc)
88 {
89 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
90
91 return container_of(gc, struct jh7110_pinctrl, gc);
92 }
93 EXPORT_SYMBOL_GPL(jh7110_from_irq_desc);
94
95 #ifdef CONFIG_DEBUG_FS
96 static void jh7110_pin_dbg_show(struct pinctrl_dev *pctldev,
97 struct seq_file *s, unsigned int pin)
98 {
99 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
100 const struct jh7110_pinctrl_soc_info *info = sfp->info;
101
102 seq_printf(s, "%s", dev_name(pctldev->dev));
103
104 if (pin < sfp->gc.ngpio) {
105 unsigned int offset = 4 * (pin / 4);
106 unsigned int shift = 8 * (pin % 4);
107 u32 dout = readl_relaxed(sfp->base + info->dout_reg_base + offset);
108 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
109 u32 gpi = readl_relaxed(sfp->base + info->gpi_reg_base + offset);
110
111 dout = (dout >> shift) & info->dout_mask;
112 doen = (doen >> shift) & info->doen_mask;
113 gpi = ((gpi >> shift) - 2) & info->gpi_mask;
114
115 seq_printf(s, " dout=%u doen=%u din=%u", dout, doen, gpi);
116 }
117 }
118 #else
119 #define jh7110_pin_dbg_show NULL
120 #endif
121
122 static int jh7110_dt_node_to_map(struct pinctrl_dev *pctldev,
123 struct device_node *np,
124 struct pinctrl_map **maps,
125 unsigned int *num_maps)
126 {
127 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
128 struct device *dev = sfp->gc.parent;
129 struct device_node *child;
130 struct pinctrl_map *map;
131 const char **pgnames;
132 const char *grpname;
133 int ngroups;
134 int nmaps;
135 int ret;
136
137 ngroups = 0;
138 for_each_child_of_node(np, child)
139 ngroups += 1;
140 nmaps = 2 * ngroups;
141
142 pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
143 if (!pgnames)
144 return -ENOMEM;
145
146 map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
147 if (!map)
148 return -ENOMEM;
149
150 nmaps = 0;
151 ngroups = 0;
152 mutex_lock(&sfp->mutex);
153 for_each_child_of_node(np, child) {
154 int npins = of_property_count_u32_elems(child, "pinmux");
155 int *pins;
156 u32 *pinmux;
157 int i;
158
159 if (npins < 1) {
160 dev_err(dev,
161 "invalid pinctrl group %pOFn.%pOFn: pinmux not set\n",
162 np, child);
163 ret = -EINVAL;
164 goto put_child;
165 }
166
167 grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
168 if (!grpname) {
169 ret = -ENOMEM;
170 goto put_child;
171 }
172
173 pgnames[ngroups++] = grpname;
174
175 pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
176 if (!pins) {
177 ret = -ENOMEM;
178 goto put_child;
179 }
180
181 pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
182 if (!pinmux) {
183 ret = -ENOMEM;
184 goto put_child;
185 }
186
187 ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
188 if (ret)
189 goto put_child;
190
191 for (i = 0; i < npins; i++)
192 pins[i] = jh7110_pinmux_pin(pinmux[i]);
193
194 map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
195 map[nmaps].data.mux.function = np->name;
196 map[nmaps].data.mux.group = grpname;
197 nmaps += 1;
198
199 ret = pinctrl_generic_add_group(pctldev, grpname,
200 pins, npins, pinmux);
201 if (ret < 0) {
202 dev_err(dev, "error adding group %s: %d\n", grpname, ret);
203 goto put_child;
204 }
205
206 ret = pinconf_generic_parse_dt_config(child, pctldev,
207 &map[nmaps].data.configs.configs,
208 &map[nmaps].data.configs.num_configs);
209 if (ret) {
210 dev_err(dev, "error parsing pin config of group %s: %d\n",
211 grpname, ret);
212 goto put_child;
213 }
214
215 /* don't create a map if there are no pinconf settings */
216 if (map[nmaps].data.configs.num_configs == 0)
217 continue;
218
219 map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
220 map[nmaps].data.configs.group_or_pin = grpname;
221 nmaps += 1;
222 }
223
224 ret = pinmux_generic_add_function(pctldev, np->name,
225 pgnames, ngroups, NULL);
226 if (ret < 0) {
227 dev_err(dev, "error adding function %s: %d\n", np->name, ret);
228 goto free_map;
229 }
230 mutex_unlock(&sfp->mutex);
231
232 *maps = map;
233 *num_maps = nmaps;
234 return 0;
235
236 put_child:
237 of_node_put(child);
238 free_map:
239 pinctrl_utils_free_map(pctldev, map, nmaps);
240 mutex_unlock(&sfp->mutex);
241 return ret;
242 }
243
244 static const struct pinctrl_ops jh7110_pinctrl_ops = {
245 .get_groups_count = pinctrl_generic_get_group_count,
246 .get_group_name = pinctrl_generic_get_group_name,
247 .get_group_pins = pinctrl_generic_get_group_pins,
248 .pin_dbg_show = jh7110_pin_dbg_show,
249 .dt_node_to_map = jh7110_dt_node_to_map,
250 .dt_free_map = pinctrl_utils_free_map,
251 };
252
253 void jh7110_set_gpiomux(struct jh7110_pinctrl *sfp, unsigned int pin,
254 unsigned int din, u32 dout, u32 doen)
255 {
256 const struct jh7110_pinctrl_soc_info *info = sfp->info;
257
258 unsigned int offset = 4 * (pin / 4);
259 unsigned int shift = 8 * (pin % 4);
260 u32 dout_mask = info->dout_mask << shift;
261 u32 done_mask = info->doen_mask << shift;
262 u32 ival, imask;
263 void __iomem *reg_dout;
264 void __iomem *reg_doen;
265 void __iomem *reg_din;
266 unsigned long flags;
267
268 reg_dout = sfp->base + info->dout_reg_base + offset;
269 reg_doen = sfp->base + info->doen_reg_base + offset;
270 dout <<= shift;
271 doen <<= shift;
272 if (din != GPI_NONE) {
273 unsigned int ioffset = 4 * (din / 4);
274 unsigned int ishift = 8 * (din % 4);
275
276 reg_din = sfp->base + info->gpi_reg_base + ioffset;
277 ival = (pin + 2) << ishift;
278 imask = info->gpi_mask << ishift;
279 } else {
280 reg_din = NULL;
281 }
282
283 raw_spin_lock_irqsave(&sfp->lock, flags);
284 dout |= readl_relaxed(reg_dout) & ~dout_mask;
285 writel_relaxed(dout, reg_dout);
286 doen |= readl_relaxed(reg_doen) & ~done_mask;
287 writel_relaxed(doen, reg_doen);
288 if (reg_din) {
289 ival |= readl_relaxed(reg_din) & ~imask;
290 writel_relaxed(ival, reg_din);
291 }
292 raw_spin_unlock_irqrestore(&sfp->lock, flags);
293 }
294 EXPORT_SYMBOL_GPL(jh7110_set_gpiomux);
295
296 static int jh7110_set_mux(struct pinctrl_dev *pctldev,
297 unsigned int fsel, unsigned int gsel)
298 {
299 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
300 const struct jh7110_pinctrl_soc_info *info = sfp->info;
301 const struct group_desc *group;
302 const u32 *pinmux;
303 unsigned int i;
304
305 group = pinctrl_generic_get_group(pctldev, gsel);
306 if (!group)
307 return -EINVAL;
308
309 pinmux = group->data;
310 for (i = 0; i < group->num_pins; i++) {
311 u32 v = pinmux[i];
312
313 if (info->jh7110_set_one_pin_mux)
314 info->jh7110_set_one_pin_mux(sfp,
315 jh7110_pinmux_pin(v),
316 jh7110_pinmux_din(v),
317 jh7110_pinmux_dout(v),
318 jh7110_pinmux_doen(v),
319 jh7110_pinmux_function(v));
320 }
321
322 return 0;
323 }
324
325 static const struct pinmux_ops jh7110_pinmux_ops = {
326 .get_functions_count = pinmux_generic_get_function_count,
327 .get_function_name = pinmux_generic_get_function_name,
328 .get_function_groups = pinmux_generic_get_function_groups,
329 .set_mux = jh7110_set_mux,
330 .strict = true,
331 };
332
333 static const u8 jh7110_drive_strength_mA[4] = { 2, 4, 8, 12 };
334
335 static u32 jh7110_padcfg_ds_to_mA(u32 padcfg)
336 {
337 return jh7110_drive_strength_mA[(padcfg >> 1) & 3U];
338 }
339
340 static u32 jh7110_padcfg_ds_from_mA(u32 v)
341 {
342 int i;
343
344 for (i = 0; i < 3; i++) {
345 if (v <= jh7110_drive_strength_mA[i])
346 break;
347 }
348 return i << 1;
349 }
350
351 static void jh7110_padcfg_rmw(struct jh7110_pinctrl *sfp,
352 unsigned int pin, u32 mask, u32 value)
353 {
354 const struct jh7110_pinctrl_soc_info *info = sfp->info;
355 void __iomem *reg;
356 unsigned long flags;
357 int padcfg_base;
358
359 if (!info->jh7110_get_padcfg_base)
360 return;
361
362 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
363 if (padcfg_base < 0)
364 return;
365
366 reg = sfp->base + padcfg_base + 4 * pin;
367 value &= mask;
368
369 raw_spin_lock_irqsave(&sfp->lock, flags);
370 value |= readl_relaxed(reg) & ~mask;
371 writel_relaxed(value, reg);
372 raw_spin_unlock_irqrestore(&sfp->lock, flags);
373 }
374
375 static int jh7110_pinconf_get(struct pinctrl_dev *pctldev,
376 unsigned int pin, unsigned long *config)
377 {
378 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
379 const struct jh7110_pinctrl_soc_info *info = sfp->info;
380 int param = pinconf_to_config_param(*config);
381 u32 padcfg, arg;
382 bool enabled;
383 int padcfg_base;
384
385 if (!info->jh7110_get_padcfg_base)
386 return 0;
387
388 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
389 if (padcfg_base < 0)
390 return 0;
391
392 padcfg = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
393 switch (param) {
394 case PIN_CONFIG_BIAS_DISABLE:
395 enabled = !(padcfg & JH7110_PADCFG_BIAS);
396 arg = 0;
397 break;
398 case PIN_CONFIG_BIAS_PULL_DOWN:
399 enabled = padcfg & JH7110_PADCFG_PD;
400 arg = 1;
401 break;
402 case PIN_CONFIG_BIAS_PULL_UP:
403 enabled = padcfg & JH7110_PADCFG_PU;
404 arg = 1;
405 break;
406 case PIN_CONFIG_DRIVE_STRENGTH:
407 enabled = true;
408 arg = jh7110_padcfg_ds_to_mA(padcfg);
409 break;
410 case PIN_CONFIG_INPUT_ENABLE:
411 enabled = padcfg & JH7110_PADCFG_IE;
412 arg = enabled;
413 break;
414 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
415 enabled = padcfg & JH7110_PADCFG_SMT;
416 arg = enabled;
417 break;
418 case PIN_CONFIG_SLEW_RATE:
419 enabled = true;
420 arg = !!(padcfg & JH7110_PADCFG_SLEW);
421 break;
422 default:
423 return -ENOTSUPP;
424 }
425
426 *config = pinconf_to_config_packed(param, arg);
427 return enabled ? 0 : -EINVAL;
428 }
429
430 static int jh7110_pinconf_group_get(struct pinctrl_dev *pctldev,
431 unsigned int gsel,
432 unsigned long *config)
433 {
434 const struct group_desc *group;
435
436 group = pinctrl_generic_get_group(pctldev, gsel);
437 if (!group)
438 return -EINVAL;
439
440 return jh7110_pinconf_get(pctldev, group->pins[0], config);
441 }
442
443 static int jh7110_pinconf_group_set(struct pinctrl_dev *pctldev,
444 unsigned int gsel,
445 unsigned long *configs,
446 unsigned int num_configs)
447 {
448 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
449 const struct group_desc *group;
450 u16 mask, value;
451 int i;
452
453 group = pinctrl_generic_get_group(pctldev, gsel);
454 if (!group)
455 return -EINVAL;
456
457 mask = 0;
458 value = 0;
459 for (i = 0; i < num_configs; i++) {
460 int param = pinconf_to_config_param(configs[i]);
461 u32 arg = pinconf_to_config_argument(configs[i]);
462
463 switch (param) {
464 case PIN_CONFIG_BIAS_DISABLE:
465 mask |= JH7110_PADCFG_BIAS;
466 value &= ~JH7110_PADCFG_BIAS;
467 break;
468 case PIN_CONFIG_BIAS_PULL_DOWN:
469 if (arg == 0)
470 return -ENOTSUPP;
471 mask |= JH7110_PADCFG_BIAS;
472 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PD;
473 break;
474 case PIN_CONFIG_BIAS_PULL_UP:
475 if (arg == 0)
476 return -ENOTSUPP;
477 mask |= JH7110_PADCFG_BIAS;
478 value = (value & ~JH7110_PADCFG_BIAS) | JH7110_PADCFG_PU;
479 break;
480 case PIN_CONFIG_DRIVE_STRENGTH:
481 mask |= JH7110_PADCFG_DS_MASK;
482 value = (value & ~JH7110_PADCFG_DS_MASK) |
483 jh7110_padcfg_ds_from_mA(arg);
484 break;
485 case PIN_CONFIG_INPUT_ENABLE:
486 mask |= JH7110_PADCFG_IE;
487 if (arg)
488 value |= JH7110_PADCFG_IE;
489 else
490 value &= ~JH7110_PADCFG_IE;
491 break;
492 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
493 mask |= JH7110_PADCFG_SMT;
494 if (arg)
495 value |= JH7110_PADCFG_SMT;
496 else
497 value &= ~JH7110_PADCFG_SMT;
498 break;
499 case PIN_CONFIG_SLEW_RATE:
500 mask |= JH7110_PADCFG_SLEW;
501 if (arg)
502 value |= JH7110_PADCFG_SLEW;
503 else
504 value &= ~JH7110_PADCFG_SLEW;
505 break;
506 default:
507 return -ENOTSUPP;
508 }
509 }
510
511 for (i = 0; i < group->num_pins; i++)
512 jh7110_padcfg_rmw(sfp, group->pins[i], mask, value);
513
514 return 0;
515 }
516
517 #ifdef CONFIG_DEBUG_FS
518 static void jh7110_pinconf_dbg_show(struct pinctrl_dev *pctldev,
519 struct seq_file *s, unsigned int pin)
520 {
521 struct jh7110_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
522 const struct jh7110_pinctrl_soc_info *info = sfp->info;
523 u32 value;
524 int padcfg_base;
525
526 if (!info->jh7110_get_padcfg_base)
527 return;
528
529 padcfg_base = info->jh7110_get_padcfg_base(sfp, pin);
530 if (padcfg_base < 0)
531 return;
532
533 value = readl_relaxed(sfp->base + padcfg_base + 4 * pin);
534 seq_printf(s, " (0x%02x)", value);
535 }
536 #else
537 #define jh7110_pinconf_dbg_show NULL
538 #endif
539
540 static const struct pinconf_ops jh7110_pinconf_ops = {
541 .pin_config_get = jh7110_pinconf_get,
542 .pin_config_group_get = jh7110_pinconf_group_get,
543 .pin_config_group_set = jh7110_pinconf_group_set,
544 .pin_config_dbg_show = jh7110_pinconf_dbg_show,
545 .is_generic = true,
546 };
547
548 static int jh7110_gpio_request(struct gpio_chip *gc, unsigned int gpio)
549 {
550 return pinctrl_gpio_request(gc->base + gpio);
551 }
552
553 static void jh7110_gpio_free(struct gpio_chip *gc, unsigned int gpio)
554 {
555 pinctrl_gpio_free(gc->base + gpio);
556 }
557
558 static int jh7110_gpio_get_direction(struct gpio_chip *gc,
559 unsigned int gpio)
560 {
561 struct jh7110_pinctrl *sfp = container_of(gc,
562 struct jh7110_pinctrl, gc);
563 const struct jh7110_pinctrl_soc_info *info = sfp->info;
564 unsigned int offset = 4 * (gpio / 4);
565 unsigned int shift = 8 * (gpio % 4);
566 u32 doen = readl_relaxed(sfp->base + info->doen_reg_base + offset);
567
568 doen = (doen >> shift) & info->doen_mask;
569
570 return doen == GPOEN_ENABLE ?
571 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
572 }
573
574 static int jh7110_gpio_direction_input(struct gpio_chip *gc,
575 unsigned int gpio)
576 {
577 struct jh7110_pinctrl *sfp = container_of(gc,
578 struct jh7110_pinctrl, gc);
579 const struct jh7110_pinctrl_soc_info *info = sfp->info;
580
581 /* enable input and schmitt trigger */
582 jh7110_padcfg_rmw(sfp, gpio,
583 JH7110_PADCFG_IE | JH7110_PADCFG_SMT,
584 JH7110_PADCFG_IE | JH7110_PADCFG_SMT);
585
586 if (info->jh7110_set_one_pin_mux)
587 info->jh7110_set_one_pin_mux(sfp, gpio,
588 GPI_NONE, GPOUT_LOW, GPOEN_DISABLE, 0);
589
590 return 0;
591 }
592
593 static int jh7110_gpio_direction_output(struct gpio_chip *gc,
594 unsigned int gpio, int value)
595 {
596 struct jh7110_pinctrl *sfp = container_of(gc,
597 struct jh7110_pinctrl, gc);
598 const struct jh7110_pinctrl_soc_info *info = sfp->info;
599
600 if (info->jh7110_set_one_pin_mux)
601 info->jh7110_set_one_pin_mux(sfp, gpio,
602 GPI_NONE, value ? GPOUT_HIGH : GPOUT_LOW,
603 GPOEN_ENABLE, 0);
604
605 /* disable input, schmitt trigger and bias */
606 jh7110_padcfg_rmw(sfp, gpio,
607 JH7110_PADCFG_IE | JH7110_PADCFG_SMT |
608 JH7110_PADCFG_BIAS, 0);
609 return 0;
610 }
611
612 static int jh7110_gpio_get(struct gpio_chip *gc, unsigned int gpio)
613 {
614 struct jh7110_pinctrl *sfp = container_of(gc,
615 struct jh7110_pinctrl, gc);
616 const struct jh7110_pinctrl_soc_info *info = sfp->info;
617 void __iomem *reg = sfp->base + info->gpioin_reg_base
618 + 4 * (gpio / 32);
619
620 return !!(readl_relaxed(reg) & BIT(gpio % 32));
621 }
622
623 static void jh7110_gpio_set(struct gpio_chip *gc,
624 unsigned int gpio, int value)
625 {
626 struct jh7110_pinctrl *sfp = container_of(gc,
627 struct jh7110_pinctrl, gc);
628 const struct jh7110_pinctrl_soc_info *info = sfp->info;
629 unsigned int offset = 4 * (gpio / 4);
630 unsigned int shift = 8 * (gpio % 4);
631 void __iomem *reg_dout = sfp->base + info->dout_reg_base + offset;
632 u32 dout = (value ? GPOUT_HIGH : GPOUT_LOW) << shift;
633 u32 mask = info->dout_mask << shift;
634 unsigned long flags;
635
636 raw_spin_lock_irqsave(&sfp->lock, flags);
637 dout |= readl_relaxed(reg_dout) & ~mask;
638 writel_relaxed(dout, reg_dout);
639 raw_spin_unlock_irqrestore(&sfp->lock, flags);
640 }
641
642 static int jh7110_gpio_set_config(struct gpio_chip *gc,
643 unsigned int gpio, unsigned long config)
644 {
645 struct jh7110_pinctrl *sfp = container_of(gc,
646 struct jh7110_pinctrl, gc);
647 u32 arg = pinconf_to_config_argument(config);
648 u32 value;
649 u32 mask;
650
651 switch (pinconf_to_config_param(config)) {
652 case PIN_CONFIG_BIAS_DISABLE:
653 mask = JH7110_PADCFG_BIAS;
654 value = 0;
655 break;
656 case PIN_CONFIG_BIAS_PULL_DOWN:
657 if (arg == 0)
658 return -ENOTSUPP;
659 mask = JH7110_PADCFG_BIAS;
660 value = JH7110_PADCFG_PD;
661 break;
662 case PIN_CONFIG_BIAS_PULL_UP:
663 if (arg == 0)
664 return -ENOTSUPP;
665 mask = JH7110_PADCFG_BIAS;
666 value = JH7110_PADCFG_PU;
667 break;
668 case PIN_CONFIG_DRIVE_PUSH_PULL:
669 return 0;
670 case PIN_CONFIG_INPUT_ENABLE:
671 mask = JH7110_PADCFG_IE;
672 value = arg ? JH7110_PADCFG_IE : 0;
673 break;
674 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
675 mask = JH7110_PADCFG_SMT;
676 value = arg ? JH7110_PADCFG_SMT : 0;
677 break;
678 default:
679 return -ENOTSUPP;
680 }
681
682 jh7110_padcfg_rmw(sfp, gpio, mask, value);
683 return 0;
684 }
685
686 static int jh7110_gpio_add_pin_ranges(struct gpio_chip *gc)
687 {
688 struct jh7110_pinctrl *sfp = container_of(gc,
689 struct jh7110_pinctrl, gc);
690
691 sfp->gpios.name = sfp->gc.label;
692 sfp->gpios.base = sfp->gc.base;
693 sfp->gpios.pin_base = 0;
694 sfp->gpios.npins = sfp->gc.ngpio;
695 sfp->gpios.gc = &sfp->gc;
696 pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
697 return 0;
698 }
699
700 static void jh7110_irq_ack(struct irq_data *d)
701 {
702 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
703 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
704 irq_hw_number_t gpio = irqd_to_hwirq(d);
705 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
706 + 4 * (gpio / 32);
707 u32 mask = BIT(gpio % 32);
708 unsigned long flags;
709 u32 value;
710
711 raw_spin_lock_irqsave(&sfp->lock, flags);
712 value = readl_relaxed(ic) & ~mask;
713 writel_relaxed(value, ic);
714 writel_relaxed(value | mask, ic);
715 raw_spin_unlock_irqrestore(&sfp->lock, flags);
716 }
717
718 static void jh7110_irq_mask(struct irq_data *d)
719 {
720 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
721 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
722 irq_hw_number_t gpio = irqd_to_hwirq(d);
723 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
724 + 4 * (gpio / 32);
725 u32 mask = BIT(gpio % 32);
726 unsigned long flags;
727 u32 value;
728
729 raw_spin_lock_irqsave(&sfp->lock, flags);
730 value = readl_relaxed(ie) & ~mask;
731 writel_relaxed(value, ie);
732 raw_spin_unlock_irqrestore(&sfp->lock, flags);
733
734 gpiochip_disable_irq(&sfp->gc, d->hwirq);
735 }
736
737 static void jh7110_irq_mask_ack(struct irq_data *d)
738 {
739 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
740 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
741 irq_hw_number_t gpio = irqd_to_hwirq(d);
742 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
743 + 4 * (gpio / 32);
744 void __iomem *ic = sfp->base + irq_reg->ic_reg_base
745 + 4 * (gpio / 32);
746 u32 mask = BIT(gpio % 32);
747 unsigned long flags;
748 u32 value;
749
750 raw_spin_lock_irqsave(&sfp->lock, flags);
751 value = readl_relaxed(ie) & ~mask;
752 writel_relaxed(value, ie);
753
754 value = readl_relaxed(ic) & ~mask;
755 writel_relaxed(value, ic);
756 writel_relaxed(value | mask, ic);
757 raw_spin_unlock_irqrestore(&sfp->lock, flags);
758 }
759
760 static void jh7110_irq_unmask(struct irq_data *d)
761 {
762 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
763 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
764 irq_hw_number_t gpio = irqd_to_hwirq(d);
765 void __iomem *ie = sfp->base + irq_reg->ie_reg_base
766 + 4 * (gpio / 32);
767 u32 mask = BIT(gpio % 32);
768 unsigned long flags;
769 u32 value;
770
771 gpiochip_enable_irq(&sfp->gc, d->hwirq);
772
773 raw_spin_lock_irqsave(&sfp->lock, flags);
774 value = readl_relaxed(ie) | mask;
775 writel_relaxed(value, ie);
776 raw_spin_unlock_irqrestore(&sfp->lock, flags);
777 }
778
779 static int jh7110_irq_set_type(struct irq_data *d, unsigned int trigger)
780 {
781 struct jh7110_pinctrl *sfp = jh7110_from_irq_data(d);
782 const struct jh7110_gpio_irq_reg *irq_reg = sfp->info->irq_reg;
783 irq_hw_number_t gpio = irqd_to_hwirq(d);
784 void __iomem *base = sfp->base + 4 * (gpio / 32);
785 u32 mask = BIT(gpio % 32);
786 u32 irq_type, edge_both, polarity;
787 unsigned long flags;
788
789 switch (trigger) {
790 case IRQ_TYPE_EDGE_RISING:
791 irq_type = mask; /* 1: edge triggered */
792 edge_both = 0; /* 0: single edge */
793 polarity = mask; /* 1: rising edge */
794 break;
795 case IRQ_TYPE_EDGE_FALLING:
796 irq_type = mask; /* 1: edge triggered */
797 edge_both = 0; /* 0: single edge */
798 polarity = 0; /* 0: falling edge */
799 break;
800 case IRQ_TYPE_EDGE_BOTH:
801 irq_type = mask; /* 1: edge triggered */
802 edge_both = mask; /* 1: both edges */
803 polarity = 0; /* 0: ignored */
804 break;
805 case IRQ_TYPE_LEVEL_HIGH:
806 irq_type = 0; /* 0: level triggered */
807 edge_both = 0; /* 0: ignored */
808 polarity = mask; /* 1: high level */
809 break;
810 case IRQ_TYPE_LEVEL_LOW:
811 irq_type = 0; /* 0: level triggered */
812 edge_both = 0; /* 0: ignored */
813 polarity = 0; /* 0: low level */
814 break;
815 default:
816 return -EINVAL;
817 }
818
819 if (trigger & IRQ_TYPE_EDGE_BOTH)
820 irq_set_handler_locked(d, handle_edge_irq);
821 else
822 irq_set_handler_locked(d, handle_level_irq);
823
824 raw_spin_lock_irqsave(&sfp->lock, flags);
825 irq_type |= readl_relaxed(base + irq_reg->is_reg_base) & ~mask;
826 writel_relaxed(irq_type, base + irq_reg->is_reg_base);
827
828 edge_both |= readl_relaxed(base + irq_reg->ibe_reg_base) & ~mask;
829 writel_relaxed(edge_both, base + irq_reg->ibe_reg_base);
830
831 polarity |= readl_relaxed(base + irq_reg->iev_reg_base) & ~mask;
832 writel_relaxed(polarity, base + irq_reg->iev_reg_base);
833 raw_spin_unlock_irqrestore(&sfp->lock, flags);
834 return 0;
835 }
836
837 static struct irq_chip jh7110_irq_chip = {
838 .irq_ack = jh7110_irq_ack,
839 .irq_mask = jh7110_irq_mask,
840 .irq_mask_ack = jh7110_irq_mask_ack,
841 .irq_unmask = jh7110_irq_unmask,
842 .irq_set_type = jh7110_irq_set_type,
843 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
844 GPIOCHIP_IRQ_RESOURCE_HELPERS,
845 };
846
847 static void jh7110_disable_clock(void *data)
848 {
849 clk_disable_unprepare(data);
850 }
851
852 int jh7110_pinctrl_probe(struct platform_device *pdev)
853 {
854 struct device *dev = &pdev->dev;
855 const struct jh7110_pinctrl_soc_info *info;
856 struct jh7110_pinctrl *sfp;
857 struct pinctrl_desc *jh7110_pinctrl_desc;
858 struct reset_control *rst;
859 struct clk *clk;
860 int ret;
861
862 info = of_device_get_match_data(&pdev->dev);
863 if (!info)
864 return -ENODEV;
865
866 if (!info->pins || !info->npins) {
867 dev_err(dev, "wrong pinctrl info\n");
868 return -EINVAL;
869 }
870
871 sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
872 if (!sfp)
873 return -ENOMEM;
874
875 #if IS_ENABLED(CONFIG_PM_SLEEP)
876 sfp->saved_regs = devm_kcalloc(dev, info->nsaved_regs,
877 sizeof(*sfp->saved_regs), GFP_KERNEL);
878 if (!sfp->saved_regs)
879 return -ENOMEM;
880 #endif
881
882 sfp->base = devm_platform_ioremap_resource(pdev, 0);
883 if (IS_ERR(sfp->base))
884 return PTR_ERR(sfp->base);
885
886 clk = devm_clk_get_optional(dev, NULL);
887 if (IS_ERR(clk))
888 return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
889
890 rst = devm_reset_control_get_exclusive(dev, NULL);
891 if (IS_ERR(rst))
892 return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
893
894 /*
895 * we don't want to assert reset and risk undoing pin muxing for the
896 * early boot serial console, but let's make sure the reset line is
897 * deasserted in case someone runs a really minimal bootloader.
898 */
899 ret = reset_control_deassert(rst);
900 if (ret)
901 return dev_err_probe(dev, ret, "could not deassert reset\n");
902
903 if (clk) {
904 ret = clk_prepare_enable(clk);
905 if (ret)
906 return dev_err_probe(dev, ret, "could not enable clock\n");
907
908 ret = devm_add_action_or_reset(dev, jh7110_disable_clock, clk);
909 if (ret)
910 return ret;
911 }
912
913 jh7110_pinctrl_desc = devm_kzalloc(&pdev->dev,
914 sizeof(*jh7110_pinctrl_desc),
915 GFP_KERNEL);
916 if (!jh7110_pinctrl_desc)
917 return -ENOMEM;
918
919 jh7110_pinctrl_desc->name = dev_name(dev);
920 jh7110_pinctrl_desc->pins = info->pins;
921 jh7110_pinctrl_desc->npins = info->npins;
922 jh7110_pinctrl_desc->pctlops = &jh7110_pinctrl_ops;
923 jh7110_pinctrl_desc->pmxops = &jh7110_pinmux_ops;
924 jh7110_pinctrl_desc->confops = &jh7110_pinconf_ops;
925 jh7110_pinctrl_desc->owner = THIS_MODULE;
926
927 sfp->info = info;
928 sfp->dev = dev;
929 platform_set_drvdata(pdev, sfp);
930 sfp->gc.parent = dev;
931 raw_spin_lock_init(&sfp->lock);
932 mutex_init(&sfp->mutex);
933
934 ret = devm_pinctrl_register_and_init(dev,
935 jh7110_pinctrl_desc,
936 sfp, &sfp->pctl);
937 if (ret)
938 return dev_err_probe(dev, ret,
939 "could not register pinctrl driver\n");
940
941 sfp->gc.label = dev_name(dev);
942 sfp->gc.owner = THIS_MODULE;
943 sfp->gc.request = jh7110_gpio_request;
944 sfp->gc.free = jh7110_gpio_free;
945 sfp->gc.get_direction = jh7110_gpio_get_direction;
946 sfp->gc.direction_input = jh7110_gpio_direction_input;
947 sfp->gc.direction_output = jh7110_gpio_direction_output;
948 sfp->gc.get = jh7110_gpio_get;
949 sfp->gc.set = jh7110_gpio_set;
950 sfp->gc.set_config = jh7110_gpio_set_config;
951 sfp->gc.add_pin_ranges = jh7110_gpio_add_pin_ranges;
952 sfp->gc.base = info->gc_base;
953 sfp->gc.ngpio = info->ngpios;
954
955 jh7110_irq_chip.name = sfp->gc.label;
956 gpio_irq_chip_set_chip(&sfp->gc.irq, &jh7110_irq_chip);
957 sfp->gc.irq.parent_handler = info->jh7110_gpio_irq_handler;
958 sfp->gc.irq.num_parents = 1;
959 sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
960 sizeof(*sfp->gc.irq.parents),
961 GFP_KERNEL);
962 if (!sfp->gc.irq.parents)
963 return -ENOMEM;
964 sfp->gc.irq.default_type = IRQ_TYPE_NONE;
965 sfp->gc.irq.handler = handle_bad_irq;
966 sfp->gc.irq.init_hw = info->jh7110_gpio_init_hw;
967
968 ret = platform_get_irq(pdev, 0);
969 if (ret < 0)
970 return ret;
971 sfp->gc.irq.parents[0] = ret;
972
973 ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
974 if (ret)
975 return dev_err_probe(dev, ret, "could not register gpiochip\n");
976
977 dev_info(dev, "StarFive GPIO chip registered %d GPIOs\n", sfp->gc.ngpio);
978
979 return pinctrl_enable(sfp->pctl);
980 }
981 EXPORT_SYMBOL_GPL(jh7110_pinctrl_probe);
982
983 static int jh7110_pinctrl_suspend(struct device *dev)
984 {
985 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
986 unsigned long flags;
987 unsigned int i;
988
989 raw_spin_lock_irqsave(&sfp->lock, flags);
990 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
991 sfp->saved_regs[i] = readl_relaxed(sfp->base + 4 * i);
992
993 raw_spin_unlock_irqrestore(&sfp->lock, flags);
994 return 0;
995 }
996
997 static int jh7110_pinctrl_resume(struct device *dev)
998 {
999 struct jh7110_pinctrl *sfp = dev_get_drvdata(dev);
1000 unsigned long flags;
1001 unsigned int i;
1002
1003 raw_spin_lock_irqsave(&sfp->lock, flags);
1004 for (i = 0 ; i < sfp->info->nsaved_regs ; i++)
1005 writel_relaxed(sfp->saved_regs[i], sfp->base + 4 * i);
1006
1007 raw_spin_unlock_irqrestore(&sfp->lock, flags);
1008 return 0;
1009 }
1010
1011 const struct dev_pm_ops jh7110_pinctrl_pm_ops = {
1012 LATE_SYSTEM_SLEEP_PM_OPS(jh7110_pinctrl_suspend, jh7110_pinctrl_resume)
1013 };
1014 EXPORT_SYMBOL_GPL(jh7110_pinctrl_pm_ops);
1015
1016 MODULE_DESCRIPTION("Pinctrl driver for the StarFive JH7110 SoC");
1017 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1018 MODULE_AUTHOR("Jianlong Huang <jianlong.huang@starfivetech.com>");
1019 MODULE_LICENSE("GPL");
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git