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Merge tag 'hyperv-fixes-signed-20240411' of git://git.kernel.org/pub/scm/linux/kernel...
[thirdparty/linux.git] / drivers / ptp / ptp_ocp.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
83
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
86
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
89
90 struct tod_reg {
91 u32 ctrl;
92 u32 status;
93 u32 uart_polarity;
94 u32 version;
95 u32 adj_sec;
96 u32 __pad0[3];
97 u32 uart_baud;
98 u32 __pad1[3];
99 u32 utc_status;
100 u32 leap;
101 };
102
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
109
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
114
115 struct ts_reg {
116 u32 enable;
117 u32 error;
118 u32 polarity;
119 u32 version;
120 u32 __pad0[4];
121 u32 cable_delay;
122 u32 __pad1[3];
123 u32 intr;
124 u32 intr_mask;
125 u32 event_count;
126 u32 __pad2[1];
127 u32 ts_count;
128 u32 time_ns;
129 u32 time_sec;
130 u32 data_width;
131 u32 data;
132 };
133
134 struct pps_reg {
135 u32 ctrl;
136 u32 status;
137 u32 __pad0[6];
138 u32 cable_delay;
139 };
140
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
143
144 struct img_reg {
145 u32 version;
146 };
147
148 struct gpio_reg {
149 u32 gpio1;
150 u32 __pad0;
151 u32 gpio2;
152 u32 __pad1;
153 };
154
155 struct irig_master_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_M_CTRL_ENABLE BIT(0)
165
166 struct irig_slave_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 u32 mode_ctrl;
173 };
174
175 #define IRIG_S_CTRL_ENABLE BIT(0)
176
177 struct dcf_master_reg {
178 u32 ctrl;
179 u32 status;
180 u32 __pad0;
181 u32 version;
182 u32 adj_sec;
183 };
184
185 #define DCF_M_CTRL_ENABLE BIT(0)
186
187 struct dcf_slave_reg {
188 u32 ctrl;
189 u32 status;
190 u32 __pad0;
191 u32 version;
192 u32 adj_sec;
193 };
194
195 #define DCF_S_CTRL_ENABLE BIT(0)
196
197 struct signal_reg {
198 u32 enable;
199 u32 status;
200 u32 polarity;
201 u32 version;
202 u32 __pad0[4];
203 u32 cable_delay;
204 u32 __pad1[3];
205 u32 intr;
206 u32 intr_mask;
207 u32 __pad2[2];
208 u32 start_ns;
209 u32 start_sec;
210 u32 pulse_ns;
211 u32 pulse_sec;
212 u32 period_ns;
213 u32 period_sec;
214 u32 repeat_count;
215 };
216
217 struct frequency_reg {
218 u32 ctrl;
219 u32 status;
220 };
221
222 struct board_config_reg {
223 u32 mro50_serial_activate;
224 };
225
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
230
231 struct ptp_ocp_flash_info {
232 const char *name;
233 int pci_offset;
234 int data_size;
235 void *data;
236 };
237
238 struct ptp_ocp_firmware_header {
239 char magic[4];
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
242 __be32 image_size;
243 __be16 hw_revision;
244 __be16 crc;
245 };
246
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
248
249 struct ptp_ocp_i2c_info {
250 const char *name;
251 unsigned long fixed_rate;
252 size_t data_size;
253 void *data;
254 };
255
256 struct ptp_ocp_ext_info {
257 int index;
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
260 };
261
262 struct ptp_ocp_ext_src {
263 void __iomem *mem;
264 struct ptp_ocp *bp;
265 struct ptp_ocp_ext_info *info;
266 int irq_vec;
267 };
268
269 enum ptp_ocp_sma_mode {
270 SMA_MODE_IN,
271 SMA_MODE_OUT,
272 };
273
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
279 };
280
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
283 bool fixed_fcn;
284 bool fixed_dir;
285 bool disabled;
286 u8 default_fcn;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318
319 struct ptp_ocp {
320 struct pci_dev *pdev;
321 struct device dev;
322 spinlock_t lock;
323 struct ocp_reg __iomem *reg;
324 struct tod_reg __iomem *tod;
325 struct pps_reg __iomem *pps_to_ext;
326 struct pps_reg __iomem *pps_to_clk;
327 struct board_config_reg __iomem *board_config;
328 struct gpio_reg __iomem *pps_select;
329 struct gpio_reg __iomem *sma_map1;
330 struct gpio_reg __iomem *sma_map2;
331 struct irig_master_reg __iomem *irig_out;
332 struct irig_slave_reg __iomem *irig_in;
333 struct dcf_master_reg __iomem *dcf_out;
334 struct dcf_slave_reg __iomem *dcf_in;
335 struct tod_reg __iomem *nmea_out;
336 struct frequency_reg __iomem *freq_in[4];
337 struct ptp_ocp_ext_src *signal_out[4];
338 struct ptp_ocp_ext_src *pps;
339 struct ptp_ocp_ext_src *ts0;
340 struct ptp_ocp_ext_src *ts1;
341 struct ptp_ocp_ext_src *ts2;
342 struct ptp_ocp_ext_src *ts3;
343 struct ptp_ocp_ext_src *ts4;
344 struct ocp_art_gpio_reg __iomem *art_sma;
345 struct img_reg __iomem *image;
346 struct ptp_clock *ptp;
347 struct ptp_clock_info ptp_info;
348 struct platform_device *i2c_ctrl;
349 struct platform_device *spi_flash;
350 struct clk_hw *i2c_clk;
351 struct timer_list watchdog;
352 const struct attribute_group **attr_group;
353 const struct ptp_ocp_eeprom_map *eeprom_map;
354 struct dentry *debug_root;
355 bool sync;
356 time64_t gnss_lost;
357 struct delayed_work sync_work;
358 int id;
359 int n_irqs;
360 struct ptp_ocp_serial_port gnss_port;
361 struct ptp_ocp_serial_port gnss2_port;
362 struct ptp_ocp_serial_port mac_port; /* miniature atomic clock */
363 struct ptp_ocp_serial_port nmea_port;
364 bool fw_loader;
365 u8 fw_tag;
366 u16 fw_version;
367 u8 board_id[OCP_BOARD_ID_LEN];
368 u8 serial[OCP_SERIAL_LEN];
369 bool has_eeprom_data;
370 u32 pps_req_map;
371 int flash_start;
372 u32 utc_tai_offset;
373 u32 ts_window_adjust;
374 u64 fw_cap;
375 struct ptp_ocp_signal signal[4];
376 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
377 const struct ocp_sma_op *sma_op;
378 struct dpll_device *dpll;
379 };
380
381 #define OCP_REQ_TIMESTAMP BIT(0)
382 #define OCP_REQ_PPS BIT(1)
383
384 struct ocp_resource {
385 unsigned long offset;
386 int size;
387 int irq_vec;
388 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
389 void *extra;
390 unsigned long bp_offset;
391 const char * const name;
392 };
393
394 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
395 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
396 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
397 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
398 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
399 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
400 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
401 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
402 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
403 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
404 struct ptp_perout_request *req);
405 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
406 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
407
408 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
409
410 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
411
412 static const struct ocp_attr_group fb_timecard_groups[];
413
414 static const struct ocp_attr_group art_timecard_groups[];
415
416 static const struct ocp_attr_group adva_timecard_groups[];
417
418 struct ptp_ocp_eeprom_map {
419 u16 off;
420 u16 len;
421 u32 bp_offset;
422 const void * const tag;
423 };
424
425 #define EEPROM_ENTRY(addr, member) \
426 .off = addr, \
427 .len = sizeof_field(struct ptp_ocp, member), \
428 .bp_offset = offsetof(struct ptp_ocp, member)
429
430 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
431 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
432 })
433
434 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
435 { EEPROM_ENTRY(0x43, board_id) },
436 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
437 { }
438 };
439
440 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
441 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
442 { EEPROM_ENTRY(0x200 + 0x63, serial) },
443 { }
444 };
445
446 #define bp_assign_entry(bp, res, val) ({ \
447 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
448 *(typeof(val) *)addr = val; \
449 })
450
451 #define OCP_RES_LOCATION(member) \
452 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
453
454 #define OCP_MEM_RESOURCE(member) \
455 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
456
457 #define OCP_SERIAL_RESOURCE(member) \
458 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
459
460 #define OCP_I2C_RESOURCE(member) \
461 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
462
463 #define OCP_SPI_RESOURCE(member) \
464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
465
466 #define OCP_EXT_RESOURCE(member) \
467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
468
469 /* This is the MSI vector mapping used.
470 * 0: PPS (TS5)
471 * 1: TS0
472 * 2: TS1
473 * 3: GNSS1
474 * 4: GNSS2
475 * 5: MAC
476 * 6: TS2
477 * 7: I2C controller
478 * 8: HWICAP (notused)
479 * 9: SPI Flash
480 * 10: NMEA
481 * 11: Signal Generator 1
482 * 12: Signal Generator 2
483 * 13: Signal Generator 3
484 * 14: Signal Generator 4
485 * 15: TS3
486 * 16: TS4
487 --
488 * 8: Orolia TS1
489 * 10: Orolia TS2
490 * 11: Orolia TS0 (GNSS)
491 * 12: Orolia PPS
492 * 14: Orolia TS3
493 * 15: Orolia TS4
494 */
495
496 static struct ocp_resource ocp_fb_resource[] = {
497 {
498 OCP_MEM_RESOURCE(reg),
499 .offset = 0x01000000, .size = 0x10000,
500 },
501 {
502 OCP_EXT_RESOURCE(ts0),
503 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
504 .extra = &(struct ptp_ocp_ext_info) {
505 .index = 0,
506 .irq_fcn = ptp_ocp_ts_irq,
507 .enable = ptp_ocp_ts_enable,
508 },
509 },
510 {
511 OCP_EXT_RESOURCE(ts1),
512 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
513 .extra = &(struct ptp_ocp_ext_info) {
514 .index = 1,
515 .irq_fcn = ptp_ocp_ts_irq,
516 .enable = ptp_ocp_ts_enable,
517 },
518 },
519 {
520 OCP_EXT_RESOURCE(ts2),
521 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
522 .extra = &(struct ptp_ocp_ext_info) {
523 .index = 2,
524 .irq_fcn = ptp_ocp_ts_irq,
525 .enable = ptp_ocp_ts_enable,
526 },
527 },
528 {
529 OCP_EXT_RESOURCE(ts3),
530 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
531 .extra = &(struct ptp_ocp_ext_info) {
532 .index = 3,
533 .irq_fcn = ptp_ocp_ts_irq,
534 .enable = ptp_ocp_ts_enable,
535 },
536 },
537 {
538 OCP_EXT_RESOURCE(ts4),
539 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
540 .extra = &(struct ptp_ocp_ext_info) {
541 .index = 4,
542 .irq_fcn = ptp_ocp_ts_irq,
543 .enable = ptp_ocp_ts_enable,
544 },
545 },
546 /* Timestamp for PHC and/or PPS generator */
547 {
548 OCP_EXT_RESOURCE(pps),
549 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
550 .extra = &(struct ptp_ocp_ext_info) {
551 .index = 5,
552 .irq_fcn = ptp_ocp_ts_irq,
553 .enable = ptp_ocp_ts_enable,
554 },
555 },
556 {
557 OCP_EXT_RESOURCE(signal_out[0]),
558 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
559 .extra = &(struct ptp_ocp_ext_info) {
560 .index = 1,
561 .irq_fcn = ptp_ocp_signal_irq,
562 .enable = ptp_ocp_signal_enable,
563 },
564 },
565 {
566 OCP_EXT_RESOURCE(signal_out[1]),
567 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
568 .extra = &(struct ptp_ocp_ext_info) {
569 .index = 2,
570 .irq_fcn = ptp_ocp_signal_irq,
571 .enable = ptp_ocp_signal_enable,
572 },
573 },
574 {
575 OCP_EXT_RESOURCE(signal_out[2]),
576 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
577 .extra = &(struct ptp_ocp_ext_info) {
578 .index = 3,
579 .irq_fcn = ptp_ocp_signal_irq,
580 .enable = ptp_ocp_signal_enable,
581 },
582 },
583 {
584 OCP_EXT_RESOURCE(signal_out[3]),
585 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
586 .extra = &(struct ptp_ocp_ext_info) {
587 .index = 4,
588 .irq_fcn = ptp_ocp_signal_irq,
589 .enable = ptp_ocp_signal_enable,
590 },
591 },
592 {
593 OCP_MEM_RESOURCE(pps_to_ext),
594 .offset = 0x01030000, .size = 0x10000,
595 },
596 {
597 OCP_MEM_RESOURCE(pps_to_clk),
598 .offset = 0x01040000, .size = 0x10000,
599 },
600 {
601 OCP_MEM_RESOURCE(tod),
602 .offset = 0x01050000, .size = 0x10000,
603 },
604 {
605 OCP_MEM_RESOURCE(irig_in),
606 .offset = 0x01070000, .size = 0x10000,
607 },
608 {
609 OCP_MEM_RESOURCE(irig_out),
610 .offset = 0x01080000, .size = 0x10000,
611 },
612 {
613 OCP_MEM_RESOURCE(dcf_in),
614 .offset = 0x01090000, .size = 0x10000,
615 },
616 {
617 OCP_MEM_RESOURCE(dcf_out),
618 .offset = 0x010A0000, .size = 0x10000,
619 },
620 {
621 OCP_MEM_RESOURCE(nmea_out),
622 .offset = 0x010B0000, .size = 0x10000,
623 },
624 {
625 OCP_MEM_RESOURCE(image),
626 .offset = 0x00020000, .size = 0x1000,
627 },
628 {
629 OCP_MEM_RESOURCE(pps_select),
630 .offset = 0x00130000, .size = 0x1000,
631 },
632 {
633 OCP_MEM_RESOURCE(sma_map1),
634 .offset = 0x00140000, .size = 0x1000,
635 },
636 {
637 OCP_MEM_RESOURCE(sma_map2),
638 .offset = 0x00220000, .size = 0x1000,
639 },
640 {
641 OCP_I2C_RESOURCE(i2c_ctrl),
642 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
643 .extra = &(struct ptp_ocp_i2c_info) {
644 .name = "xiic-i2c",
645 .fixed_rate = 50000000,
646 .data_size = sizeof(struct xiic_i2c_platform_data),
647 .data = &(struct xiic_i2c_platform_data) {
648 .num_devices = 2,
649 .devices = (struct i2c_board_info[]) {
650 { I2C_BOARD_INFO("24c02", 0x50) },
651 { I2C_BOARD_INFO("24mac402", 0x58),
652 .platform_data = "mac" },
653 },
654 },
655 },
656 },
657 {
658 OCP_SERIAL_RESOURCE(gnss_port),
659 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
660 .extra = &(struct ptp_ocp_serial_port) {
661 .baud = 115200,
662 },
663 },
664 {
665 OCP_SERIAL_RESOURCE(gnss2_port),
666 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
667 .extra = &(struct ptp_ocp_serial_port) {
668 .baud = 115200,
669 },
670 },
671 {
672 OCP_SERIAL_RESOURCE(mac_port),
673 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
674 .extra = &(struct ptp_ocp_serial_port) {
675 .baud = 57600,
676 },
677 },
678 {
679 OCP_SERIAL_RESOURCE(nmea_port),
680 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
681 },
682 {
683 OCP_SPI_RESOURCE(spi_flash),
684 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
685 .extra = &(struct ptp_ocp_flash_info) {
686 .name = "xilinx_spi", .pci_offset = 0,
687 .data_size = sizeof(struct xspi_platform_data),
688 .data = &(struct xspi_platform_data) {
689 .num_chipselect = 1,
690 .bits_per_word = 8,
691 .num_devices = 1,
692 .force_irq = true,
693 .devices = &(struct spi_board_info) {
694 .modalias = "spi-nor",
695 },
696 },
697 },
698 },
699 {
700 OCP_MEM_RESOURCE(freq_in[0]),
701 .offset = 0x01200000, .size = 0x10000,
702 },
703 {
704 OCP_MEM_RESOURCE(freq_in[1]),
705 .offset = 0x01210000, .size = 0x10000,
706 },
707 {
708 OCP_MEM_RESOURCE(freq_in[2]),
709 .offset = 0x01220000, .size = 0x10000,
710 },
711 {
712 OCP_MEM_RESOURCE(freq_in[3]),
713 .offset = 0x01230000, .size = 0x10000,
714 },
715 {
716 .setup = ptp_ocp_fb_board_init,
717 .extra = &(struct ptp_ocp_servo_conf) {
718 .servo_offset_p = 0x2000,
719 .servo_offset_i = 0x1000,
720 .servo_drift_p = 0,
721 .servo_drift_i = 0,
722 },
723 },
724 { }
725 };
726
727 #define OCP_ART_CONFIG_SIZE 144
728 #define OCP_ART_TEMP_TABLE_SIZE 368
729
730 struct ocp_art_gpio_reg {
731 struct {
732 u32 gpio;
733 u32 __pad[3];
734 } map[4];
735 };
736
737 static struct ocp_resource ocp_art_resource[] = {
738 {
739 OCP_MEM_RESOURCE(reg),
740 .offset = 0x01000000, .size = 0x10000,
741 },
742 {
743 OCP_SERIAL_RESOURCE(gnss_port),
744 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
745 .extra = &(struct ptp_ocp_serial_port) {
746 .baud = 115200,
747 },
748 },
749 {
750 OCP_MEM_RESOURCE(art_sma),
751 .offset = 0x003C0000, .size = 0x1000,
752 },
753 /* Timestamp associated with GNSS1 receiver PPS */
754 {
755 OCP_EXT_RESOURCE(ts0),
756 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
757 .extra = &(struct ptp_ocp_ext_info) {
758 .index = 0,
759 .irq_fcn = ptp_ocp_ts_irq,
760 .enable = ptp_ocp_ts_enable,
761 },
762 },
763 {
764 OCP_EXT_RESOURCE(ts1),
765 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
766 .extra = &(struct ptp_ocp_ext_info) {
767 .index = 1,
768 .irq_fcn = ptp_ocp_ts_irq,
769 .enable = ptp_ocp_ts_enable,
770 },
771 },
772 {
773 OCP_EXT_RESOURCE(ts2),
774 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
775 .extra = &(struct ptp_ocp_ext_info) {
776 .index = 2,
777 .irq_fcn = ptp_ocp_ts_irq,
778 .enable = ptp_ocp_ts_enable,
779 },
780 },
781 {
782 OCP_EXT_RESOURCE(ts3),
783 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
784 .extra = &(struct ptp_ocp_ext_info) {
785 .index = 3,
786 .irq_fcn = ptp_ocp_ts_irq,
787 .enable = ptp_ocp_ts_enable,
788 },
789 },
790 {
791 OCP_EXT_RESOURCE(ts4),
792 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
793 .extra = &(struct ptp_ocp_ext_info) {
794 .index = 4,
795 .irq_fcn = ptp_ocp_ts_irq,
796 .enable = ptp_ocp_ts_enable,
797 },
798 },
799 /* Timestamp associated with Internal PPS of the card */
800 {
801 OCP_EXT_RESOURCE(pps),
802 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
803 .extra = &(struct ptp_ocp_ext_info) {
804 .index = 5,
805 .irq_fcn = ptp_ocp_ts_irq,
806 .enable = ptp_ocp_ts_enable,
807 },
808 },
809 {
810 OCP_SPI_RESOURCE(spi_flash),
811 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
812 .extra = &(struct ptp_ocp_flash_info) {
813 .name = "spi_altera", .pci_offset = 0,
814 .data_size = sizeof(struct altera_spi_platform_data),
815 .data = &(struct altera_spi_platform_data) {
816 .num_chipselect = 1,
817 .num_devices = 1,
818 .devices = &(struct spi_board_info) {
819 .modalias = "spi-nor",
820 },
821 },
822 },
823 },
824 {
825 OCP_I2C_RESOURCE(i2c_ctrl),
826 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
827 .extra = &(struct ptp_ocp_i2c_info) {
828 .name = "ocores-i2c",
829 .fixed_rate = 400000,
830 .data_size = sizeof(struct ocores_i2c_platform_data),
831 .data = &(struct ocores_i2c_platform_data) {
832 .clock_khz = 125000,
833 .bus_khz = 400,
834 .num_devices = 1,
835 .devices = &(struct i2c_board_info) {
836 I2C_BOARD_INFO("24c08", 0x50),
837 },
838 },
839 },
840 },
841 {
842 OCP_SERIAL_RESOURCE(mac_port),
843 .offset = 0x00190000, .irq_vec = 7,
844 .extra = &(struct ptp_ocp_serial_port) {
845 .baud = 9600,
846 },
847 },
848 {
849 OCP_MEM_RESOURCE(board_config),
850 .offset = 0x210000, .size = 0x1000,
851 },
852 {
853 .setup = ptp_ocp_art_board_init,
854 .extra = &(struct ptp_ocp_servo_conf) {
855 .servo_offset_p = 0x2000,
856 .servo_offset_i = 0x1000,
857 .servo_drift_p = 0,
858 .servo_drift_i = 0,
859 },
860 },
861 { }
862 };
863
864 static struct ocp_resource ocp_adva_resource[] = {
865 {
866 OCP_MEM_RESOURCE(reg),
867 .offset = 0x01000000, .size = 0x10000,
868 },
869 {
870 OCP_EXT_RESOURCE(ts0),
871 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
872 .extra = &(struct ptp_ocp_ext_info) {
873 .index = 0,
874 .irq_fcn = ptp_ocp_ts_irq,
875 .enable = ptp_ocp_ts_enable,
876 },
877 },
878 {
879 OCP_EXT_RESOURCE(ts1),
880 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
881 .extra = &(struct ptp_ocp_ext_info) {
882 .index = 1,
883 .irq_fcn = ptp_ocp_ts_irq,
884 .enable = ptp_ocp_ts_enable,
885 },
886 },
887 {
888 OCP_EXT_RESOURCE(ts2),
889 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
890 .extra = &(struct ptp_ocp_ext_info) {
891 .index = 2,
892 .irq_fcn = ptp_ocp_ts_irq,
893 .enable = ptp_ocp_ts_enable,
894 },
895 },
896 /* Timestamp for PHC and/or PPS generator */
897 {
898 OCP_EXT_RESOURCE(pps),
899 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
900 .extra = &(struct ptp_ocp_ext_info) {
901 .index = 5,
902 .irq_fcn = ptp_ocp_ts_irq,
903 .enable = ptp_ocp_ts_enable,
904 },
905 },
906 {
907 OCP_EXT_RESOURCE(signal_out[0]),
908 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
909 .extra = &(struct ptp_ocp_ext_info) {
910 .index = 1,
911 .irq_fcn = ptp_ocp_signal_irq,
912 .enable = ptp_ocp_signal_enable,
913 },
914 },
915 {
916 OCP_EXT_RESOURCE(signal_out[1]),
917 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
918 .extra = &(struct ptp_ocp_ext_info) {
919 .index = 2,
920 .irq_fcn = ptp_ocp_signal_irq,
921 .enable = ptp_ocp_signal_enable,
922 },
923 },
924 {
925 OCP_MEM_RESOURCE(pps_to_ext),
926 .offset = 0x01030000, .size = 0x10000,
927 },
928 {
929 OCP_MEM_RESOURCE(pps_to_clk),
930 .offset = 0x01040000, .size = 0x10000,
931 },
932 {
933 OCP_MEM_RESOURCE(tod),
934 .offset = 0x01050000, .size = 0x10000,
935 },
936 {
937 OCP_MEM_RESOURCE(image),
938 .offset = 0x00020000, .size = 0x1000,
939 },
940 {
941 OCP_MEM_RESOURCE(pps_select),
942 .offset = 0x00130000, .size = 0x1000,
943 },
944 {
945 OCP_MEM_RESOURCE(sma_map1),
946 .offset = 0x00140000, .size = 0x1000,
947 },
948 {
949 OCP_MEM_RESOURCE(sma_map2),
950 .offset = 0x00220000, .size = 0x1000,
951 },
952 {
953 OCP_SERIAL_RESOURCE(gnss_port),
954 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
955 .extra = &(struct ptp_ocp_serial_port) {
956 .baud = 9600,
957 },
958 },
959 {
960 OCP_SERIAL_RESOURCE(mac_port),
961 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
962 .extra = &(struct ptp_ocp_serial_port) {
963 .baud = 115200,
964 },
965 },
966 {
967 OCP_MEM_RESOURCE(freq_in[0]),
968 .offset = 0x01200000, .size = 0x10000,
969 },
970 {
971 OCP_MEM_RESOURCE(freq_in[1]),
972 .offset = 0x01210000, .size = 0x10000,
973 },
974 {
975 OCP_SPI_RESOURCE(spi_flash),
976 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
977 .extra = &(struct ptp_ocp_flash_info) {
978 .name = "spi_altera", .pci_offset = 0,
979 .data_size = sizeof(struct altera_spi_platform_data),
980 .data = &(struct altera_spi_platform_data) {
981 .num_chipselect = 1,
982 .num_devices = 1,
983 .devices = &(struct spi_board_info) {
984 .modalias = "spi-nor",
985 },
986 },
987 },
988 },
989 {
990 OCP_I2C_RESOURCE(i2c_ctrl),
991 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
992 .extra = &(struct ptp_ocp_i2c_info) {
993 .name = "ocores-i2c",
994 .fixed_rate = 50000000,
995 .data_size = sizeof(struct ocores_i2c_platform_data),
996 .data = &(struct ocores_i2c_platform_data) {
997 .clock_khz = 50000,
998 .bus_khz = 100,
999 .reg_io_width = 4, // 32-bit/4-byte
1000 .reg_shift = 2, // 32-bit addressing
1001 .num_devices = 2,
1002 .devices = (struct i2c_board_info[]) {
1003 { I2C_BOARD_INFO("24c02", 0x50) },
1004 { I2C_BOARD_INFO("24mac402", 0x58),
1005 .platform_data = "mac" },
1006 },
1007 },
1008 },
1009 },
1010 {
1011 .setup = ptp_ocp_adva_board_init,
1012 .extra = &(struct ptp_ocp_servo_conf) {
1013 .servo_offset_p = 0xc000,
1014 .servo_offset_i = 0x1000,
1015 .servo_drift_p = 0,
1016 .servo_drift_i = 0,
1017 },
1018 },
1019 { }
1020 };
1021
1022 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1023 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1024 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1025 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1026 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1027 { }
1028 };
1029 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1030
1031 static DEFINE_MUTEX(ptp_ocp_lock);
1032 static DEFINE_IDR(ptp_ocp_idr);
1033
1034 struct ocp_selector {
1035 const char *name;
1036 int value;
1037 u64 frequency;
1038 };
1039
1040 static const struct ocp_selector ptp_ocp_clock[] = {
1041 { .name = "NONE", .value = 0 },
1042 { .name = "TOD", .value = 1 },
1043 { .name = "IRIG", .value = 2 },
1044 { .name = "PPS", .value = 3 },
1045 { .name = "PTP", .value = 4 },
1046 { .name = "RTC", .value = 5 },
1047 { .name = "DCF", .value = 6 },
1048 { .name = "REGS", .value = 0xfe },
1049 { .name = "EXT", .value = 0xff },
1050 { }
1051 };
1052
1053 #define SMA_DISABLE BIT(16)
1054 #define SMA_ENABLE BIT(15)
1055 #define SMA_SELECT_MASK GENMASK(14, 0)
1056
1057 static const struct ocp_selector ptp_ocp_sma_in[] = {
1058 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1059 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1060 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1061 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1062 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1063 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1064 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1065 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1066 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1067 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1068 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1069 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1070 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1071 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1072 { }
1073 };
1074
1075 static const struct ocp_selector ptp_ocp_sma_out[] = {
1076 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1077 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1078 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1079 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1080 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1081 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1082 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1083 { .name = "GEN1", .value = 0x0040 },
1084 { .name = "GEN2", .value = 0x0080 },
1085 { .name = "GEN3", .value = 0x0100 },
1086 { .name = "GEN4", .value = 0x0200 },
1087 { .name = "GND", .value = 0x2000 },
1088 { .name = "VCC", .value = 0x4000 },
1089 { }
1090 };
1091
1092 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1093 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1094 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1095 { }
1096 };
1097
1098 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1099 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1100 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1101 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1102 { }
1103 };
1104
1105 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1106 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1107 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1108 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1109 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1110 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1111 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1112 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1113 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1114 { }
1115 };
1116
1117 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1118 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1119 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1120 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1121 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1122 { .name = "GEN1", .value = 0x0040 },
1123 { .name = "GEN2", .value = 0x0080 },
1124 { .name = "GND", .value = 0x2000 },
1125 { .name = "VCC", .value = 0x4000 },
1126 { }
1127 };
1128
1129 struct ocp_sma_op {
1130 const struct ocp_selector *tbl[2];
1131 void (*init)(struct ptp_ocp *bp);
1132 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1133 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1134 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1135 };
1136
1137 static void
1138 ptp_ocp_sma_init(struct ptp_ocp *bp)
1139 {
1140 return bp->sma_op->init(bp);
1141 }
1142
1143 static u32
1144 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1145 {
1146 return bp->sma_op->get(bp, sma_nr);
1147 }
1148
1149 static int
1150 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1151 {
1152 return bp->sma_op->set_inputs(bp, sma_nr, val);
1153 }
1154
1155 static int
1156 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1157 {
1158 return bp->sma_op->set_output(bp, sma_nr, val);
1159 }
1160
1161 static const char *
1162 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1163 {
1164 int i;
1165
1166 for (i = 0; tbl[i].name; i++)
1167 if (tbl[i].value == val)
1168 return tbl[i].name;
1169 return NULL;
1170 }
1171
1172 static int
1173 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1174 {
1175 const char *select;
1176 int i;
1177
1178 for (i = 0; tbl[i].name; i++) {
1179 select = tbl[i].name;
1180 if (!strncasecmp(name, select, strlen(select)))
1181 return tbl[i].value;
1182 }
1183 return -EINVAL;
1184 }
1185
1186 static ssize_t
1187 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1188 {
1189 ssize_t count;
1190 int i;
1191
1192 count = 0;
1193 for (i = 0; tbl[i].name; i++)
1194 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1195 if (count)
1196 count--;
1197 count += sysfs_emit_at(buf, count, "\n");
1198 return count;
1199 }
1200
1201 static int
1202 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1203 struct ptp_system_timestamp *sts)
1204 {
1205 u32 ctrl, time_sec, time_ns;
1206 int i;
1207
1208 ptp_read_system_prets(sts);
1209
1210 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1211 iowrite32(ctrl, &bp->reg->ctrl);
1212
1213 for (i = 0; i < 100; i++) {
1214 ctrl = ioread32(&bp->reg->ctrl);
1215 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1216 break;
1217 }
1218 ptp_read_system_postts(sts);
1219
1220 if (sts && bp->ts_window_adjust) {
1221 s64 ns = timespec64_to_ns(&sts->post_ts);
1222
1223 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1224 }
1225
1226 time_ns = ioread32(&bp->reg->time_ns);
1227 time_sec = ioread32(&bp->reg->time_sec);
1228
1229 ts->tv_sec = time_sec;
1230 ts->tv_nsec = time_ns;
1231
1232 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1233 }
1234
1235 static int
1236 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1237 struct ptp_system_timestamp *sts)
1238 {
1239 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1240 unsigned long flags;
1241 int err;
1242
1243 spin_lock_irqsave(&bp->lock, flags);
1244 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1245 spin_unlock_irqrestore(&bp->lock, flags);
1246
1247 return err;
1248 }
1249
1250 static void
1251 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1252 {
1253 u32 ctrl, time_sec, time_ns;
1254 u32 select;
1255
1256 time_ns = ts->tv_nsec;
1257 time_sec = ts->tv_sec;
1258
1259 select = ioread32(&bp->reg->select);
1260 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1261
1262 iowrite32(time_ns, &bp->reg->adjust_ns);
1263 iowrite32(time_sec, &bp->reg->adjust_sec);
1264
1265 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1266 iowrite32(ctrl, &bp->reg->ctrl);
1267
1268 /* restore clock selection */
1269 iowrite32(select >> 16, &bp->reg->select);
1270 }
1271
1272 static int
1273 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1274 {
1275 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1276 unsigned long flags;
1277
1278 spin_lock_irqsave(&bp->lock, flags);
1279 __ptp_ocp_settime_locked(bp, ts);
1280 spin_unlock_irqrestore(&bp->lock, flags);
1281
1282 return 0;
1283 }
1284
1285 static void
1286 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1287 {
1288 u32 select, ctrl;
1289
1290 select = ioread32(&bp->reg->select);
1291 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1292
1293 iowrite32(adj_val, &bp->reg->offset_ns);
1294 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1295
1296 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1297 iowrite32(ctrl, &bp->reg->ctrl);
1298
1299 /* restore clock selection */
1300 iowrite32(select >> 16, &bp->reg->select);
1301 }
1302
1303 static void
1304 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1305 {
1306 struct timespec64 ts;
1307 unsigned long flags;
1308 int err;
1309
1310 spin_lock_irqsave(&bp->lock, flags);
1311 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1312 if (likely(!err)) {
1313 set_normalized_timespec64(&ts, ts.tv_sec,
1314 ts.tv_nsec + delta_ns);
1315 __ptp_ocp_settime_locked(bp, &ts);
1316 }
1317 spin_unlock_irqrestore(&bp->lock, flags);
1318 }
1319
1320 static int
1321 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1322 {
1323 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1324 unsigned long flags;
1325 u32 adj_ns, sign;
1326
1327 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1328 ptp_ocp_adjtime_coarse(bp, delta_ns);
1329 return 0;
1330 }
1331
1332 sign = delta_ns < 0 ? BIT(31) : 0;
1333 adj_ns = sign ? -delta_ns : delta_ns;
1334
1335 spin_lock_irqsave(&bp->lock, flags);
1336 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1337 spin_unlock_irqrestore(&bp->lock, flags);
1338
1339 return 0;
1340 }
1341
1342 static int
1343 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1344 {
1345 if (scaled_ppm == 0)
1346 return 0;
1347
1348 return -EOPNOTSUPP;
1349 }
1350
1351 static s32
1352 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1353 {
1354 return 0;
1355 }
1356
1357 static int
1358 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1359 {
1360 return -EOPNOTSUPP;
1361 }
1362
1363 static int
1364 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1365 int on)
1366 {
1367 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1368 struct ptp_ocp_ext_src *ext = NULL;
1369 u32 req;
1370 int err;
1371
1372 switch (rq->type) {
1373 case PTP_CLK_REQ_EXTTS:
1374 req = OCP_REQ_TIMESTAMP;
1375 switch (rq->extts.index) {
1376 case 0:
1377 ext = bp->ts0;
1378 break;
1379 case 1:
1380 ext = bp->ts1;
1381 break;
1382 case 2:
1383 ext = bp->ts2;
1384 break;
1385 case 3:
1386 ext = bp->ts3;
1387 break;
1388 case 4:
1389 ext = bp->ts4;
1390 break;
1391 case 5:
1392 ext = bp->pps;
1393 break;
1394 }
1395 break;
1396 case PTP_CLK_REQ_PPS:
1397 req = OCP_REQ_PPS;
1398 ext = bp->pps;
1399 break;
1400 case PTP_CLK_REQ_PEROUT:
1401 switch (rq->perout.index) {
1402 case 0:
1403 /* This is a request for 1PPS on an output SMA.
1404 * Allow, but assume manual configuration.
1405 */
1406 if (on && (rq->perout.period.sec != 1 ||
1407 rq->perout.period.nsec != 0))
1408 return -EINVAL;
1409 return 0;
1410 case 1:
1411 case 2:
1412 case 3:
1413 case 4:
1414 req = rq->perout.index - 1;
1415 ext = bp->signal_out[req];
1416 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1417 if (err)
1418 return err;
1419 break;
1420 }
1421 break;
1422 default:
1423 return -EOPNOTSUPP;
1424 }
1425
1426 err = -ENXIO;
1427 if (ext)
1428 err = ext->info->enable(ext, req, on);
1429
1430 return err;
1431 }
1432
1433 static int
1434 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1435 enum ptp_pin_function func, unsigned chan)
1436 {
1437 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1438 char buf[16];
1439
1440 switch (func) {
1441 case PTP_PF_NONE:
1442 snprintf(buf, sizeof(buf), "IN: None");
1443 break;
1444 case PTP_PF_EXTTS:
1445 /* Allow timestamps, but require sysfs configuration. */
1446 return 0;
1447 case PTP_PF_PEROUT:
1448 /* channel 0 is 1PPS from PHC.
1449 * channels 1..4 are the frequency generators.
1450 */
1451 if (chan)
1452 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1453 else
1454 snprintf(buf, sizeof(buf), "OUT: PHC");
1455 break;
1456 default:
1457 return -EOPNOTSUPP;
1458 }
1459
1460 return ptp_ocp_sma_store(bp, buf, pin + 1);
1461 }
1462
1463 static const struct ptp_clock_info ptp_ocp_clock_info = {
1464 .owner = THIS_MODULE,
1465 .name = KBUILD_MODNAME,
1466 .max_adj = 100000000,
1467 .gettimex64 = ptp_ocp_gettimex,
1468 .settime64 = ptp_ocp_settime,
1469 .adjtime = ptp_ocp_adjtime,
1470 .adjfine = ptp_ocp_null_adjfine,
1471 .adjphase = ptp_ocp_null_adjphase,
1472 .getmaxphase = ptp_ocp_null_getmaxphase,
1473 .enable = ptp_ocp_enable,
1474 .verify = ptp_ocp_verify,
1475 .pps = true,
1476 .n_ext_ts = 6,
1477 .n_per_out = 5,
1478 };
1479
1480 static void
1481 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1482 {
1483 u32 ctrl, select;
1484
1485 select = ioread32(&bp->reg->select);
1486 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1487
1488 iowrite32(0, &bp->reg->drift_ns);
1489
1490 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1491 iowrite32(ctrl, &bp->reg->ctrl);
1492
1493 /* restore clock selection */
1494 iowrite32(select >> 16, &bp->reg->select);
1495 }
1496
1497 static void
1498 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1499 {
1500 unsigned long flags;
1501
1502 spin_lock_irqsave(&bp->lock, flags);
1503
1504 bp->utc_tai_offset = val;
1505
1506 if (bp->irig_out)
1507 iowrite32(val, &bp->irig_out->adj_sec);
1508 if (bp->dcf_out)
1509 iowrite32(val, &bp->dcf_out->adj_sec);
1510 if (bp->nmea_out)
1511 iowrite32(val, &bp->nmea_out->adj_sec);
1512
1513 spin_unlock_irqrestore(&bp->lock, flags);
1514 }
1515
1516 static void
1517 ptp_ocp_watchdog(struct timer_list *t)
1518 {
1519 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1520 unsigned long flags;
1521 u32 status, utc_offset;
1522
1523 status = ioread32(&bp->pps_to_clk->status);
1524
1525 if (status & PPS_STATUS_SUPERV_ERR) {
1526 iowrite32(status, &bp->pps_to_clk->status);
1527 if (!bp->gnss_lost) {
1528 spin_lock_irqsave(&bp->lock, flags);
1529 __ptp_ocp_clear_drift_locked(bp);
1530 spin_unlock_irqrestore(&bp->lock, flags);
1531 bp->gnss_lost = ktime_get_real_seconds();
1532 }
1533
1534 } else if (bp->gnss_lost) {
1535 bp->gnss_lost = 0;
1536 }
1537
1538 /* if GNSS provides correct data we can rely on
1539 * it to get leap second information
1540 */
1541 if (bp->tod) {
1542 status = ioread32(&bp->tod->utc_status);
1543 utc_offset = status & TOD_STATUS_UTC_MASK;
1544 if (status & TOD_STATUS_UTC_VALID &&
1545 utc_offset != bp->utc_tai_offset)
1546 ptp_ocp_utc_distribute(bp, utc_offset);
1547 }
1548
1549 mod_timer(&bp->watchdog, jiffies + HZ);
1550 }
1551
1552 static void
1553 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1554 {
1555 ktime_t start, end;
1556 ktime_t delay;
1557 u32 ctrl;
1558
1559 ctrl = ioread32(&bp->reg->ctrl);
1560 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1561
1562 iowrite32(ctrl, &bp->reg->ctrl);
1563
1564 start = ktime_get_ns();
1565
1566 ctrl = ioread32(&bp->reg->ctrl);
1567
1568 end = ktime_get_ns();
1569
1570 delay = end - start;
1571 bp->ts_window_adjust = (delay >> 5) * 3;
1572 }
1573
1574 static int
1575 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1576 {
1577 struct timespec64 ts;
1578 u32 ctrl;
1579
1580 ctrl = OCP_CTRL_ENABLE;
1581 iowrite32(ctrl, &bp->reg->ctrl);
1582
1583 /* servo configuration */
1584 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1585 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1586 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1587 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1588
1589 /* latch servo values */
1590 ctrl |= OCP_CTRL_ADJUST_SERVO;
1591 iowrite32(ctrl, &bp->reg->ctrl);
1592
1593 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1594 dev_err(&bp->pdev->dev, "clock not enabled\n");
1595 return -ENODEV;
1596 }
1597
1598 ptp_ocp_estimate_pci_timing(bp);
1599
1600 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1601 if (!bp->sync) {
1602 ktime_get_clocktai_ts64(&ts);
1603 ptp_ocp_settime(&bp->ptp_info, &ts);
1604 }
1605
1606 /* If there is a clock supervisor, then enable the watchdog */
1607 if (bp->pps_to_clk) {
1608 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1609 mod_timer(&bp->watchdog, jiffies + HZ);
1610 }
1611
1612 return 0;
1613 }
1614
1615 static void
1616 ptp_ocp_tod_init(struct ptp_ocp *bp)
1617 {
1618 u32 ctrl, reg;
1619
1620 ctrl = ioread32(&bp->tod->ctrl);
1621 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1622 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1623 iowrite32(ctrl, &bp->tod->ctrl);
1624
1625 reg = ioread32(&bp->tod->utc_status);
1626 if (reg & TOD_STATUS_UTC_VALID)
1627 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1628 }
1629
1630 static const char *
1631 ptp_ocp_tod_proto_name(const int idx)
1632 {
1633 static const char * const proto_name[] = {
1634 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1635 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1636 };
1637 return proto_name[idx];
1638 }
1639
1640 static const char *
1641 ptp_ocp_tod_gnss_name(int idx)
1642 {
1643 static const char * const gnss_name[] = {
1644 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1645 "Unknown"
1646 };
1647 if (idx >= ARRAY_SIZE(gnss_name))
1648 idx = ARRAY_SIZE(gnss_name) - 1;
1649 return gnss_name[idx];
1650 }
1651
1652 struct ptp_ocp_nvmem_match_info {
1653 struct ptp_ocp *bp;
1654 const void * const tag;
1655 };
1656
1657 static int
1658 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1659 {
1660 const struct ptp_ocp_nvmem_match_info *info = data;
1661
1662 dev = dev->parent;
1663 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1664 return 0;
1665
1666 while ((dev = dev->parent))
1667 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1668 return info->bp == dev_get_drvdata(dev);
1669 return 0;
1670 }
1671
1672 static inline struct nvmem_device *
1673 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1674 {
1675 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1676
1677 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1678 }
1679
1680 static inline void
1681 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1682 {
1683 if (!IS_ERR_OR_NULL(*nvmemp))
1684 nvmem_device_put(*nvmemp);
1685 *nvmemp = NULL;
1686 }
1687
1688 static void
1689 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1690 {
1691 const struct ptp_ocp_eeprom_map *map;
1692 struct nvmem_device *nvmem;
1693 const void *tag;
1694 int ret;
1695
1696 if (!bp->i2c_ctrl)
1697 return;
1698
1699 tag = NULL;
1700 nvmem = NULL;
1701
1702 for (map = bp->eeprom_map; map->len; map++) {
1703 if (map->tag != tag) {
1704 tag = map->tag;
1705 ptp_ocp_nvmem_device_put(&nvmem);
1706 }
1707 if (!nvmem) {
1708 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1709 if (IS_ERR(nvmem)) {
1710 ret = PTR_ERR(nvmem);
1711 goto fail;
1712 }
1713 }
1714 ret = nvmem_device_read(nvmem, map->off, map->len,
1715 BP_MAP_ENTRY_ADDR(bp, map));
1716 if (ret != map->len)
1717 goto fail;
1718 }
1719
1720 bp->has_eeprom_data = true;
1721
1722 out:
1723 ptp_ocp_nvmem_device_put(&nvmem);
1724 return;
1725
1726 fail:
1727 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1728 goto out;
1729 }
1730
1731 static struct device *
1732 ptp_ocp_find_flash(struct ptp_ocp *bp)
1733 {
1734 struct device *dev, *last;
1735
1736 last = NULL;
1737 dev = &bp->spi_flash->dev;
1738
1739 while ((dev = device_find_any_child(dev))) {
1740 if (!strcmp("mtd", dev_bus_name(dev)))
1741 break;
1742 put_device(last);
1743 last = dev;
1744 }
1745 put_device(last);
1746
1747 return dev;
1748 }
1749
1750 static int
1751 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1752 const u8 **data, size_t *size)
1753 {
1754 struct ptp_ocp *bp = devlink_priv(devlink);
1755 const struct ptp_ocp_firmware_header *hdr;
1756 size_t offset, length;
1757 u16 crc;
1758
1759 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1760 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1761 devlink_flash_update_status_notify(devlink,
1762 "No firmware header found, cancel firmware upgrade",
1763 NULL, 0, 0);
1764 return -EINVAL;
1765 }
1766
1767 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1768 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1769 devlink_flash_update_status_notify(devlink,
1770 "Firmware image compatibility check failed",
1771 NULL, 0, 0);
1772 return -EINVAL;
1773 }
1774
1775 offset = sizeof(*hdr);
1776 length = be32_to_cpu(hdr->image_size);
1777 if (length != (fw->size - offset)) {
1778 devlink_flash_update_status_notify(devlink,
1779 "Firmware image size check failed",
1780 NULL, 0, 0);
1781 return -EINVAL;
1782 }
1783
1784 crc = crc16(0xffff, &fw->data[offset], length);
1785 if (be16_to_cpu(hdr->crc) != crc) {
1786 devlink_flash_update_status_notify(devlink,
1787 "Firmware image CRC check failed",
1788 NULL, 0, 0);
1789 return -EINVAL;
1790 }
1791
1792 *data = &fw->data[offset];
1793 *size = length;
1794
1795 return 0;
1796 }
1797
1798 static int
1799 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1800 const struct firmware *fw)
1801 {
1802 struct mtd_info *mtd = dev_get_drvdata(dev);
1803 struct ptp_ocp *bp = devlink_priv(devlink);
1804 size_t off, len, size, resid, wrote;
1805 struct erase_info erase;
1806 size_t base, blksz;
1807 const u8 *data;
1808 int err;
1809
1810 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1811 if (err)
1812 goto out;
1813
1814 off = 0;
1815 base = bp->flash_start;
1816 blksz = 4096;
1817 resid = size;
1818
1819 while (resid) {
1820 devlink_flash_update_status_notify(devlink, "Flashing",
1821 NULL, off, size);
1822
1823 len = min_t(size_t, resid, blksz);
1824 erase.addr = base + off;
1825 erase.len = blksz;
1826
1827 err = mtd_erase(mtd, &erase);
1828 if (err)
1829 goto out;
1830
1831 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1832 if (err)
1833 goto out;
1834
1835 off += blksz;
1836 resid -= len;
1837 }
1838 out:
1839 return err;
1840 }
1841
1842 static int
1843 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1844 struct devlink_flash_update_params *params,
1845 struct netlink_ext_ack *extack)
1846 {
1847 struct ptp_ocp *bp = devlink_priv(devlink);
1848 struct device *dev;
1849 const char *msg;
1850 int err;
1851
1852 dev = ptp_ocp_find_flash(bp);
1853 if (!dev) {
1854 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1855 return -ENODEV;
1856 }
1857
1858 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1859 NULL, 0, 0);
1860
1861 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1862
1863 msg = err ? "Flash error" : "Flash complete";
1864 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1865
1866 put_device(dev);
1867 return err;
1868 }
1869
1870 static int
1871 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1872 struct netlink_ext_ack *extack)
1873 {
1874 struct ptp_ocp *bp = devlink_priv(devlink);
1875 const char *fw_image;
1876 char buf[32];
1877 int err;
1878
1879 fw_image = bp->fw_loader ? "loader" : "fw";
1880 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1881 err = devlink_info_version_running_put(req, fw_image, buf);
1882 if (err)
1883 return err;
1884
1885 if (!bp->has_eeprom_data) {
1886 ptp_ocp_read_eeprom(bp);
1887 if (!bp->has_eeprom_data)
1888 return 0;
1889 }
1890
1891 sprintf(buf, "%pM", bp->serial);
1892 err = devlink_info_serial_number_put(req, buf);
1893 if (err)
1894 return err;
1895
1896 err = devlink_info_version_fixed_put(req,
1897 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1898 bp->board_id);
1899 if (err)
1900 return err;
1901
1902 return 0;
1903 }
1904
1905 static const struct devlink_ops ptp_ocp_devlink_ops = {
1906 .flash_update = ptp_ocp_devlink_flash_update,
1907 .info_get = ptp_ocp_devlink_info_get,
1908 };
1909
1910 static void __iomem *
1911 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1912 {
1913 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1914
1915 return devm_ioremap_resource(&bp->pdev->dev, &res);
1916 }
1917
1918 static void __iomem *
1919 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1920 {
1921 resource_size_t start;
1922
1923 start = pci_resource_start(bp->pdev, 0) + r->offset;
1924 return __ptp_ocp_get_mem(bp, start, r->size);
1925 }
1926
1927 static int
1928 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1929 {
1930 struct ptp_ocp_flash_info *info;
1931 struct pci_dev *pdev = bp->pdev;
1932 struct platform_device *p;
1933 struct resource res[2];
1934 resource_size_t start;
1935 int id;
1936
1937 start = pci_resource_start(pdev, 0) + r->offset;
1938 res[0] = DEFINE_RES_MEM(start, r->size);
1939 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1940
1941 info = r->extra;
1942 id = pci_dev_id(pdev) << 1;
1943 id += info->pci_offset;
1944
1945 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1946 res, ARRAY_SIZE(res), info->data,
1947 info->data_size);
1948 if (IS_ERR(p))
1949 return PTR_ERR(p);
1950
1951 bp_assign_entry(bp, r, p);
1952
1953 return 0;
1954 }
1955
1956 static struct platform_device *
1957 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1958 {
1959 struct ptp_ocp_i2c_info *info;
1960 struct resource res[2];
1961 resource_size_t start;
1962
1963 info = r->extra;
1964 start = pci_resource_start(pdev, 0) + r->offset;
1965 res[0] = DEFINE_RES_MEM(start, r->size);
1966 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1967
1968 return platform_device_register_resndata(&pdev->dev, info->name,
1969 id, res, ARRAY_SIZE(res),
1970 info->data, info->data_size);
1971 }
1972
1973 static int
1974 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1975 {
1976 struct pci_dev *pdev = bp->pdev;
1977 struct ptp_ocp_i2c_info *info;
1978 struct platform_device *p;
1979 struct clk_hw *clk;
1980 char buf[32];
1981 int id;
1982
1983 info = r->extra;
1984 id = pci_dev_id(bp->pdev);
1985
1986 sprintf(buf, "AXI.%d", id);
1987 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
1988 info->fixed_rate);
1989 if (IS_ERR(clk))
1990 return PTR_ERR(clk);
1991 bp->i2c_clk = clk;
1992
1993 sprintf(buf, "%s.%d", info->name, id);
1994 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
1995 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
1996 if (IS_ERR(p))
1997 return PTR_ERR(p);
1998
1999 bp_assign_entry(bp, r, p);
2000
2001 return 0;
2002 }
2003
2004 /* The expectation is that this is triggered only on error. */
2005 static irqreturn_t
2006 ptp_ocp_signal_irq(int irq, void *priv)
2007 {
2008 struct ptp_ocp_ext_src *ext = priv;
2009 struct signal_reg __iomem *reg = ext->mem;
2010 struct ptp_ocp *bp = ext->bp;
2011 u32 enable, status;
2012 int gen;
2013
2014 gen = ext->info->index - 1;
2015
2016 enable = ioread32(&reg->enable);
2017 status = ioread32(&reg->status);
2018
2019 /* disable generator on error */
2020 if (status || !enable) {
2021 iowrite32(0, &reg->intr_mask);
2022 iowrite32(0, &reg->enable);
2023 bp->signal[gen].running = false;
2024 }
2025
2026 iowrite32(0, &reg->intr); /* ack interrupt */
2027
2028 return IRQ_HANDLED;
2029 }
2030
2031 static int
2032 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2033 {
2034 struct ptp_system_timestamp sts;
2035 struct timespec64 ts;
2036 ktime_t start_ns;
2037 int err;
2038
2039 if (!s->period)
2040 return 0;
2041
2042 if (!s->pulse)
2043 s->pulse = ktime_divns(s->period * s->duty, 100);
2044
2045 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2046 if (err)
2047 return err;
2048
2049 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2050 if (!s->start) {
2051 /* roundup() does not work on 32-bit systems */
2052 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2053 s->start = ktime_add(s->start, s->phase);
2054 }
2055
2056 if (s->duty < 1 || s->duty > 99)
2057 return -EINVAL;
2058
2059 if (s->pulse < 1 || s->pulse > s->period)
2060 return -EINVAL;
2061
2062 if (s->start < start_ns)
2063 return -EINVAL;
2064
2065 bp->signal[gen] = *s;
2066
2067 return 0;
2068 }
2069
2070 static int
2071 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2072 struct ptp_perout_request *req)
2073 {
2074 struct ptp_ocp_signal s = { };
2075
2076 s.polarity = bp->signal[gen].polarity;
2077 s.period = ktime_set(req->period.sec, req->period.nsec);
2078 if (!s.period)
2079 return 0;
2080
2081 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2082 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2083 s.duty = ktime_divns(s.pulse * 100, s.period);
2084 }
2085
2086 if (req->flags & PTP_PEROUT_PHASE)
2087 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2088 else
2089 s.start = ktime_set(req->start.sec, req->start.nsec);
2090
2091 return ptp_ocp_signal_set(bp, gen, &s);
2092 }
2093
2094 static int
2095 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2096 {
2097 struct ptp_ocp_ext_src *ext = priv;
2098 struct signal_reg __iomem *reg = ext->mem;
2099 struct ptp_ocp *bp = ext->bp;
2100 struct timespec64 ts;
2101 int gen;
2102
2103 gen = ext->info->index - 1;
2104
2105 iowrite32(0, &reg->intr_mask);
2106 iowrite32(0, &reg->enable);
2107 bp->signal[gen].running = false;
2108 if (!enable)
2109 return 0;
2110
2111 ts = ktime_to_timespec64(bp->signal[gen].start);
2112 iowrite32(ts.tv_sec, &reg->start_sec);
2113 iowrite32(ts.tv_nsec, &reg->start_ns);
2114
2115 ts = ktime_to_timespec64(bp->signal[gen].period);
2116 iowrite32(ts.tv_sec, &reg->period_sec);
2117 iowrite32(ts.tv_nsec, &reg->period_ns);
2118
2119 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2120 iowrite32(ts.tv_sec, &reg->pulse_sec);
2121 iowrite32(ts.tv_nsec, &reg->pulse_ns);
2122
2123 iowrite32(bp->signal[gen].polarity, &reg->polarity);
2124 iowrite32(0, &reg->repeat_count);
2125
2126 iowrite32(0, &reg->intr); /* clear interrupt state */
2127 iowrite32(1, &reg->intr_mask); /* enable interrupt */
2128 iowrite32(3, &reg->enable); /* valid & enable */
2129
2130 bp->signal[gen].running = true;
2131
2132 return 0;
2133 }
2134
2135 static irqreturn_t
2136 ptp_ocp_ts_irq(int irq, void *priv)
2137 {
2138 struct ptp_ocp_ext_src *ext = priv;
2139 struct ts_reg __iomem *reg = ext->mem;
2140 struct ptp_clock_event ev;
2141 u32 sec, nsec;
2142
2143 if (ext == ext->bp->pps) {
2144 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2145 ev.type = PTP_CLOCK_PPS;
2146 ptp_clock_event(ext->bp->ptp, &ev);
2147 }
2148
2149 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2150 goto out;
2151 }
2152
2153 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2154 sec = ioread32(&reg->time_sec);
2155 nsec = ioread32(&reg->time_ns);
2156
2157 ev.type = PTP_CLOCK_EXTTS;
2158 ev.index = ext->info->index;
2159 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2160
2161 ptp_clock_event(ext->bp->ptp, &ev);
2162
2163 out:
2164 iowrite32(1, &reg->intr); /* write 1 to ack */
2165
2166 return IRQ_HANDLED;
2167 }
2168
2169 static int
2170 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2171 {
2172 struct ptp_ocp_ext_src *ext = priv;
2173 struct ts_reg __iomem *reg = ext->mem;
2174 struct ptp_ocp *bp = ext->bp;
2175
2176 if (ext == bp->pps) {
2177 u32 old_map = bp->pps_req_map;
2178
2179 if (enable)
2180 bp->pps_req_map |= req;
2181 else
2182 bp->pps_req_map &= ~req;
2183
2184 /* if no state change, just return */
2185 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2186 return 0;
2187 }
2188
2189 if (enable) {
2190 iowrite32(1, &reg->enable);
2191 iowrite32(1, &reg->intr_mask);
2192 iowrite32(1, &reg->intr);
2193 } else {
2194 iowrite32(0, &reg->intr_mask);
2195 iowrite32(0, &reg->enable);
2196 }
2197
2198 return 0;
2199 }
2200
2201 static void
2202 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2203 {
2204 ext->info->enable(ext, ~0, false);
2205 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2206 kfree(ext);
2207 }
2208
2209 static int
2210 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2211 {
2212 struct pci_dev *pdev = bp->pdev;
2213 struct ptp_ocp_ext_src *ext;
2214 int err;
2215
2216 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2217 if (!ext)
2218 return -ENOMEM;
2219
2220 ext->mem = ptp_ocp_get_mem(bp, r);
2221 if (IS_ERR(ext->mem)) {
2222 err = PTR_ERR(ext->mem);
2223 goto out;
2224 }
2225
2226 ext->bp = bp;
2227 ext->info = r->extra;
2228 ext->irq_vec = r->irq_vec;
2229
2230 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2231 ext, "ocp%d.%s", bp->id, r->name);
2232 if (err) {
2233 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2234 goto out;
2235 }
2236
2237 bp_assign_entry(bp, r, ext);
2238
2239 return 0;
2240
2241 out:
2242 kfree(ext);
2243 return err;
2244 }
2245
2246 static int
2247 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2248 {
2249 struct pci_dev *pdev = bp->pdev;
2250 struct uart_8250_port uart;
2251
2252 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2253 * the serial port device claim and release the pci resource.
2254 */
2255 memset(&uart, 0, sizeof(uart));
2256 uart.port.dev = &pdev->dev;
2257 uart.port.iotype = UPIO_MEM;
2258 uart.port.regshift = 2;
2259 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2260 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2261 uart.port.uartclk = 50000000;
2262 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2263 uart.port.type = PORT_16550A;
2264
2265 return serial8250_register_8250_port(&uart);
2266 }
2267
2268 static int
2269 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2270 {
2271 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2272 struct ptp_ocp_serial_port port = {};
2273
2274 port.line = ptp_ocp_serial_line(bp, r);
2275 if (port.line < 0)
2276 return port.line;
2277
2278 if (p)
2279 port.baud = p->baud;
2280
2281 bp_assign_entry(bp, r, port);
2282
2283 return 0;
2284 }
2285
2286 static int
2287 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2288 {
2289 void __iomem *mem;
2290
2291 mem = ptp_ocp_get_mem(bp, r);
2292 if (IS_ERR(mem))
2293 return PTR_ERR(mem);
2294
2295 bp_assign_entry(bp, r, mem);
2296
2297 return 0;
2298 }
2299
2300 static void
2301 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2302 {
2303 if (!bp->nmea_out)
2304 return;
2305
2306 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2307 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2308 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2309 }
2310
2311 static void
2312 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2313 {
2314 u32 val;
2315
2316 iowrite32(0, &reg->enable); /* disable */
2317
2318 val = ioread32(&reg->polarity);
2319 s->polarity = val ? true : false;
2320 s->duty = 50;
2321 }
2322
2323 static void
2324 ptp_ocp_signal_init(struct ptp_ocp *bp)
2325 {
2326 int i;
2327
2328 for (i = 0; i < 4; i++)
2329 if (bp->signal_out[i])
2330 _ptp_ocp_signal_init(&bp->signal[i],
2331 bp->signal_out[i]->mem);
2332 }
2333
2334 static void
2335 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2336 {
2337 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2338 kfree(bp->attr_group);
2339 }
2340
2341 static int
2342 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2343 const struct ocp_attr_group *attr_tbl)
2344 {
2345 int count, i;
2346 int err;
2347
2348 count = 0;
2349 for (i = 0; attr_tbl[i].cap; i++)
2350 if (attr_tbl[i].cap & bp->fw_cap)
2351 count++;
2352
2353 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2354 GFP_KERNEL);
2355 if (!bp->attr_group)
2356 return -ENOMEM;
2357
2358 count = 0;
2359 for (i = 0; attr_tbl[i].cap; i++)
2360 if (attr_tbl[i].cap & bp->fw_cap)
2361 bp->attr_group[count++] = attr_tbl[i].group;
2362
2363 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2364 if (err)
2365 bp->attr_group[0] = NULL;
2366
2367 return err;
2368 }
2369
2370 static void
2371 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2372 {
2373 u32 ctrl;
2374 bool on;
2375
2376 ctrl = ioread32(reg);
2377 on = ctrl & bit;
2378 if (on ^ enable) {
2379 ctrl &= ~bit;
2380 ctrl |= enable ? bit : 0;
2381 iowrite32(ctrl, reg);
2382 }
2383 }
2384
2385 static void
2386 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2387 {
2388 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2389 IRIG_M_CTRL_ENABLE, enable);
2390 }
2391
2392 static void
2393 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2394 {
2395 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2396 IRIG_S_CTRL_ENABLE, enable);
2397 }
2398
2399 static void
2400 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2401 {
2402 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2403 DCF_M_CTRL_ENABLE, enable);
2404 }
2405
2406 static void
2407 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2408 {
2409 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2410 DCF_S_CTRL_ENABLE, enable);
2411 }
2412
2413 static void
2414 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2415 {
2416 ptp_ocp_irig_out(bp, val & 0x00100010);
2417 ptp_ocp_dcf_out(bp, val & 0x00200020);
2418 }
2419
2420 static void
2421 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2422 {
2423 ptp_ocp_irig_in(bp, val & 0x00100010);
2424 ptp_ocp_dcf_in(bp, val & 0x00200020);
2425 }
2426
2427 static u32
2428 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2429 {
2430 u32 __iomem *gpio;
2431 u32 shift;
2432
2433 if (bp->sma[sma_nr - 1].fixed_fcn)
2434 return (sma_nr - 1) & 1;
2435
2436 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2437 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2438 else
2439 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2440 shift = sma_nr & 1 ? 0 : 16;
2441
2442 return (ioread32(gpio) >> shift) & 0xffff;
2443 }
2444
2445 static int
2446 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2447 {
2448 u32 reg, mask, shift;
2449 unsigned long flags;
2450 u32 __iomem *gpio;
2451
2452 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2453 shift = sma_nr & 1 ? 0 : 16;
2454
2455 mask = 0xffff << (16 - shift);
2456
2457 spin_lock_irqsave(&bp->lock, flags);
2458
2459 reg = ioread32(gpio);
2460 reg = (reg & mask) | (val << shift);
2461
2462 __handle_signal_outputs(bp, reg);
2463
2464 iowrite32(reg, gpio);
2465
2466 spin_unlock_irqrestore(&bp->lock, flags);
2467
2468 return 0;
2469 }
2470
2471 static int
2472 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2473 {
2474 u32 reg, mask, shift;
2475 unsigned long flags;
2476 u32 __iomem *gpio;
2477
2478 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2479 shift = sma_nr & 1 ? 0 : 16;
2480
2481 mask = 0xffff << (16 - shift);
2482
2483 spin_lock_irqsave(&bp->lock, flags);
2484
2485 reg = ioread32(gpio);
2486 reg = (reg & mask) | (val << shift);
2487
2488 __handle_signal_inputs(bp, reg);
2489
2490 iowrite32(reg, gpio);
2491
2492 spin_unlock_irqrestore(&bp->lock, flags);
2493
2494 return 0;
2495 }
2496
2497 static void
2498 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2499 {
2500 struct dpll_pin_properties prop = {
2501 .board_label = NULL,
2502 .type = DPLL_PIN_TYPE_EXT,
2503 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2504 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2505 .freq_supported = ptp_ocp_sma_freq,
2506
2507 };
2508 u32 reg;
2509 int i;
2510
2511 /* defaults */
2512 for (i = 0; i < OCP_SMA_NUM; i++) {
2513 bp->sma[i].default_fcn = i & 1;
2514 bp->sma[i].dpll_prop = prop;
2515 bp->sma[i].dpll_prop.board_label =
2516 bp->ptp_info.pin_config[i].name;
2517 }
2518 bp->sma[0].mode = SMA_MODE_IN;
2519 bp->sma[1].mode = SMA_MODE_IN;
2520 bp->sma[2].mode = SMA_MODE_OUT;
2521 bp->sma[3].mode = SMA_MODE_OUT;
2522 /* If no SMA1 map, the pin functions and directions are fixed. */
2523 if (!bp->sma_map1) {
2524 for (i = 0; i < OCP_SMA_NUM; i++) {
2525 bp->sma[i].fixed_fcn = true;
2526 bp->sma[i].fixed_dir = true;
2527 bp->sma[1].dpll_prop.capabilities &=
2528 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2529 }
2530 return;
2531 }
2532
2533 /* If SMA2 GPIO output map is all 1, it is not present.
2534 * This indicates the firmware has fixed direction SMA pins.
2535 */
2536 reg = ioread32(&bp->sma_map2->gpio2);
2537 if (reg == 0xffffffff) {
2538 for (i = 0; i < OCP_SMA_NUM; i++)
2539 bp->sma[i].fixed_dir = true;
2540 } else {
2541 reg = ioread32(&bp->sma_map1->gpio1);
2542 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2543 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2544
2545 reg = ioread32(&bp->sma_map1->gpio2);
2546 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2547 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2548 }
2549 }
2550
2551 static const struct ocp_sma_op ocp_fb_sma_op = {
2552 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2553 .init = ptp_ocp_sma_fb_init,
2554 .get = ptp_ocp_sma_fb_get,
2555 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2556 .set_output = ptp_ocp_sma_fb_set_output,
2557 };
2558
2559 static const struct ocp_sma_op ocp_adva_sma_op = {
2560 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2561 .init = ptp_ocp_sma_fb_init,
2562 .get = ptp_ocp_sma_fb_get,
2563 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2564 .set_output = ptp_ocp_sma_fb_set_output,
2565 };
2566
2567 static int
2568 ptp_ocp_set_pins(struct ptp_ocp *bp)
2569 {
2570 struct ptp_pin_desc *config;
2571 int i;
2572
2573 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2574 if (!config)
2575 return -ENOMEM;
2576
2577 for (i = 0; i < 4; i++) {
2578 sprintf(config[i].name, "sma%d", i + 1);
2579 config[i].index = i;
2580 }
2581
2582 bp->ptp_info.n_pins = 4;
2583 bp->ptp_info.pin_config = config;
2584
2585 return 0;
2586 }
2587
2588 static void
2589 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2590 {
2591 u64 cap = OCP_CAP_BASIC;
2592 u32 version;
2593
2594 version = ioread32(&bp->image->version);
2595
2596 /* if lower 16 bits are empty, this is the fw loader. */
2597 if ((version & 0xffff) == 0) {
2598 version = version >> 16;
2599 bp->fw_loader = true;
2600 }
2601
2602 bp->fw_tag = version >> 15;
2603 bp->fw_version = version & 0x7fff;
2604
2605 if (bp->fw_tag) {
2606 /* FPGA firmware */
2607 if (version >= 5)
2608 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2609 } else {
2610 /* SOM firmware */
2611 if (version >= 19)
2612 cap |= OCP_CAP_SIGNAL;
2613 if (version >= 20)
2614 cap |= OCP_CAP_FREQ;
2615 }
2616
2617 bp->fw_cap = cap;
2618 }
2619
2620 /* FB specific board initializers; last "resource" registered. */
2621 static int
2622 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2623 {
2624 int err;
2625
2626 bp->flash_start = 1024 * 4096;
2627 bp->eeprom_map = fb_eeprom_map;
2628 bp->fw_version = ioread32(&bp->image->version);
2629 bp->sma_op = &ocp_fb_sma_op;
2630
2631 ptp_ocp_fb_set_version(bp);
2632
2633 ptp_ocp_tod_init(bp);
2634 ptp_ocp_nmea_out_init(bp);
2635 ptp_ocp_signal_init(bp);
2636
2637 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2638 if (err)
2639 return err;
2640
2641 err = ptp_ocp_set_pins(bp);
2642 if (err)
2643 return err;
2644 ptp_ocp_sma_init(bp);
2645
2646 return ptp_ocp_init_clock(bp, r->extra);
2647 }
2648
2649 static bool
2650 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2651 {
2652 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2653
2654 if (!allow)
2655 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2656 r->irq_vec, r->name);
2657 return allow;
2658 }
2659
2660 static int
2661 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2662 {
2663 struct ocp_resource *r, *table;
2664 int err = 0;
2665
2666 table = (struct ocp_resource *)driver_data;
2667 for (r = table; r->setup; r++) {
2668 if (!ptp_ocp_allow_irq(bp, r))
2669 continue;
2670 err = r->setup(bp, r);
2671 if (err) {
2672 dev_err(&bp->pdev->dev,
2673 "Could not register %s: err %d\n",
2674 r->name, err);
2675 break;
2676 }
2677 }
2678 return err;
2679 }
2680
2681 static void
2682 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2683 {
2684 struct dpll_pin_properties prop = {
2685 .board_label = NULL,
2686 .type = DPLL_PIN_TYPE_EXT,
2687 .capabilities = 0,
2688 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2689 .freq_supported = ptp_ocp_sma_freq,
2690
2691 };
2692 u32 reg;
2693 int i;
2694
2695 /* defaults */
2696 bp->sma[0].mode = SMA_MODE_IN;
2697 bp->sma[1].mode = SMA_MODE_IN;
2698 bp->sma[2].mode = SMA_MODE_OUT;
2699 bp->sma[3].mode = SMA_MODE_OUT;
2700
2701 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2702 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2703 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2704 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2705
2706 for (i = 0; i < OCP_SMA_NUM; i++) {
2707 /* If no SMA map, the pin functions and directions are fixed. */
2708 bp->sma[i].dpll_prop = prop;
2709 bp->sma[i].dpll_prop.board_label =
2710 bp->ptp_info.pin_config[i].name;
2711 if (!bp->art_sma) {
2712 bp->sma[i].fixed_fcn = true;
2713 bp->sma[i].fixed_dir = true;
2714 continue;
2715 }
2716 reg = ioread32(&bp->art_sma->map[i].gpio);
2717
2718 switch (reg & 0xff) {
2719 case 0:
2720 bp->sma[i].fixed_fcn = true;
2721 bp->sma[i].fixed_dir = true;
2722 break;
2723 case 1:
2724 case 8:
2725 bp->sma[i].mode = SMA_MODE_IN;
2726 bp->sma[i].dpll_prop.capabilities =
2727 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2728 break;
2729 default:
2730 bp->sma[i].mode = SMA_MODE_OUT;
2731 bp->sma[i].dpll_prop.capabilities =
2732 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2733 break;
2734 }
2735 }
2736 }
2737
2738 static u32
2739 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2740 {
2741 if (bp->sma[sma_nr - 1].fixed_fcn)
2742 return bp->sma[sma_nr - 1].default_fcn;
2743
2744 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2745 }
2746
2747 /* note: store 0 is considered invalid. */
2748 static int
2749 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2750 {
2751 unsigned long flags;
2752 u32 __iomem *gpio;
2753 int err = 0;
2754 u32 reg;
2755
2756 val &= SMA_SELECT_MASK;
2757 if (hweight32(val) > 1)
2758 return -EINVAL;
2759
2760 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2761
2762 spin_lock_irqsave(&bp->lock, flags);
2763 reg = ioread32(gpio);
2764 if (((reg >> 16) & val) == 0) {
2765 err = -EOPNOTSUPP;
2766 } else {
2767 reg = (reg & 0xff00) | (val & 0xff);
2768 iowrite32(reg, gpio);
2769 }
2770 spin_unlock_irqrestore(&bp->lock, flags);
2771
2772 return err;
2773 }
2774
2775 static const struct ocp_sma_op ocp_art_sma_op = {
2776 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2777 .init = ptp_ocp_art_sma_init,
2778 .get = ptp_ocp_art_sma_get,
2779 .set_inputs = ptp_ocp_art_sma_set,
2780 .set_output = ptp_ocp_art_sma_set,
2781 };
2782
2783 /* ART specific board initializers; last "resource" registered. */
2784 static int
2785 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2786 {
2787 int err;
2788
2789 bp->flash_start = 0x1000000;
2790 bp->eeprom_map = art_eeprom_map;
2791 bp->fw_cap = OCP_CAP_BASIC;
2792 bp->fw_version = ioread32(&bp->reg->version);
2793 bp->fw_tag = 2;
2794 bp->sma_op = &ocp_art_sma_op;
2795
2796 /* Enable MAC serial port during initialisation */
2797 iowrite32(1, &bp->board_config->mro50_serial_activate);
2798
2799 err = ptp_ocp_set_pins(bp);
2800 if (err)
2801 return err;
2802 ptp_ocp_sma_init(bp);
2803
2804 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2805 if (err)
2806 return err;
2807
2808 return ptp_ocp_init_clock(bp, r->extra);
2809 }
2810
2811 /* ADVA specific board initializers; last "resource" registered. */
2812 static int
2813 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2814 {
2815 int err;
2816 u32 version;
2817
2818 bp->flash_start = 0xA00000;
2819 bp->eeprom_map = fb_eeprom_map;
2820 bp->sma_op = &ocp_adva_sma_op;
2821
2822 version = ioread32(&bp->image->version);
2823 /* if lower 16 bits are empty, this is the fw loader. */
2824 if ((version & 0xffff) == 0) {
2825 version = version >> 16;
2826 bp->fw_loader = true;
2827 }
2828 bp->fw_tag = 3;
2829 bp->fw_version = version & 0xffff;
2830 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2831
2832 ptp_ocp_tod_init(bp);
2833 ptp_ocp_nmea_out_init(bp);
2834 ptp_ocp_signal_init(bp);
2835
2836 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2837 if (err)
2838 return err;
2839
2840 err = ptp_ocp_set_pins(bp);
2841 if (err)
2842 return err;
2843 ptp_ocp_sma_init(bp);
2844
2845 return ptp_ocp_init_clock(bp, r->extra);
2846 }
2847
2848 static ssize_t
2849 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2850 int def_val)
2851 {
2852 const char *name;
2853 ssize_t count;
2854
2855 count = sysfs_emit(buf, "OUT: ");
2856 name = ptp_ocp_select_name_from_val(tbl, val);
2857 if (!name)
2858 name = ptp_ocp_select_name_from_val(tbl, def_val);
2859 count += sysfs_emit_at(buf, count, "%s\n", name);
2860 return count;
2861 }
2862
2863 static ssize_t
2864 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2865 int def_val)
2866 {
2867 const char *name;
2868 ssize_t count;
2869 int i;
2870
2871 count = sysfs_emit(buf, "IN: ");
2872 for (i = 0; tbl[i].name; i++) {
2873 if (val & tbl[i].value) {
2874 name = tbl[i].name;
2875 count += sysfs_emit_at(buf, count, "%s ", name);
2876 }
2877 }
2878 if (!val && def_val >= 0) {
2879 name = ptp_ocp_select_name_from_val(tbl, def_val);
2880 count += sysfs_emit_at(buf, count, "%s ", name);
2881 }
2882 if (count)
2883 count--;
2884 count += sysfs_emit_at(buf, count, "\n");
2885 return count;
2886 }
2887
2888 static int
2889 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2890 enum ptp_ocp_sma_mode *mode)
2891 {
2892 int idx, count, dir;
2893 char **argv;
2894 int ret;
2895
2896 argv = argv_split(GFP_KERNEL, buf, &count);
2897 if (!argv)
2898 return -ENOMEM;
2899
2900 ret = -EINVAL;
2901 if (!count)
2902 goto out;
2903
2904 idx = 0;
2905 dir = *mode == SMA_MODE_IN ? 0 : 1;
2906 if (!strcasecmp("IN:", argv[0])) {
2907 dir = 0;
2908 idx++;
2909 }
2910 if (!strcasecmp("OUT:", argv[0])) {
2911 dir = 1;
2912 idx++;
2913 }
2914 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2915
2916 ret = 0;
2917 for (; idx < count; idx++)
2918 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2919 if (ret < 0)
2920 ret = -EINVAL;
2921
2922 out:
2923 argv_free(argv);
2924 return ret;
2925 }
2926
2927 static ssize_t
2928 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2929 int default_in_val, int default_out_val)
2930 {
2931 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2932 const struct ocp_selector * const *tbl;
2933 u32 val;
2934
2935 tbl = bp->sma_op->tbl;
2936 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2937
2938 if (sma->mode == SMA_MODE_IN) {
2939 if (sma->disabled)
2940 val = SMA_DISABLE;
2941 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2942 }
2943
2944 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2945 }
2946
2947 static ssize_t
2948 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2949 {
2950 struct ptp_ocp *bp = dev_get_drvdata(dev);
2951
2952 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2953 }
2954
2955 static ssize_t
2956 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2957 {
2958 struct ptp_ocp *bp = dev_get_drvdata(dev);
2959
2960 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2961 }
2962
2963 static ssize_t
2964 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2965 {
2966 struct ptp_ocp *bp = dev_get_drvdata(dev);
2967
2968 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2969 }
2970
2971 static ssize_t
2972 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2973 {
2974 struct ptp_ocp *bp = dev_get_drvdata(dev);
2975
2976 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2977 }
2978
2979 static int
2980 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
2981 {
2982 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2983
2984 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
2985 return -EOPNOTSUPP;
2986
2987 if (sma->fixed_fcn) {
2988 if (val != sma->default_fcn)
2989 return -EOPNOTSUPP;
2990 return 0;
2991 }
2992
2993 sma->disabled = !!(val & SMA_DISABLE);
2994
2995 if (mode != sma->mode) {
2996 if (mode == SMA_MODE_IN)
2997 ptp_ocp_sma_set_output(bp, sma_nr, 0);
2998 else
2999 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3000 sma->mode = mode;
3001 }
3002
3003 if (!sma->fixed_dir)
3004 val |= SMA_ENABLE; /* add enable bit */
3005
3006 if (sma->disabled)
3007 val = 0;
3008
3009 if (mode == SMA_MODE_IN)
3010 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3011 else
3012 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3013
3014 return val;
3015 }
3016
3017 static int
3018 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3019 {
3020 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3021 enum ptp_ocp_sma_mode mode;
3022 int val;
3023
3024 mode = sma->mode;
3025 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3026 if (val < 0)
3027 return val;
3028 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3029 }
3030
3031 static ssize_t
3032 sma1_store(struct device *dev, struct device_attribute *attr,
3033 const char *buf, size_t count)
3034 {
3035 struct ptp_ocp *bp = dev_get_drvdata(dev);
3036 int err;
3037
3038 err = ptp_ocp_sma_store(bp, buf, 1);
3039 return err ? err : count;
3040 }
3041
3042 static ssize_t
3043 sma2_store(struct device *dev, struct device_attribute *attr,
3044 const char *buf, size_t count)
3045 {
3046 struct ptp_ocp *bp = dev_get_drvdata(dev);
3047 int err;
3048
3049 err = ptp_ocp_sma_store(bp, buf, 2);
3050 return err ? err : count;
3051 }
3052
3053 static ssize_t
3054 sma3_store(struct device *dev, struct device_attribute *attr,
3055 const char *buf, size_t count)
3056 {
3057 struct ptp_ocp *bp = dev_get_drvdata(dev);
3058 int err;
3059
3060 err = ptp_ocp_sma_store(bp, buf, 3);
3061 return err ? err : count;
3062 }
3063
3064 static ssize_t
3065 sma4_store(struct device *dev, struct device_attribute *attr,
3066 const char *buf, size_t count)
3067 {
3068 struct ptp_ocp *bp = dev_get_drvdata(dev);
3069 int err;
3070
3071 err = ptp_ocp_sma_store(bp, buf, 4);
3072 return err ? err : count;
3073 }
3074 static DEVICE_ATTR_RW(sma1);
3075 static DEVICE_ATTR_RW(sma2);
3076 static DEVICE_ATTR_RW(sma3);
3077 static DEVICE_ATTR_RW(sma4);
3078
3079 static ssize_t
3080 available_sma_inputs_show(struct device *dev,
3081 struct device_attribute *attr, char *buf)
3082 {
3083 struct ptp_ocp *bp = dev_get_drvdata(dev);
3084
3085 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3086 }
3087 static DEVICE_ATTR_RO(available_sma_inputs);
3088
3089 static ssize_t
3090 available_sma_outputs_show(struct device *dev,
3091 struct device_attribute *attr, char *buf)
3092 {
3093 struct ptp_ocp *bp = dev_get_drvdata(dev);
3094
3095 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3096 }
3097 static DEVICE_ATTR_RO(available_sma_outputs);
3098
3099 #define EXT_ATTR_RO(_group, _name, _val) \
3100 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3101 { __ATTR_RO(_name), (void *)_val }
3102 #define EXT_ATTR_RW(_group, _name, _val) \
3103 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3104 { __ATTR_RW(_name), (void *)_val }
3105 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3106
3107 /* period [duty [phase [polarity]]] */
3108 static ssize_t
3109 signal_store(struct device *dev, struct device_attribute *attr,
3110 const char *buf, size_t count)
3111 {
3112 struct dev_ext_attribute *ea = to_ext_attr(attr);
3113 struct ptp_ocp *bp = dev_get_drvdata(dev);
3114 struct ptp_ocp_signal s = { };
3115 int gen = (uintptr_t)ea->var;
3116 int argc, err;
3117 char **argv;
3118
3119 argv = argv_split(GFP_KERNEL, buf, &argc);
3120 if (!argv)
3121 return -ENOMEM;
3122
3123 err = -EINVAL;
3124 s.duty = bp->signal[gen].duty;
3125 s.phase = bp->signal[gen].phase;
3126 s.period = bp->signal[gen].period;
3127 s.polarity = bp->signal[gen].polarity;
3128
3129 switch (argc) {
3130 case 4:
3131 argc--;
3132 err = kstrtobool(argv[argc], &s.polarity);
3133 if (err)
3134 goto out;
3135 fallthrough;
3136 case 3:
3137 argc--;
3138 err = kstrtou64(argv[argc], 0, &s.phase);
3139 if (err)
3140 goto out;
3141 fallthrough;
3142 case 2:
3143 argc--;
3144 err = kstrtoint(argv[argc], 0, &s.duty);
3145 if (err)
3146 goto out;
3147 fallthrough;
3148 case 1:
3149 argc--;
3150 err = kstrtou64(argv[argc], 0, &s.period);
3151 if (err)
3152 goto out;
3153 break;
3154 default:
3155 goto out;
3156 }
3157
3158 err = ptp_ocp_signal_set(bp, gen, &s);
3159 if (err)
3160 goto out;
3161
3162 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3163
3164 out:
3165 argv_free(argv);
3166 return err ? err : count;
3167 }
3168
3169 static ssize_t
3170 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3171 {
3172 struct dev_ext_attribute *ea = to_ext_attr(attr);
3173 struct ptp_ocp *bp = dev_get_drvdata(dev);
3174 struct ptp_ocp_signal *signal;
3175 struct timespec64 ts;
3176 ssize_t count;
3177 int i;
3178
3179 i = (uintptr_t)ea->var;
3180 signal = &bp->signal[i];
3181
3182 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3183 signal->duty, signal->phase, signal->polarity);
3184
3185 ts = ktime_to_timespec64(signal->start);
3186 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3187
3188 return count;
3189 }
3190 static EXT_ATTR_RW(signal, signal, 0);
3191 static EXT_ATTR_RW(signal, signal, 1);
3192 static EXT_ATTR_RW(signal, signal, 2);
3193 static EXT_ATTR_RW(signal, signal, 3);
3194
3195 static ssize_t
3196 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3197 {
3198 struct dev_ext_attribute *ea = to_ext_attr(attr);
3199 struct ptp_ocp *bp = dev_get_drvdata(dev);
3200 int i = (uintptr_t)ea->var;
3201
3202 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3203 }
3204 static EXT_ATTR_RO(signal, duty, 0);
3205 static EXT_ATTR_RO(signal, duty, 1);
3206 static EXT_ATTR_RO(signal, duty, 2);
3207 static EXT_ATTR_RO(signal, duty, 3);
3208
3209 static ssize_t
3210 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3211 {
3212 struct dev_ext_attribute *ea = to_ext_attr(attr);
3213 struct ptp_ocp *bp = dev_get_drvdata(dev);
3214 int i = (uintptr_t)ea->var;
3215
3216 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3217 }
3218 static EXT_ATTR_RO(signal, period, 0);
3219 static EXT_ATTR_RO(signal, period, 1);
3220 static EXT_ATTR_RO(signal, period, 2);
3221 static EXT_ATTR_RO(signal, period, 3);
3222
3223 static ssize_t
3224 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3225 {
3226 struct dev_ext_attribute *ea = to_ext_attr(attr);
3227 struct ptp_ocp *bp = dev_get_drvdata(dev);
3228 int i = (uintptr_t)ea->var;
3229
3230 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3231 }
3232 static EXT_ATTR_RO(signal, phase, 0);
3233 static EXT_ATTR_RO(signal, phase, 1);
3234 static EXT_ATTR_RO(signal, phase, 2);
3235 static EXT_ATTR_RO(signal, phase, 3);
3236
3237 static ssize_t
3238 polarity_show(struct device *dev, struct device_attribute *attr,
3239 char *buf)
3240 {
3241 struct dev_ext_attribute *ea = to_ext_attr(attr);
3242 struct ptp_ocp *bp = dev_get_drvdata(dev);
3243 int i = (uintptr_t)ea->var;
3244
3245 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3246 }
3247 static EXT_ATTR_RO(signal, polarity, 0);
3248 static EXT_ATTR_RO(signal, polarity, 1);
3249 static EXT_ATTR_RO(signal, polarity, 2);
3250 static EXT_ATTR_RO(signal, polarity, 3);
3251
3252 static ssize_t
3253 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3254 {
3255 struct dev_ext_attribute *ea = to_ext_attr(attr);
3256 struct ptp_ocp *bp = dev_get_drvdata(dev);
3257 int i = (uintptr_t)ea->var;
3258
3259 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3260 }
3261 static EXT_ATTR_RO(signal, running, 0);
3262 static EXT_ATTR_RO(signal, running, 1);
3263 static EXT_ATTR_RO(signal, running, 2);
3264 static EXT_ATTR_RO(signal, running, 3);
3265
3266 static ssize_t
3267 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3268 {
3269 struct dev_ext_attribute *ea = to_ext_attr(attr);
3270 struct ptp_ocp *bp = dev_get_drvdata(dev);
3271 int i = (uintptr_t)ea->var;
3272 struct timespec64 ts;
3273
3274 ts = ktime_to_timespec64(bp->signal[i].start);
3275 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3276 }
3277 static EXT_ATTR_RO(signal, start, 0);
3278 static EXT_ATTR_RO(signal, start, 1);
3279 static EXT_ATTR_RO(signal, start, 2);
3280 static EXT_ATTR_RO(signal, start, 3);
3281
3282 static ssize_t
3283 seconds_store(struct device *dev, struct device_attribute *attr,
3284 const char *buf, size_t count)
3285 {
3286 struct dev_ext_attribute *ea = to_ext_attr(attr);
3287 struct ptp_ocp *bp = dev_get_drvdata(dev);
3288 int idx = (uintptr_t)ea->var;
3289 u32 val;
3290 int err;
3291
3292 err = kstrtou32(buf, 0, &val);
3293 if (err)
3294 return err;
3295 if (val > 0xff)
3296 return -EINVAL;
3297
3298 if (val)
3299 val = (val << 8) | 0x1;
3300
3301 iowrite32(val, &bp->freq_in[idx]->ctrl);
3302
3303 return count;
3304 }
3305
3306 static ssize_t
3307 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3308 {
3309 struct dev_ext_attribute *ea = to_ext_attr(attr);
3310 struct ptp_ocp *bp = dev_get_drvdata(dev);
3311 int idx = (uintptr_t)ea->var;
3312 u32 val;
3313
3314 val = ioread32(&bp->freq_in[idx]->ctrl);
3315 if (val & 1)
3316 val = (val >> 8) & 0xff;
3317 else
3318 val = 0;
3319
3320 return sysfs_emit(buf, "%u\n", val);
3321 }
3322 static EXT_ATTR_RW(freq, seconds, 0);
3323 static EXT_ATTR_RW(freq, seconds, 1);
3324 static EXT_ATTR_RW(freq, seconds, 2);
3325 static EXT_ATTR_RW(freq, seconds, 3);
3326
3327 static ssize_t
3328 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3329 {
3330 struct dev_ext_attribute *ea = to_ext_attr(attr);
3331 struct ptp_ocp *bp = dev_get_drvdata(dev);
3332 int idx = (uintptr_t)ea->var;
3333 u32 val;
3334
3335 val = ioread32(&bp->freq_in[idx]->status);
3336 if (val & FREQ_STATUS_ERROR)
3337 return sysfs_emit(buf, "error\n");
3338 if (val & FREQ_STATUS_OVERRUN)
3339 return sysfs_emit(buf, "overrun\n");
3340 if (val & FREQ_STATUS_VALID)
3341 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3342 return 0;
3343 }
3344 static EXT_ATTR_RO(freq, frequency, 0);
3345 static EXT_ATTR_RO(freq, frequency, 1);
3346 static EXT_ATTR_RO(freq, frequency, 2);
3347 static EXT_ATTR_RO(freq, frequency, 3);
3348
3349 static ssize_t
3350 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3351 {
3352 struct ptp_ocp *bp = dev_get_drvdata(dev);
3353
3354 if (!bp->has_eeprom_data)
3355 ptp_ocp_read_eeprom(bp);
3356
3357 return sysfs_emit(buf, "%pM\n", bp->serial);
3358 }
3359 static DEVICE_ATTR_RO(serialnum);
3360
3361 static ssize_t
3362 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3363 {
3364 struct ptp_ocp *bp = dev_get_drvdata(dev);
3365 ssize_t ret;
3366
3367 if (bp->gnss_lost)
3368 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3369 else
3370 ret = sysfs_emit(buf, "SYNC\n");
3371
3372 return ret;
3373 }
3374 static DEVICE_ATTR_RO(gnss_sync);
3375
3376 static ssize_t
3377 utc_tai_offset_show(struct device *dev,
3378 struct device_attribute *attr, char *buf)
3379 {
3380 struct ptp_ocp *bp = dev_get_drvdata(dev);
3381
3382 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3383 }
3384
3385 static ssize_t
3386 utc_tai_offset_store(struct device *dev,
3387 struct device_attribute *attr,
3388 const char *buf, size_t count)
3389 {
3390 struct ptp_ocp *bp = dev_get_drvdata(dev);
3391 int err;
3392 u32 val;
3393
3394 err = kstrtou32(buf, 0, &val);
3395 if (err)
3396 return err;
3397
3398 ptp_ocp_utc_distribute(bp, val);
3399
3400 return count;
3401 }
3402 static DEVICE_ATTR_RW(utc_tai_offset);
3403
3404 static ssize_t
3405 ts_window_adjust_show(struct device *dev,
3406 struct device_attribute *attr, char *buf)
3407 {
3408 struct ptp_ocp *bp = dev_get_drvdata(dev);
3409
3410 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3411 }
3412
3413 static ssize_t
3414 ts_window_adjust_store(struct device *dev,
3415 struct device_attribute *attr,
3416 const char *buf, size_t count)
3417 {
3418 struct ptp_ocp *bp = dev_get_drvdata(dev);
3419 int err;
3420 u32 val;
3421
3422 err = kstrtou32(buf, 0, &val);
3423 if (err)
3424 return err;
3425
3426 bp->ts_window_adjust = val;
3427
3428 return count;
3429 }
3430 static DEVICE_ATTR_RW(ts_window_adjust);
3431
3432 static ssize_t
3433 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3434 {
3435 struct ptp_ocp *bp = dev_get_drvdata(dev);
3436 u32 val;
3437
3438 val = ioread32(&bp->irig_out->ctrl);
3439 val = (val >> 16) & 0x07;
3440 return sysfs_emit(buf, "%d\n", val);
3441 }
3442
3443 static ssize_t
3444 irig_b_mode_store(struct device *dev,
3445 struct device_attribute *attr,
3446 const char *buf, size_t count)
3447 {
3448 struct ptp_ocp *bp = dev_get_drvdata(dev);
3449 unsigned long flags;
3450 int err;
3451 u32 reg;
3452 u8 val;
3453
3454 err = kstrtou8(buf, 0, &val);
3455 if (err)
3456 return err;
3457 if (val > 7)
3458 return -EINVAL;
3459
3460 reg = ((val & 0x7) << 16);
3461
3462 spin_lock_irqsave(&bp->lock, flags);
3463 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3464 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3465 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3466 spin_unlock_irqrestore(&bp->lock, flags);
3467
3468 return count;
3469 }
3470 static DEVICE_ATTR_RW(irig_b_mode);
3471
3472 static ssize_t
3473 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3474 {
3475 struct ptp_ocp *bp = dev_get_drvdata(dev);
3476 const char *p;
3477 u32 select;
3478
3479 select = ioread32(&bp->reg->select);
3480 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3481
3482 return sysfs_emit(buf, "%s\n", p);
3483 }
3484
3485 static ssize_t
3486 clock_source_store(struct device *dev, struct device_attribute *attr,
3487 const char *buf, size_t count)
3488 {
3489 struct ptp_ocp *bp = dev_get_drvdata(dev);
3490 unsigned long flags;
3491 int val;
3492
3493 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3494 if (val < 0)
3495 return val;
3496
3497 spin_lock_irqsave(&bp->lock, flags);
3498 iowrite32(val, &bp->reg->select);
3499 spin_unlock_irqrestore(&bp->lock, flags);
3500
3501 return count;
3502 }
3503 static DEVICE_ATTR_RW(clock_source);
3504
3505 static ssize_t
3506 available_clock_sources_show(struct device *dev,
3507 struct device_attribute *attr, char *buf)
3508 {
3509 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3510 }
3511 static DEVICE_ATTR_RO(available_clock_sources);
3512
3513 static ssize_t
3514 clock_status_drift_show(struct device *dev,
3515 struct device_attribute *attr, char *buf)
3516 {
3517 struct ptp_ocp *bp = dev_get_drvdata(dev);
3518 u32 val;
3519 int res;
3520
3521 val = ioread32(&bp->reg->status_drift);
3522 res = (val & ~INT_MAX) ? -1 : 1;
3523 res *= (val & INT_MAX);
3524 return sysfs_emit(buf, "%d\n", res);
3525 }
3526 static DEVICE_ATTR_RO(clock_status_drift);
3527
3528 static ssize_t
3529 clock_status_offset_show(struct device *dev,
3530 struct device_attribute *attr, char *buf)
3531 {
3532 struct ptp_ocp *bp = dev_get_drvdata(dev);
3533 u32 val;
3534 int res;
3535
3536 val = ioread32(&bp->reg->status_offset);
3537 res = (val & ~INT_MAX) ? -1 : 1;
3538 res *= (val & INT_MAX);
3539 return sysfs_emit(buf, "%d\n", res);
3540 }
3541 static DEVICE_ATTR_RO(clock_status_offset);
3542
3543 static ssize_t
3544 tod_correction_show(struct device *dev,
3545 struct device_attribute *attr, char *buf)
3546 {
3547 struct ptp_ocp *bp = dev_get_drvdata(dev);
3548 u32 val;
3549 int res;
3550
3551 val = ioread32(&bp->tod->adj_sec);
3552 res = (val & ~INT_MAX) ? -1 : 1;
3553 res *= (val & INT_MAX);
3554 return sysfs_emit(buf, "%d\n", res);
3555 }
3556
3557 static ssize_t
3558 tod_correction_store(struct device *dev, struct device_attribute *attr,
3559 const char *buf, size_t count)
3560 {
3561 struct ptp_ocp *bp = dev_get_drvdata(dev);
3562 unsigned long flags;
3563 int err, res;
3564 u32 val = 0;
3565
3566 err = kstrtos32(buf, 0, &res);
3567 if (err)
3568 return err;
3569 if (res < 0) {
3570 res *= -1;
3571 val |= BIT(31);
3572 }
3573 val |= res;
3574
3575 spin_lock_irqsave(&bp->lock, flags);
3576 iowrite32(val, &bp->tod->adj_sec);
3577 spin_unlock_irqrestore(&bp->lock, flags);
3578
3579 return count;
3580 }
3581 static DEVICE_ATTR_RW(tod_correction);
3582
3583 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3584 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3585 &dev_attr_signal##_nr##_signal.attr.attr, \
3586 &dev_attr_signal##_nr##_duty.attr.attr, \
3587 &dev_attr_signal##_nr##_phase.attr.attr, \
3588 &dev_attr_signal##_nr##_period.attr.attr, \
3589 &dev_attr_signal##_nr##_polarity.attr.attr, \
3590 &dev_attr_signal##_nr##_running.attr.attr, \
3591 &dev_attr_signal##_nr##_start.attr.attr, \
3592 NULL, \
3593 }
3594
3595 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3596 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3597 static const struct attribute_group \
3598 fb_timecard_signal##_nr##_group = { \
3599 .name = #_name, \
3600 .attrs = fb_timecard_signal##_nr##_attrs, \
3601 }
3602
3603 DEVICE_SIGNAL_GROUP(gen1, 0);
3604 DEVICE_SIGNAL_GROUP(gen2, 1);
3605 DEVICE_SIGNAL_GROUP(gen3, 2);
3606 DEVICE_SIGNAL_GROUP(gen4, 3);
3607
3608 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3609 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3610 &dev_attr_freq##_nr##_seconds.attr.attr, \
3611 &dev_attr_freq##_nr##_frequency.attr.attr, \
3612 NULL, \
3613 }
3614
3615 #define DEVICE_FREQ_GROUP(_name, _nr) \
3616 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3617 static const struct attribute_group \
3618 fb_timecard_freq##_nr##_group = { \
3619 .name = #_name, \
3620 .attrs = fb_timecard_freq##_nr##_attrs, \
3621 }
3622
3623 DEVICE_FREQ_GROUP(freq1, 0);
3624 DEVICE_FREQ_GROUP(freq2, 1);
3625 DEVICE_FREQ_GROUP(freq3, 2);
3626 DEVICE_FREQ_GROUP(freq4, 3);
3627
3628 static ssize_t
3629 disciplining_config_read(struct file *filp, struct kobject *kobj,
3630 struct bin_attribute *bin_attr, char *buf,
3631 loff_t off, size_t count)
3632 {
3633 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3634 size_t size = OCP_ART_CONFIG_SIZE;
3635 struct nvmem_device *nvmem;
3636 ssize_t err;
3637
3638 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3639 if (IS_ERR(nvmem))
3640 return PTR_ERR(nvmem);
3641
3642 if (off > size) {
3643 err = 0;
3644 goto out;
3645 }
3646
3647 if (off + count > size)
3648 count = size - off;
3649
3650 // the configuration is in the very beginning of the EEPROM
3651 err = nvmem_device_read(nvmem, off, count, buf);
3652 if (err != count) {
3653 err = -EFAULT;
3654 goto out;
3655 }
3656
3657 out:
3658 ptp_ocp_nvmem_device_put(&nvmem);
3659
3660 return err;
3661 }
3662
3663 static ssize_t
3664 disciplining_config_write(struct file *filp, struct kobject *kobj,
3665 struct bin_attribute *bin_attr, char *buf,
3666 loff_t off, size_t count)
3667 {
3668 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3669 struct nvmem_device *nvmem;
3670 ssize_t err;
3671
3672 /* Allow write of the whole area only */
3673 if (off || count != OCP_ART_CONFIG_SIZE)
3674 return -EFAULT;
3675
3676 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3677 if (IS_ERR(nvmem))
3678 return PTR_ERR(nvmem);
3679
3680 err = nvmem_device_write(nvmem, 0x00, count, buf);
3681 if (err != count)
3682 err = -EFAULT;
3683
3684 ptp_ocp_nvmem_device_put(&nvmem);
3685
3686 return err;
3687 }
3688 static BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3689
3690 static ssize_t
3691 temperature_table_read(struct file *filp, struct kobject *kobj,
3692 struct bin_attribute *bin_attr, char *buf,
3693 loff_t off, size_t count)
3694 {
3695 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3696 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3697 struct nvmem_device *nvmem;
3698 ssize_t err;
3699
3700 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3701 if (IS_ERR(nvmem))
3702 return PTR_ERR(nvmem);
3703
3704 if (off > size) {
3705 err = 0;
3706 goto out;
3707 }
3708
3709 if (off + count > size)
3710 count = size - off;
3711
3712 // the configuration is in the very beginning of the EEPROM
3713 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3714 if (err != count) {
3715 err = -EFAULT;
3716 goto out;
3717 }
3718
3719 out:
3720 ptp_ocp_nvmem_device_put(&nvmem);
3721
3722 return err;
3723 }
3724
3725 static ssize_t
3726 temperature_table_write(struct file *filp, struct kobject *kobj,
3727 struct bin_attribute *bin_attr, char *buf,
3728 loff_t off, size_t count)
3729 {
3730 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3731 struct nvmem_device *nvmem;
3732 ssize_t err;
3733
3734 /* Allow write of the whole area only */
3735 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3736 return -EFAULT;
3737
3738 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3739 if (IS_ERR(nvmem))
3740 return PTR_ERR(nvmem);
3741
3742 err = nvmem_device_write(nvmem, 0x90, count, buf);
3743 if (err != count)
3744 err = -EFAULT;
3745
3746 ptp_ocp_nvmem_device_put(&nvmem);
3747
3748 return err;
3749 }
3750 static BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3751
3752 static struct attribute *fb_timecard_attrs[] = {
3753 &dev_attr_serialnum.attr,
3754 &dev_attr_gnss_sync.attr,
3755 &dev_attr_clock_source.attr,
3756 &dev_attr_available_clock_sources.attr,
3757 &dev_attr_sma1.attr,
3758 &dev_attr_sma2.attr,
3759 &dev_attr_sma3.attr,
3760 &dev_attr_sma4.attr,
3761 &dev_attr_available_sma_inputs.attr,
3762 &dev_attr_available_sma_outputs.attr,
3763 &dev_attr_clock_status_drift.attr,
3764 &dev_attr_clock_status_offset.attr,
3765 &dev_attr_irig_b_mode.attr,
3766 &dev_attr_utc_tai_offset.attr,
3767 &dev_attr_ts_window_adjust.attr,
3768 &dev_attr_tod_correction.attr,
3769 NULL,
3770 };
3771
3772 static const struct attribute_group fb_timecard_group = {
3773 .attrs = fb_timecard_attrs,
3774 };
3775
3776 static const struct ocp_attr_group fb_timecard_groups[] = {
3777 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3778 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3779 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3780 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3781 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3782 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3783 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3784 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3785 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3786 { },
3787 };
3788
3789 static struct attribute *art_timecard_attrs[] = {
3790 &dev_attr_serialnum.attr,
3791 &dev_attr_clock_source.attr,
3792 &dev_attr_available_clock_sources.attr,
3793 &dev_attr_utc_tai_offset.attr,
3794 &dev_attr_ts_window_adjust.attr,
3795 &dev_attr_sma1.attr,
3796 &dev_attr_sma2.attr,
3797 &dev_attr_sma3.attr,
3798 &dev_attr_sma4.attr,
3799 &dev_attr_available_sma_inputs.attr,
3800 &dev_attr_available_sma_outputs.attr,
3801 NULL,
3802 };
3803
3804 static struct bin_attribute *bin_art_timecard_attrs[] = {
3805 &bin_attr_disciplining_config,
3806 &bin_attr_temperature_table,
3807 NULL,
3808 };
3809
3810 static const struct attribute_group art_timecard_group = {
3811 .attrs = art_timecard_attrs,
3812 .bin_attrs = bin_art_timecard_attrs,
3813 };
3814
3815 static const struct ocp_attr_group art_timecard_groups[] = {
3816 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3817 { },
3818 };
3819
3820 static struct attribute *adva_timecard_attrs[] = {
3821 &dev_attr_serialnum.attr,
3822 &dev_attr_gnss_sync.attr,
3823 &dev_attr_clock_source.attr,
3824 &dev_attr_available_clock_sources.attr,
3825 &dev_attr_sma1.attr,
3826 &dev_attr_sma2.attr,
3827 &dev_attr_sma3.attr,
3828 &dev_attr_sma4.attr,
3829 &dev_attr_available_sma_inputs.attr,
3830 &dev_attr_available_sma_outputs.attr,
3831 &dev_attr_clock_status_drift.attr,
3832 &dev_attr_clock_status_offset.attr,
3833 &dev_attr_ts_window_adjust.attr,
3834 &dev_attr_tod_correction.attr,
3835 NULL,
3836 };
3837
3838 static const struct attribute_group adva_timecard_group = {
3839 .attrs = adva_timecard_attrs,
3840 };
3841
3842 static const struct ocp_attr_group adva_timecard_groups[] = {
3843 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3844 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3845 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3846 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3847 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3848 { },
3849 };
3850
3851 static void
3852 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3853 const char *def)
3854 {
3855 int i;
3856
3857 for (i = 0; i < 4; i++) {
3858 if (bp->sma[i].mode != SMA_MODE_IN)
3859 continue;
3860 if (map[i][0] & (1 << bit)) {
3861 sprintf(buf, "sma%d", i + 1);
3862 return;
3863 }
3864 }
3865 if (!def)
3866 def = "----";
3867 strcpy(buf, def);
3868 }
3869
3870 static void
3871 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3872 {
3873 char *ans = buf;
3874 int i;
3875
3876 strcpy(ans, "----");
3877 for (i = 0; i < 4; i++) {
3878 if (bp->sma[i].mode != SMA_MODE_OUT)
3879 continue;
3880 if (map[i][1] & (1 << bit))
3881 ans += sprintf(ans, "sma%d ", i + 1);
3882 }
3883 }
3884
3885 static void
3886 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3887 {
3888 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3889 struct ptp_ocp_signal *signal = &bp->signal[nr];
3890 char label[8];
3891 bool on;
3892 u32 val;
3893
3894 if (!signal)
3895 return;
3896
3897 on = signal->running;
3898 sprintf(label, "GEN%d", nr + 1);
3899 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3900 label, on ? " ON" : "OFF",
3901 signal->period, signal->duty, signal->phase,
3902 signal->polarity);
3903
3904 val = ioread32(&reg->enable);
3905 seq_printf(s, " [%x", val);
3906 val = ioread32(&reg->status);
3907 seq_printf(s, " %x]", val);
3908
3909 seq_printf(s, " start:%llu\n", signal->start);
3910 }
3911
3912 static void
3913 _frequency_summary_show(struct seq_file *s, int nr,
3914 struct frequency_reg __iomem *reg)
3915 {
3916 char label[8];
3917 bool on;
3918 u32 val;
3919
3920 if (!reg)
3921 return;
3922
3923 sprintf(label, "FREQ%d", nr + 1);
3924 val = ioread32(&reg->ctrl);
3925 on = val & 1;
3926 val = (val >> 8) & 0xff;
3927 seq_printf(s, "%7s: %s, sec:%u",
3928 label,
3929 on ? " ON" : "OFF",
3930 val);
3931
3932 val = ioread32(&reg->status);
3933 if (val & FREQ_STATUS_ERROR)
3934 seq_printf(s, ", error");
3935 if (val & FREQ_STATUS_OVERRUN)
3936 seq_printf(s, ", overrun");
3937 if (val & FREQ_STATUS_VALID)
3938 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
3939 seq_printf(s, " reg:%x\n", val);
3940 }
3941
3942 static int
3943 ptp_ocp_summary_show(struct seq_file *s, void *data)
3944 {
3945 struct device *dev = s->private;
3946 struct ptp_system_timestamp sts;
3947 struct ts_reg __iomem *ts_reg;
3948 char *buf, *src, *mac_src;
3949 struct timespec64 ts;
3950 struct ptp_ocp *bp;
3951 u16 sma_val[4][2];
3952 u32 ctrl, val;
3953 bool on, map;
3954 int i;
3955
3956 buf = (char *)__get_free_page(GFP_KERNEL);
3957 if (!buf)
3958 return -ENOMEM;
3959
3960 bp = dev_get_drvdata(dev);
3961
3962 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
3963 if (bp->gnss_port.line != -1)
3964 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS1",
3965 bp->gnss_port.line);
3966 if (bp->gnss2_port.line != -1)
3967 seq_printf(s, "%7s: /dev/ttyS%d\n", "GNSS2",
3968 bp->gnss2_port.line);
3969 if (bp->mac_port.line != -1)
3970 seq_printf(s, "%7s: /dev/ttyS%d\n", "MAC", bp->mac_port.line);
3971 if (bp->nmea_port.line != -1)
3972 seq_printf(s, "%7s: /dev/ttyS%d\n", "NMEA", bp->nmea_port.line);
3973
3974 memset(sma_val, 0xff, sizeof(sma_val));
3975 if (bp->sma_map1) {
3976 u32 reg;
3977
3978 reg = ioread32(&bp->sma_map1->gpio1);
3979 sma_val[0][0] = reg & 0xffff;
3980 sma_val[1][0] = reg >> 16;
3981
3982 reg = ioread32(&bp->sma_map1->gpio2);
3983 sma_val[2][1] = reg & 0xffff;
3984 sma_val[3][1] = reg >> 16;
3985
3986 reg = ioread32(&bp->sma_map2->gpio1);
3987 sma_val[2][0] = reg & 0xffff;
3988 sma_val[3][0] = reg >> 16;
3989
3990 reg = ioread32(&bp->sma_map2->gpio2);
3991 sma_val[0][1] = reg & 0xffff;
3992 sma_val[1][1] = reg >> 16;
3993 }
3994
3995 sma1_show(dev, NULL, buf);
3996 seq_printf(s, " sma1: %04x,%04x %s",
3997 sma_val[0][0], sma_val[0][1], buf);
3998
3999 sma2_show(dev, NULL, buf);
4000 seq_printf(s, " sma2: %04x,%04x %s",
4001 sma_val[1][0], sma_val[1][1], buf);
4002
4003 sma3_show(dev, NULL, buf);
4004 seq_printf(s, " sma3: %04x,%04x %s",
4005 sma_val[2][0], sma_val[2][1], buf);
4006
4007 sma4_show(dev, NULL, buf);
4008 seq_printf(s, " sma4: %04x,%04x %s",
4009 sma_val[3][0], sma_val[3][1], buf);
4010
4011 if (bp->ts0) {
4012 ts_reg = bp->ts0->mem;
4013 on = ioread32(&ts_reg->enable);
4014 src = "GNSS1";
4015 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4016 on ? " ON" : "OFF", src);
4017 }
4018
4019 if (bp->ts1) {
4020 ts_reg = bp->ts1->mem;
4021 on = ioread32(&ts_reg->enable);
4022 gpio_input_map(buf, bp, sma_val, 2, NULL);
4023 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4024 on ? " ON" : "OFF", buf);
4025 }
4026
4027 if (bp->ts2) {
4028 ts_reg = bp->ts2->mem;
4029 on = ioread32(&ts_reg->enable);
4030 gpio_input_map(buf, bp, sma_val, 3, NULL);
4031 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4032 on ? " ON" : "OFF", buf);
4033 }
4034
4035 if (bp->ts3) {
4036 ts_reg = bp->ts3->mem;
4037 on = ioread32(&ts_reg->enable);
4038 gpio_input_map(buf, bp, sma_val, 6, NULL);
4039 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4040 on ? " ON" : "OFF", buf);
4041 }
4042
4043 if (bp->ts4) {
4044 ts_reg = bp->ts4->mem;
4045 on = ioread32(&ts_reg->enable);
4046 gpio_input_map(buf, bp, sma_val, 7, NULL);
4047 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4048 on ? " ON" : "OFF", buf);
4049 }
4050
4051 if (bp->pps) {
4052 ts_reg = bp->pps->mem;
4053 src = "PHC";
4054 on = ioread32(&ts_reg->enable);
4055 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4056 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4057 on && map ? " ON" : "OFF", src);
4058
4059 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4060 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4061 on && map ? " ON" : "OFF", src);
4062 }
4063
4064 if (bp->fw_cap & OCP_CAP_SIGNAL)
4065 for (i = 0; i < 4; i++)
4066 _signal_summary_show(s, bp, i);
4067
4068 if (bp->fw_cap & OCP_CAP_FREQ)
4069 for (i = 0; i < 4; i++)
4070 _frequency_summary_show(s, i, bp->freq_in[i]);
4071
4072 if (bp->irig_out) {
4073 ctrl = ioread32(&bp->irig_out->ctrl);
4074 on = ctrl & IRIG_M_CTRL_ENABLE;
4075 val = ioread32(&bp->irig_out->status);
4076 gpio_output_map(buf, bp, sma_val, 4);
4077 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4078 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4079 }
4080
4081 if (bp->irig_in) {
4082 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4083 val = ioread32(&bp->irig_in->status);
4084 gpio_input_map(buf, bp, sma_val, 4, NULL);
4085 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4086 on ? " ON" : "OFF", val, buf);
4087 }
4088
4089 if (bp->dcf_out) {
4090 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4091 val = ioread32(&bp->dcf_out->status);
4092 gpio_output_map(buf, bp, sma_val, 5);
4093 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4094 on ? " ON" : "OFF", val, buf);
4095 }
4096
4097 if (bp->dcf_in) {
4098 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4099 val = ioread32(&bp->dcf_in->status);
4100 gpio_input_map(buf, bp, sma_val, 5, NULL);
4101 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4102 on ? " ON" : "OFF", val, buf);
4103 }
4104
4105 if (bp->nmea_out) {
4106 on = ioread32(&bp->nmea_out->ctrl) & 1;
4107 val = ioread32(&bp->nmea_out->status);
4108 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4109 on ? " ON" : "OFF", val);
4110 }
4111
4112 /* compute src for PPS1, used below. */
4113 if (bp->pps_select) {
4114 val = ioread32(&bp->pps_select->gpio1);
4115 src = &buf[80];
4116 mac_src = "GNSS1";
4117 if (val & 0x01) {
4118 gpio_input_map(src, bp, sma_val, 0, NULL);
4119 mac_src = src;
4120 } else if (val & 0x02) {
4121 src = "MAC";
4122 } else if (val & 0x04) {
4123 src = "GNSS1";
4124 } else {
4125 src = "----";
4126 mac_src = src;
4127 }
4128 } else {
4129 src = "?";
4130 mac_src = src;
4131 }
4132 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4133
4134 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4135 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4136
4137 /* assumes automatic switchover/selection */
4138 val = ioread32(&bp->reg->select);
4139 switch (val >> 16) {
4140 case 0:
4141 sprintf(buf, "----");
4142 break;
4143 case 2:
4144 sprintf(buf, "IRIG");
4145 break;
4146 case 3:
4147 sprintf(buf, "%s via PPS1", src);
4148 break;
4149 case 6:
4150 sprintf(buf, "DCF");
4151 break;
4152 default:
4153 strcpy(buf, "unknown");
4154 break;
4155 }
4156 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4157 bp->sync ? "sync" : "unsynced");
4158
4159 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4160 struct timespec64 sys_ts;
4161 s64 pre_ns, post_ns, ns;
4162
4163 pre_ns = timespec64_to_ns(&sts.pre_ts);
4164 post_ns = timespec64_to_ns(&sts.post_ts);
4165 ns = (pre_ns + post_ns) / 2;
4166 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4167 sys_ts = ns_to_timespec64(ns);
4168
4169 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4170 ts.tv_sec, ts.tv_nsec, &ts);
4171 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4172 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4173 bp->utc_tai_offset);
4174 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4175 timespec64_to_ns(&ts) - ns,
4176 post_ns - pre_ns);
4177 }
4178
4179 free_page((unsigned long)buf);
4180 return 0;
4181 }
4182 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4183
4184 static int
4185 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4186 {
4187 struct device *dev = s->private;
4188 struct ptp_ocp *bp;
4189 u32 val;
4190 int idx;
4191
4192 bp = dev_get_drvdata(dev);
4193
4194 val = ioread32(&bp->tod->ctrl);
4195 if (!(val & TOD_CTRL_ENABLE)) {
4196 seq_printf(s, "TOD Slave disabled\n");
4197 return 0;
4198 }
4199 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4200
4201 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4202 idx += (val >> 16) & 3;
4203 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4204
4205 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4206 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4207
4208 val = ioread32(&bp->tod->version);
4209 seq_printf(s, "TOD Version %d.%d.%d\n",
4210 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4211
4212 val = ioread32(&bp->tod->status);
4213 seq_printf(s, "Status register: 0x%08X\n", val);
4214
4215 val = ioread32(&bp->tod->adj_sec);
4216 idx = (val & ~INT_MAX) ? -1 : 1;
4217 idx *= (val & INT_MAX);
4218 seq_printf(s, "Correction seconds: %d\n", idx);
4219
4220 val = ioread32(&bp->tod->utc_status);
4221 seq_printf(s, "UTC status register: 0x%08X\n", val);
4222 seq_printf(s, "UTC offset: %ld valid:%d\n",
4223 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4224 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4225 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4226 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4227
4228 val = ioread32(&bp->tod->leap);
4229 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4230
4231 return 0;
4232 }
4233 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4234
4235 static struct dentry *ptp_ocp_debugfs_root;
4236
4237 static void
4238 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4239 {
4240 struct dentry *d;
4241
4242 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4243 bp->debug_root = d;
4244 debugfs_create_file("summary", 0444, bp->debug_root,
4245 &bp->dev, &ptp_ocp_summary_fops);
4246 if (bp->tod)
4247 debugfs_create_file("tod_status", 0444, bp->debug_root,
4248 &bp->dev, &ptp_ocp_tod_status_fops);
4249 }
4250
4251 static void
4252 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4253 {
4254 debugfs_remove_recursive(bp->debug_root);
4255 }
4256
4257 static void
4258 ptp_ocp_debugfs_init(void)
4259 {
4260 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4261 }
4262
4263 static void
4264 ptp_ocp_debugfs_fini(void)
4265 {
4266 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4267 }
4268
4269 static void
4270 ptp_ocp_dev_release(struct device *dev)
4271 {
4272 struct ptp_ocp *bp = dev_get_drvdata(dev);
4273
4274 mutex_lock(&ptp_ocp_lock);
4275 idr_remove(&ptp_ocp_idr, bp->id);
4276 mutex_unlock(&ptp_ocp_lock);
4277 }
4278
4279 static int
4280 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4281 {
4282 int err;
4283
4284 mutex_lock(&ptp_ocp_lock);
4285 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4286 mutex_unlock(&ptp_ocp_lock);
4287 if (err < 0) {
4288 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4289 return err;
4290 }
4291 bp->id = err;
4292
4293 bp->ptp_info = ptp_ocp_clock_info;
4294 spin_lock_init(&bp->lock);
4295 bp->gnss_port.line = -1;
4296 bp->gnss2_port.line = -1;
4297 bp->mac_port.line = -1;
4298 bp->nmea_port.line = -1;
4299 bp->pdev = pdev;
4300
4301 device_initialize(&bp->dev);
4302 dev_set_name(&bp->dev, "ocp%d", bp->id);
4303 bp->dev.class = &timecard_class;
4304 bp->dev.parent = &pdev->dev;
4305 bp->dev.release = ptp_ocp_dev_release;
4306 dev_set_drvdata(&bp->dev, bp);
4307
4308 err = device_add(&bp->dev);
4309 if (err) {
4310 dev_err(&bp->dev, "device add failed: %d\n", err);
4311 goto out;
4312 }
4313
4314 pci_set_drvdata(pdev, bp);
4315
4316 return 0;
4317
4318 out:
4319 put_device(&bp->dev);
4320 return err;
4321 }
4322
4323 static void
4324 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4325 {
4326 struct device *dev = &bp->dev;
4327
4328 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4329 dev_err(dev, "%s symlink failed\n", link);
4330 }
4331
4332 static void
4333 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4334 {
4335 struct device *dev, *child;
4336
4337 dev = &bp->pdev->dev;
4338
4339 child = device_find_child_by_name(dev, name);
4340 if (!child) {
4341 dev_err(dev, "Could not find device %s\n", name);
4342 return;
4343 }
4344
4345 ptp_ocp_symlink(bp, child, link);
4346 put_device(child);
4347 }
4348
4349 static int
4350 ptp_ocp_complete(struct ptp_ocp *bp)
4351 {
4352 struct pps_device *pps;
4353 char buf[32];
4354
4355 if (bp->gnss_port.line != -1) {
4356 sprintf(buf, "ttyS%d", bp->gnss_port.line);
4357 ptp_ocp_link_child(bp, buf, "ttyGNSS");
4358 }
4359 if (bp->gnss2_port.line != -1) {
4360 sprintf(buf, "ttyS%d", bp->gnss2_port.line);
4361 ptp_ocp_link_child(bp, buf, "ttyGNSS2");
4362 }
4363 if (bp->mac_port.line != -1) {
4364 sprintf(buf, "ttyS%d", bp->mac_port.line);
4365 ptp_ocp_link_child(bp, buf, "ttyMAC");
4366 }
4367 if (bp->nmea_port.line != -1) {
4368 sprintf(buf, "ttyS%d", bp->nmea_port.line);
4369 ptp_ocp_link_child(bp, buf, "ttyNMEA");
4370 }
4371 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4372 ptp_ocp_link_child(bp, buf, "ptp");
4373
4374 pps = pps_lookup_dev(bp->ptp);
4375 if (pps)
4376 ptp_ocp_symlink(bp, pps->dev, "pps");
4377
4378 ptp_ocp_debugfs_add_device(bp);
4379
4380 return 0;
4381 }
4382
4383 static void
4384 ptp_ocp_phc_info(struct ptp_ocp *bp)
4385 {
4386 struct timespec64 ts;
4387 u32 version, select;
4388
4389 version = ioread32(&bp->reg->version);
4390 select = ioread32(&bp->reg->select);
4391 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4392 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4393 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4394 ptp_clock_index(bp->ptp));
4395
4396 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4397 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4398 ts.tv_sec, ts.tv_nsec,
4399 bp->sync ? "in-sync" : "UNSYNCED");
4400 }
4401
4402 static void
4403 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4404 {
4405 if (port != -1)
4406 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4407 }
4408
4409 static void
4410 ptp_ocp_info(struct ptp_ocp *bp)
4411 {
4412 static int nmea_baud[] = {
4413 1200, 2400, 4800, 9600, 19200, 38400,
4414 57600, 115200, 230400, 460800, 921600,
4415 1000000, 2000000
4416 };
4417 struct device *dev = &bp->pdev->dev;
4418 u32 reg;
4419
4420 ptp_ocp_phc_info(bp);
4421
4422 ptp_ocp_serial_info(dev, "GNSS", bp->gnss_port.line,
4423 bp->gnss_port.baud);
4424 ptp_ocp_serial_info(dev, "GNSS2", bp->gnss2_port.line,
4425 bp->gnss2_port.baud);
4426 ptp_ocp_serial_info(dev, "MAC", bp->mac_port.line, bp->mac_port.baud);
4427 if (bp->nmea_out && bp->nmea_port.line != -1) {
4428 bp->nmea_port.baud = -1;
4429
4430 reg = ioread32(&bp->nmea_out->uart_baud);
4431 if (reg < ARRAY_SIZE(nmea_baud))
4432 bp->nmea_port.baud = nmea_baud[reg];
4433
4434 ptp_ocp_serial_info(dev, "NMEA", bp->nmea_port.line,
4435 bp->nmea_port.baud);
4436 }
4437 }
4438
4439 static void
4440 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4441 {
4442 struct device *dev = &bp->dev;
4443
4444 sysfs_remove_link(&dev->kobj, "ttyGNSS");
4445 sysfs_remove_link(&dev->kobj, "ttyGNSS2");
4446 sysfs_remove_link(&dev->kobj, "ttyMAC");
4447 sysfs_remove_link(&dev->kobj, "ptp");
4448 sysfs_remove_link(&dev->kobj, "pps");
4449 }
4450
4451 static void
4452 ptp_ocp_detach(struct ptp_ocp *bp)
4453 {
4454 int i;
4455
4456 ptp_ocp_debugfs_remove_device(bp);
4457 ptp_ocp_detach_sysfs(bp);
4458 ptp_ocp_attr_group_del(bp);
4459 if (timer_pending(&bp->watchdog))
4460 del_timer_sync(&bp->watchdog);
4461 if (bp->ts0)
4462 ptp_ocp_unregister_ext(bp->ts0);
4463 if (bp->ts1)
4464 ptp_ocp_unregister_ext(bp->ts1);
4465 if (bp->ts2)
4466 ptp_ocp_unregister_ext(bp->ts2);
4467 if (bp->ts3)
4468 ptp_ocp_unregister_ext(bp->ts3);
4469 if (bp->ts4)
4470 ptp_ocp_unregister_ext(bp->ts4);
4471 if (bp->pps)
4472 ptp_ocp_unregister_ext(bp->pps);
4473 for (i = 0; i < 4; i++)
4474 if (bp->signal_out[i])
4475 ptp_ocp_unregister_ext(bp->signal_out[i]);
4476 if (bp->gnss_port.line != -1)
4477 serial8250_unregister_port(bp->gnss_port.line);
4478 if (bp->gnss2_port.line != -1)
4479 serial8250_unregister_port(bp->gnss2_port.line);
4480 if (bp->mac_port.line != -1)
4481 serial8250_unregister_port(bp->mac_port.line);
4482 if (bp->nmea_port.line != -1)
4483 serial8250_unregister_port(bp->nmea_port.line);
4484 platform_device_unregister(bp->spi_flash);
4485 platform_device_unregister(bp->i2c_ctrl);
4486 if (bp->i2c_clk)
4487 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4488 if (bp->n_irqs)
4489 pci_free_irq_vectors(bp->pdev);
4490 if (bp->ptp)
4491 ptp_clock_unregister(bp->ptp);
4492 kfree(bp->ptp_info.pin_config);
4493 device_unregister(&bp->dev);
4494 }
4495
4496 static int
4497 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4498 enum dpll_lock_status *status,
4499 enum dpll_lock_status_error *status_error,
4500 struct netlink_ext_ack *extack)
4501 {
4502 struct ptp_ocp *bp = priv;
4503
4504 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4505
4506 return 0;
4507 }
4508
4509 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4510 const struct dpll_device *dpll, void *priv,
4511 enum dpll_pin_state *state,
4512 struct netlink_ext_ack *extack)
4513 {
4514 struct ptp_ocp *bp = priv;
4515 int idx;
4516
4517 if (bp->pps_select) {
4518 idx = ioread32(&bp->pps_select->gpio1);
4519 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4520 DPLL_PIN_STATE_SELECTABLE;
4521 return 0;
4522 }
4523 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4524 return -EINVAL;
4525 }
4526
4527 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4528 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4529 {
4530 *mode = DPLL_MODE_AUTOMATIC;
4531 return 0;
4532 }
4533
4534 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4535 void *pin_priv,
4536 const struct dpll_device *dpll,
4537 void *priv,
4538 enum dpll_pin_direction *direction,
4539 struct netlink_ext_ack *extack)
4540 {
4541 struct ptp_ocp_sma_connector *sma = pin_priv;
4542
4543 *direction = sma->mode == SMA_MODE_IN ?
4544 DPLL_PIN_DIRECTION_INPUT :
4545 DPLL_PIN_DIRECTION_OUTPUT;
4546 return 0;
4547 }
4548
4549 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4550 void *pin_priv,
4551 const struct dpll_device *dpll,
4552 void *dpll_priv,
4553 enum dpll_pin_direction direction,
4554 struct netlink_ext_ack *extack)
4555 {
4556 struct ptp_ocp_sma_connector *sma = pin_priv;
4557 struct ptp_ocp *bp = dpll_priv;
4558 enum ptp_ocp_sma_mode mode;
4559 int sma_nr = (sma - bp->sma);
4560
4561 if (sma->fixed_dir)
4562 return -EOPNOTSUPP;
4563 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4564 SMA_MODE_IN : SMA_MODE_OUT;
4565 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr);
4566 }
4567
4568 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4569 void *pin_priv,
4570 const struct dpll_device *dpll,
4571 void *dpll_priv, u64 frequency,
4572 struct netlink_ext_ack *extack)
4573 {
4574 struct ptp_ocp_sma_connector *sma = pin_priv;
4575 struct ptp_ocp *bp = dpll_priv;
4576 const struct ocp_selector *tbl;
4577 int sma_nr = (sma - bp->sma);
4578 int i;
4579
4580 if (sma->fixed_fcn)
4581 return -EOPNOTSUPP;
4582
4583 tbl = bp->sma_op->tbl[sma->mode];
4584 for (i = 0; tbl[i].name; i++)
4585 if (tbl[i].frequency == frequency)
4586 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr);
4587 return -EINVAL;
4588 }
4589
4590 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4591 void *pin_priv,
4592 const struct dpll_device *dpll,
4593 void *dpll_priv, u64 *frequency,
4594 struct netlink_ext_ack *extack)
4595 {
4596 struct ptp_ocp_sma_connector *sma = pin_priv;
4597 struct ptp_ocp *bp = dpll_priv;
4598 const struct ocp_selector *tbl;
4599 int sma_nr = (sma - bp->sma);
4600 u32 val;
4601 int i;
4602
4603 val = bp->sma_op->get(bp, sma_nr);
4604 tbl = bp->sma_op->tbl[sma->mode];
4605 for (i = 0; tbl[i].name; i++)
4606 if (val == tbl[i].value) {
4607 *frequency = tbl[i].frequency;
4608 return 0;
4609 }
4610
4611 return -EINVAL;
4612 }
4613
4614 static const struct dpll_device_ops dpll_ops = {
4615 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4616 .mode_get = ptp_ocp_dpll_mode_get,
4617 };
4618
4619 static const struct dpll_pin_ops dpll_pins_ops = {
4620 .frequency_get = ptp_ocp_dpll_frequency_get,
4621 .frequency_set = ptp_ocp_dpll_frequency_set,
4622 .direction_get = ptp_ocp_dpll_direction_get,
4623 .direction_set = ptp_ocp_dpll_direction_set,
4624 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4625 };
4626
4627 static void
4628 ptp_ocp_sync_work(struct work_struct *work)
4629 {
4630 struct ptp_ocp *bp;
4631 bool sync;
4632
4633 bp = container_of(work, struct ptp_ocp, sync_work.work);
4634 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4635
4636 if (bp->sync != sync)
4637 dpll_device_change_ntf(bp->dpll);
4638
4639 bp->sync = sync;
4640
4641 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4642 }
4643
4644 static int
4645 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4646 {
4647 struct devlink *devlink;
4648 struct ptp_ocp *bp;
4649 int err, i;
4650 u64 clkid;
4651
4652 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4653 if (!devlink) {
4654 dev_err(&pdev->dev, "devlink_alloc failed\n");
4655 return -ENOMEM;
4656 }
4657
4658 err = pci_enable_device(pdev);
4659 if (err) {
4660 dev_err(&pdev->dev, "pci_enable_device\n");
4661 goto out_free;
4662 }
4663
4664 bp = devlink_priv(devlink);
4665 err = ptp_ocp_device_init(bp, pdev);
4666 if (err)
4667 goto out_disable;
4668
4669 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4670
4671 /* compat mode.
4672 * Older FPGA firmware only returns 2 irq's.
4673 * allow this - if not all of the IRQ's are returned, skip the
4674 * extra devices and just register the clock.
4675 */
4676 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4677 if (err < 0) {
4678 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4679 goto out;
4680 }
4681 bp->n_irqs = err;
4682 pci_set_master(pdev);
4683
4684 err = ptp_ocp_register_resources(bp, id->driver_data);
4685 if (err)
4686 goto out;
4687
4688 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4689 if (IS_ERR(bp->ptp)) {
4690 err = PTR_ERR(bp->ptp);
4691 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4692 bp->ptp = NULL;
4693 goto out;
4694 }
4695
4696 err = ptp_ocp_complete(bp);
4697 if (err)
4698 goto out;
4699
4700 ptp_ocp_info(bp);
4701 devlink_register(devlink);
4702
4703 clkid = pci_get_dsn(pdev);
4704 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4705 if (IS_ERR(bp->dpll)) {
4706 err = PTR_ERR(bp->dpll);
4707 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4708 goto out;
4709 }
4710
4711 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4712 if (err)
4713 goto out;
4714
4715 for (i = 0; i < OCP_SMA_NUM; i++) {
4716 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4717 if (IS_ERR(bp->sma[i].dpll_pin)) {
4718 err = PTR_ERR(bp->sma[i].dpll_pin);
4719 goto out_dpll;
4720 }
4721
4722 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4723 &bp->sma[i]);
4724 if (err) {
4725 dpll_pin_put(bp->sma[i].dpll_pin);
4726 goto out_dpll;
4727 }
4728 }
4729 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4730
4731 return 0;
4732 out_dpll:
4733 while (i) {
4734 --i;
4735 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4736 dpll_pin_put(bp->sma[i].dpll_pin);
4737 }
4738 dpll_device_put(bp->dpll);
4739 out:
4740 ptp_ocp_detach(bp);
4741 out_disable:
4742 pci_disable_device(pdev);
4743 out_free:
4744 devlink_free(devlink);
4745 return err;
4746 }
4747
4748 static void
4749 ptp_ocp_remove(struct pci_dev *pdev)
4750 {
4751 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4752 struct devlink *devlink = priv_to_devlink(bp);
4753 int i;
4754
4755 cancel_delayed_work_sync(&bp->sync_work);
4756 for (i = 0; i < OCP_SMA_NUM; i++) {
4757 if (bp->sma[i].dpll_pin) {
4758 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4759 dpll_pin_put(bp->sma[i].dpll_pin);
4760 }
4761 }
4762 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4763 dpll_device_put(bp->dpll);
4764 devlink_unregister(devlink);
4765 ptp_ocp_detach(bp);
4766 pci_disable_device(pdev);
4767
4768 devlink_free(devlink);
4769 }
4770
4771 static struct pci_driver ptp_ocp_driver = {
4772 .name = KBUILD_MODNAME,
4773 .id_table = ptp_ocp_pcidev_id,
4774 .probe = ptp_ocp_probe,
4775 .remove = ptp_ocp_remove,
4776 };
4777
4778 static int
4779 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4780 unsigned long action, void *data)
4781 {
4782 struct device *dev, *child = data;
4783 struct ptp_ocp *bp;
4784 bool add;
4785
4786 switch (action) {
4787 case BUS_NOTIFY_ADD_DEVICE:
4788 case BUS_NOTIFY_DEL_DEVICE:
4789 add = action == BUS_NOTIFY_ADD_DEVICE;
4790 break;
4791 default:
4792 return 0;
4793 }
4794
4795 if (!i2c_verify_adapter(child))
4796 return 0;
4797
4798 dev = child;
4799 while ((dev = dev->parent))
4800 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4801 goto found;
4802 return 0;
4803
4804 found:
4805 bp = dev_get_drvdata(dev);
4806 if (add)
4807 ptp_ocp_symlink(bp, child, "i2c");
4808 else
4809 sysfs_remove_link(&bp->dev.kobj, "i2c");
4810
4811 return 0;
4812 }
4813
4814 static struct notifier_block ptp_ocp_i2c_notifier = {
4815 .notifier_call = ptp_ocp_i2c_notifier_call,
4816 };
4817
4818 static int __init
4819 ptp_ocp_init(void)
4820 {
4821 const char *what;
4822 int err;
4823
4824 ptp_ocp_debugfs_init();
4825
4826 what = "timecard class";
4827 err = class_register(&timecard_class);
4828 if (err)
4829 goto out;
4830
4831 what = "i2c notifier";
4832 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4833 if (err)
4834 goto out_notifier;
4835
4836 what = "ptp_ocp driver";
4837 err = pci_register_driver(&ptp_ocp_driver);
4838 if (err)
4839 goto out_register;
4840
4841 return 0;
4842
4843 out_register:
4844 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4845 out_notifier:
4846 class_unregister(&timecard_class);
4847 out:
4848 ptp_ocp_debugfs_fini();
4849 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4850 return err;
4851 }
4852
4853 static void __exit
4854 ptp_ocp_fini(void)
4855 {
4856 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4857 pci_unregister_driver(&ptp_ocp_driver);
4858 class_unregister(&timecard_class);
4859 ptp_ocp_debugfs_fini();
4860 }
4861
4862 module_init(ptp_ocp_init);
4863 module_exit(ptp_ocp_fini);
4864
4865 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4866 MODULE_LICENSE("GPL v2");
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