2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define QE_NUM_OF_SNUM 28
29 #define QE_NUM_OF_BRGS 16
32 #define QE_DATAONLY_BASE 0
33 #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE)
37 typedef enum qe_snum_state
{
38 QE_SNUM_STATE_USED
, /* used */
39 QE_SNUM_STATE_FREE
/* free */
42 typedef struct qe_snum
{
44 qe_snum_state_e state
; /* state */
49 typedef enum qe_risc_allocation
{
50 QE_RISC_ALLOCATION_RISC1
= 1, /* RISC 1 */
51 QE_RISC_ALLOCATION_RISC2
= 2, /* RISC 2 */
52 QE_RISC_ALLOCATION_RISC1_AND_RISC2
= 3 /* RISC 1 or RISC 2 */
53 } qe_risc_allocation_e
;
55 /* QE CECR commands for UCC fast.
57 #define QE_CR_FLG 0x00010000
58 #define QE_RESET 0x80000000
59 #define QE_INIT_TX_RX 0x00000000
60 #define QE_INIT_RX 0x00000001
61 #define QE_INIT_TX 0x00000002
62 #define QE_ENTER_HUNT_MODE 0x00000003
63 #define QE_STOP_TX 0x00000004
64 #define QE_GRACEFUL_STOP_TX 0x00000005
65 #define QE_RESTART_TX 0x00000006
66 #define QE_SWITCH_COMMAND 0x00000007
67 #define QE_SET_GROUP_ADDRESS 0x00000008
68 #define QE_INSERT_CELL 0x00000009
69 #define QE_ATM_TRANSMIT 0x0000000a
70 #define QE_CELL_POOL_GET 0x0000000b
71 #define QE_CELL_POOL_PUT 0x0000000c
72 #define QE_IMA_HOST_CMD 0x0000000d
73 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
74 #define QE_ASSIGN_PAGE 0x00000012
75 #define QE_START_FLOW_CONTROL 0x00000014
76 #define QE_STOP_FLOW_CONTROL 0x00000015
77 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
78 #define QE_GRACEFUL_STOP_RX 0x0000001a
79 #define QE_RESTART_RX 0x0000001b
81 /* QE CECR Sub Block Code - sub block code of QE command.
83 #define QE_CR_SUBBLOCK_INVALID 0x00000000
84 #define QE_CR_SUBBLOCK_USB 0x03200000
85 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
86 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
87 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
88 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
89 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
90 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
91 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
92 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
93 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
94 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
95 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
96 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
97 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
98 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
99 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
100 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
101 #define QE_CR_SUBBLOCK_MCC1 0x03800000
102 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
103 #define QE_CR_SUBBLOCK_MCC3 0x03000000
104 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
105 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
106 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
107 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
108 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
109 #define QE_CR_SUBBLOCK_SPI1 0x01400000
110 #define QE_CR_SUBBLOCK_SPI2 0x01600000
111 #define QE_CR_SUBBLOCK_RAND 0x01c00000
112 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
113 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
115 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
117 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
118 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
119 #define QE_CR_PROTOCOL_ATM_POS 0x0A
120 #define QE_CR_PROTOCOL_ETHERNET 0x0C
121 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
122 #define QE_CR_PROTOCOL_SHIFT 6
124 /* QE ASSIGN PAGE command
126 #define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17
128 /* Communication Direction.
130 typedef enum comm_dir
{
134 COMM_DIR_RX_AND_TX
= 3
139 typedef enum qe_clock
{
141 QE_BRG1
, /* Baud Rate Generator 1 */
142 QE_BRG2
, /* Baud Rate Generator 2 */
143 QE_BRG3
, /* Baud Rate Generator 3 */
144 QE_BRG4
, /* Baud Rate Generator 4 */
145 QE_BRG5
, /* Baud Rate Generator 5 */
146 QE_BRG6
, /* Baud Rate Generator 6 */
147 QE_BRG7
, /* Baud Rate Generator 7 */
148 QE_BRG8
, /* Baud Rate Generator 8 */
149 QE_BRG9
, /* Baud Rate Generator 9 */
150 QE_BRG10
, /* Baud Rate Generator 10 */
151 QE_BRG11
, /* Baud Rate Generator 11 */
152 QE_BRG12
, /* Baud Rate Generator 12 */
153 QE_BRG13
, /* Baud Rate Generator 13 */
154 QE_BRG14
, /* Baud Rate Generator 14 */
155 QE_BRG15
, /* Baud Rate Generator 15 */
156 QE_BRG16
, /* Baud Rate Generator 16 */
157 QE_CLK1
, /* Clock 1 */
158 QE_CLK2
, /* Clock 2 */
159 QE_CLK3
, /* Clock 3 */
160 QE_CLK4
, /* Clock 4 */
161 QE_CLK5
, /* Clock 5 */
162 QE_CLK6
, /* Clock 6 */
163 QE_CLK7
, /* Clock 7 */
164 QE_CLK8
, /* Clock 8 */
165 QE_CLK9
, /* Clock 9 */
166 QE_CLK10
, /* Clock 10 */
167 QE_CLK11
, /* Clock 11 */
168 QE_CLK12
, /* Clock 12 */
169 QE_CLK13
, /* Clock 13 */
170 QE_CLK14
, /* Clock 14 */
171 QE_CLK15
, /* Clock 15 */
172 QE_CLK16
, /* Clock 16 */
173 QE_CLK17
, /* Clock 17 */
174 QE_CLK18
, /* Clock 18 */
175 QE_CLK19
, /* Clock 19 */
176 QE_CLK20
, /* Clock 20 */
177 QE_CLK21
, /* Clock 21 */
178 QE_CLK22
, /* Clock 22 */
179 QE_CLK23
, /* Clock 23 */
180 QE_CLK24
, /* Clock 24 */
184 /* QE CMXGCR register
186 #define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000
187 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
189 /* QE CMXUCR registers
191 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
193 /* QE BRG configuration register
195 #define QE_BRGC_ENABLE 0x00010000
196 #define QE_BRGC_DIVISOR_SHIFT 1
197 #define QE_BRGC_DIVISOR_MAX 0xFFF
198 #define QE_BRGC_DIV16 1
202 #define QE_SDSR_BER1 0x02000000
203 #define QE_SDSR_BER2 0x01000000
205 #define QE_SDMR_GLB_1_MSK 0x80000000
206 #define QE_SDMR_ADR_SEL 0x20000000
207 #define QE_SDMR_BER1_MSK 0x02000000
208 #define QE_SDMR_BER2_MSK 0x01000000
209 #define QE_SDMR_EB1_MSK 0x00800000
210 #define QE_SDMR_ER1_MSK 0x00080000
211 #define QE_SDMR_ER2_MSK 0x00040000
212 #define QE_SDMR_CEN_MASK 0x0000E000
213 #define QE_SDMR_SBER_1 0x00000200
214 #define QE_SDMR_SBER_2 0x00000200
215 #define QE_SDMR_EB1_PR_MASK 0x000000C0
216 #define QE_SDMR_ER1_PR 0x00000008
218 #define QE_SDMR_CEN_SHIFT 13
219 #define QE_SDMR_EB1_PR_SHIFT 6
221 #define QE_SDTM_MSNUM_SHIFT 24
223 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
225 /* Communication Processor */
226 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
227 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
228 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
231 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
232 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
233 #define QE_IRAM_READY 0x80000000
235 /* Structure that defines QE firmware binary files.
237 * See doc/README.qe_firmware for a description of these fields.
241 u32 length
; /* Length of the entire structure, in bytes */
242 u8 magic
[3]; /* Set to { 'Q', 'E', 'F' } */
243 u8 version
; /* Version of this layout. First ver is '1' */
245 u8 id
[62]; /* Null-terminated identifier string */
246 u8 split
; /* 0 = shared I-RAM, 1 = split I-RAM */
247 u8 count
; /* Number of microcode[] structures */
249 u16 model
; /* The SOC model */
250 u8 major
; /* The SOC revision major */
251 u8 minor
; /* The SOC revision minor */
252 } __attribute__ ((packed
)) soc
;
253 u8 padding
[4]; /* Reserved, for alignment */
254 u64 extended_modes
; /* Extended modes */
255 u32 vtraps
[8]; /* Virtual trap addresses */
256 u8 reserved
[4]; /* Reserved, for future expansion */
257 struct qe_microcode
{
258 u8 id
[32]; /* Null-terminated identifier */
259 u32 traps
[16]; /* Trap addresses, 0 == ignore */
260 u32 eccr
; /* The value for the ECCR register */
261 u32 iram_offset
;/* Offset into I-RAM for the code */
262 u32 count
; /* Number of 32-bit words of the code */
263 u32 code_offset
;/* Offset of the actual microcode */
264 u8 major
; /* The microcode version major */
265 u8 minor
; /* The microcode version minor */
266 u8 revision
; /* The microcode version revision */
267 u8 padding
; /* Reserved, for alignment */
268 u8 reserved
[4]; /* Reserved, for future expansion */
269 } __attribute__ ((packed
)) microcode
[1];
270 /* All microcode binaries should be located here */
271 /* CRC32 should be located here, after the microcode binaries */
272 } __attribute__ ((packed
));
274 struct qe_firmware_info
{
275 char id
[64]; /* Firmware name */
276 u32 vtraps
[8]; /* Virtual trap addresses */
277 u64 extended_modes
; /* Extended modes */
280 void qe_config_iopin(u8 port
, u8 pin
, int dir
, int open_drain
, int assign
);
281 void qe_issue_cmd(uint cmd
, uint sbc
, u8 mcn
, u32 cmd_data
);
282 uint
qe_muram_alloc(uint size
, uint align
);
283 void *qe_muram_addr(uint offset
);
284 int qe_get_snum(void);
285 void qe_put_snum(u8 snum
);
286 void qe_init(uint qe_base
);
288 void qe_assign_page(uint snum
, uint para_ram_base
);
289 int qe_set_brg(uint brg
, uint rate
);
290 int qe_set_mii_clk_src(int ucc_num
);
291 int qe_upload_firmware(const struct qe_firmware
*firmware
);
292 struct qe_firmware_info
*qe_get_firmware_info(void);
293 void ft_qe_setup(void *blob
);
295 #endif /* __QE_H__ */