drivers/qe/qe.h

   1 /*
   2  * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
   3  *
   4  * Dave Liu <daveliu@freescale.com>
   5  * based on source code of Shlomi Gridish
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #ifndef __QE_H__
  24 #define __QE_H__
  25
  26 #include "common.h"
  27
  28 #define QE_NUM_OF_BRGS  16
  29 #define UCC_MAX_NUM     8
  30
  31 #define QE_DATAONLY_BASE        0
  32 #define QE_DATAONLY_SIZE        (QE_MURAM_SIZE - QE_DATAONLY_BASE)
  33
  34 /* QE threads SNUM
  35 */
  36 typedef enum qe_snum_state {
  37         QE_SNUM_STATE_USED,   /* used */
  38         QE_SNUM_STATE_FREE    /* free */
  39 } qe_snum_state_e;
  40
  41 typedef struct qe_snum {
  42         u8              num;   /* snum  */
  43         qe_snum_state_e state; /* state */
  44 } qe_snum_t;
  45
  46 /* QE RISC allocation
  47 */
  48 #define QE_RISC_ALLOCATION_RISC1        0x1  /* RISC 1 */
  49 #define QE_RISC_ALLOCATION_RISC2        0x2  /* RISC 2 */
  50 #define QE_RISC_ALLOCATION_RISC3        0x4  /* RISC 3 */
  51 #define QE_RISC_ALLOCATION_RISC4        0x8  /* RISC 4 */
  52 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2      (QE_RISC_ALLOCATION_RISC1 | \
  53                                                  QE_RISC_ALLOCATION_RISC2)
  54 #define QE_RISC_ALLOCATION_FOUR_RISCS   (QE_RISC_ALLOCATION_RISC1 | \
  55                                          QE_RISC_ALLOCATION_RISC2 | \
  56                                          QE_RISC_ALLOCATION_RISC3 | \
  57                                          QE_RISC_ALLOCATION_RISC4)
  58
  59 /* QE CECR commands for UCC fast.
  60 */
  61 #define QE_CR_FLG                       0x00010000
  62 #define QE_RESET                        0x80000000
  63 #define QE_INIT_TX_RX                   0x00000000
  64 #define QE_INIT_RX                      0x00000001
  65 #define QE_INIT_TX                      0x00000002
  66 #define QE_ENTER_HUNT_MODE              0x00000003
  67 #define QE_STOP_TX                      0x00000004
  68 #define QE_GRACEFUL_STOP_TX             0x00000005
  69 #define QE_RESTART_TX                   0x00000006
  70 #define QE_SWITCH_COMMAND               0x00000007
  71 #define QE_SET_GROUP_ADDRESS            0x00000008
  72 #define QE_INSERT_CELL                  0x00000009
  73 #define QE_ATM_TRANSMIT                 0x0000000a
  74 #define QE_CELL_POOL_GET                0x0000000b
  75 #define QE_CELL_POOL_PUT                0x0000000c
  76 #define QE_IMA_HOST_CMD                 0x0000000d
  77 #define QE_ATM_MULTI_THREAD_INIT        0x00000011
  78 #define QE_ASSIGN_PAGE                  0x00000012
  79 #define QE_START_FLOW_CONTROL           0x00000014
  80 #define QE_STOP_FLOW_CONTROL            0x00000015
  81 #define QE_ASSIGN_PAGE_TO_DEVICE        0x00000016
  82 #define QE_GRACEFUL_STOP_RX             0x0000001a
  83 #define QE_RESTART_RX                   0x0000001b
  84
  85 /* QE CECR Sub Block Code - sub block code of QE command.
  86 */
  87 #define QE_CR_SUBBLOCK_INVALID          0x00000000
  88 #define QE_CR_SUBBLOCK_USB              0x03200000
  89 #define QE_CR_SUBBLOCK_UCCFAST1         0x02000000
  90 #define QE_CR_SUBBLOCK_UCCFAST2         0x02200000
  91 #define QE_CR_SUBBLOCK_UCCFAST3         0x02400000
  92 #define QE_CR_SUBBLOCK_UCCFAST4         0x02600000
  93 #define QE_CR_SUBBLOCK_UCCFAST5         0x02800000
  94 #define QE_CR_SUBBLOCK_UCCFAST6         0x02a00000
  95 #define QE_CR_SUBBLOCK_UCCFAST7         0x02c00000
  96 #define QE_CR_SUBBLOCK_UCCFAST8         0x02e00000
  97 #define QE_CR_SUBBLOCK_UCCSLOW1         0x00000000
  98 #define QE_CR_SUBBLOCK_UCCSLOW2         0x00200000
  99 #define QE_CR_SUBBLOCK_UCCSLOW3         0x00400000
 100 #define QE_CR_SUBBLOCK_UCCSLOW4         0x00600000
 101 #define QE_CR_SUBBLOCK_UCCSLOW5         0x00800000
 102 #define QE_CR_SUBBLOCK_UCCSLOW6         0x00a00000
 103 #define QE_CR_SUBBLOCK_UCCSLOW7         0x00c00000
 104 #define QE_CR_SUBBLOCK_UCCSLOW8         0x00e00000
 105 #define QE_CR_SUBBLOCK_MCC1             0x03800000
 106 #define QE_CR_SUBBLOCK_MCC2             0x03a00000
 107 #define QE_CR_SUBBLOCK_MCC3             0x03000000
 108 #define QE_CR_SUBBLOCK_IDMA1            0x02800000
 109 #define QE_CR_SUBBLOCK_IDMA2            0x02a00000
 110 #define QE_CR_SUBBLOCK_IDMA3            0x02c00000
 111 #define QE_CR_SUBBLOCK_IDMA4            0x02e00000
 112 #define QE_CR_SUBBLOCK_HPAC             0x01e00000
 113 #define QE_CR_SUBBLOCK_SPI1             0x01400000
 114 #define QE_CR_SUBBLOCK_SPI2             0x01600000
 115 #define QE_CR_SUBBLOCK_RAND             0x01c00000
 116 #define QE_CR_SUBBLOCK_TIMER            0x01e00000
 117 #define QE_CR_SUBBLOCK_GENERAL          0x03c00000
 118
 119 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command.
 120 */
 121 #define QE_CR_PROTOCOL_UNSPECIFIED      0x00 /* For all other protocols */
 122 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
 123 #define QE_CR_PROTOCOL_ATM_POS          0x0A
 124 #define QE_CR_PROTOCOL_ETHERNET         0x0C
 125 #define QE_CR_PROTOCOL_L2_SWITCH        0x0D
 126 #define QE_CR_PROTOCOL_SHIFT            6
 127
 128 /* QE ASSIGN PAGE command
 129 */
 130 #define QE_CR_ASSIGN_PAGE_SNUM_SHIFT    17
 131
 132 /* Communication Direction.
 133 */
 134 typedef enum comm_dir {
 135         COMM_DIR_NONE           = 0,
 136         COMM_DIR_RX             = 1,
 137         COMM_DIR_TX             = 2,
 138         COMM_DIR_RX_AND_TX      = 3
 139 } comm_dir_e;
 140
 141 /* Clocks and BRG's
 142 */
 143 typedef enum qe_clock {
 144         QE_CLK_NONE = 0,
 145         QE_BRG1,     /* Baud Rate Generator  1 */
 146         QE_BRG2,     /* Baud Rate Generator  2 */
 147         QE_BRG3,     /* Baud Rate Generator  3 */
 148         QE_BRG4,     /* Baud Rate Generator  4 */
 149         QE_BRG5,     /* Baud Rate Generator  5 */
 150         QE_BRG6,     /* Baud Rate Generator  6 */
 151         QE_BRG7,     /* Baud Rate Generator  7 */
 152         QE_BRG8,     /* Baud Rate Generator  8 */
 153         QE_BRG9,     /* Baud Rate Generator  9 */
 154         QE_BRG10,    /* Baud Rate Generator 10 */
 155         QE_BRG11,    /* Baud Rate Generator 11 */
 156         QE_BRG12,    /* Baud Rate Generator 12 */
 157         QE_BRG13,    /* Baud Rate Generator 13 */
 158         QE_BRG14,    /* Baud Rate Generator 14 */
 159         QE_BRG15,    /* Baud Rate Generator 15 */
 160         QE_BRG16,    /* Baud Rate Generator 16 */
 161         QE_CLK1,     /* Clock  1               */
 162         QE_CLK2,     /* Clock  2               */
 163         QE_CLK3,     /* Clock  3               */
 164         QE_CLK4,     /* Clock  4               */
 165         QE_CLK5,     /* Clock  5               */
 166         QE_CLK6,     /* Clock  6               */
 167         QE_CLK7,     /* Clock  7               */
 168         QE_CLK8,     /* Clock  8               */
 169         QE_CLK9,     /* Clock  9               */
 170         QE_CLK10,    /* Clock 10               */
 171         QE_CLK11,    /* Clock 11               */
 172         QE_CLK12,    /* Clock 12               */
 173         QE_CLK13,    /* Clock 13               */
 174         QE_CLK14,    /* Clock 14               */
 175         QE_CLK15,    /* Clock 15               */
 176         QE_CLK16,    /* Clock 16               */
 177         QE_CLK17,    /* Clock 17               */
 178         QE_CLK18,    /* Clock 18               */
 179         QE_CLK19,    /* Clock 19               */
 180         QE_CLK20,    /* Clock 20               */
 181         QE_CLK21,    /* Clock 21               */
 182         QE_CLK22,    /* Clock 22               */
 183         QE_CLK23,    /* Clock 23               */
 184         QE_CLK24,    /* Clock 24               */
 185         QE_CLK_DUMMY
 186 } qe_clock_e;
 187
 188 /* QE CMXGCR register
 189 */
 190 #define QE_CMXGCR_MII_ENET_MNG_MASK     0x00007000
 191 #define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
 192
 193 /* QE CMXUCR registers
 194  */
 195 #define QE_CMXUCR_TX_CLK_SRC_MASK       0x0000000F
 196
 197 /* QE BRG configuration register
 198 */
 199 #define QE_BRGC_ENABLE                  0x00010000
 200 #define QE_BRGC_DIVISOR_SHIFT           1
 201 #define QE_BRGC_DIVISOR_MAX             0xFFF
 202 #define QE_BRGC_DIV16                   1
 203
 204 /* QE SDMA registers
 205 */
 206 #define QE_SDSR_BER1                    0x02000000
 207 #define QE_SDSR_BER2                    0x01000000
 208
 209 #define QE_SDMR_GLB_1_MSK               0x80000000
 210 #define QE_SDMR_ADR_SEL                 0x20000000
 211 #define QE_SDMR_BER1_MSK                0x02000000
 212 #define QE_SDMR_BER2_MSK                0x01000000
 213 #define QE_SDMR_EB1_MSK                 0x00800000
 214 #define QE_SDMR_ER1_MSK                 0x00080000
 215 #define QE_SDMR_ER2_MSK                 0x00040000
 216 #define QE_SDMR_CEN_MASK                0x0000E000
 217 #define QE_SDMR_SBER_1                  0x00000200
 218 #define QE_SDMR_SBER_2                  0x00000200
 219 #define QE_SDMR_EB1_PR_MASK             0x000000C0
 220 #define QE_SDMR_ER1_PR                  0x00000008
 221
 222 #define QE_SDMR_CEN_SHIFT               13
 223 #define QE_SDMR_EB1_PR_SHIFT            6
 224
 225 #define QE_SDTM_MSNUM_SHIFT             24
 226
 227 #define QE_SDEBCR_BA_MASK               0x01FFFFFF
 228
 229 /* Communication Processor */
 230 #define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
 231 #define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
 232 #define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
 233
 234 /* I-RAM */
 235 #define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
 236 #define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
 237 #define QE_IRAM_READY           0x80000000
 238
 239 /* Structure that defines QE firmware binary files.
 240  *
 241  * See doc/README.qe_firmware for a description of these fields.
 242  */
 243 struct qe_firmware {
 244         struct qe_header {
 245                 u32 length;     /* Length of the entire structure, in bytes */
 246                 u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
 247                 u8 version;     /* Version of this layout. First ver is '1' */
 248         } header;
 249         u8 id[62];              /* Null-terminated identifier string */
 250         u8 split;               /* 0 = shared I-RAM, 1 = split I-RAM */
 251         u8 count;               /* Number of microcode[] structures */
 252         struct {
 253                 u16 model;      /* The SOC model  */
 254                 u8 major;       /* The SOC revision major */
 255                 u8 minor;       /* The SOC revision minor */
 256         } __attribute__ ((packed)) soc;
 257         u8 padding[4];          /* Reserved, for alignment */
 258         u64 extended_modes;     /* Extended modes */
 259         u32 vtraps[8];          /* Virtual trap addresses */
 260         u8 reserved[4];         /* Reserved, for future expansion */
 261         struct qe_microcode {
 262                 u8 id[32];      /* Null-terminated identifier */
 263                 u32 traps[16];  /* Trap addresses, 0 == ignore */
 264                 u32 eccr;       /* The value for the ECCR register */
 265                 u32 iram_offset;/* Offset into I-RAM for the code */
 266                 u32 count;      /* Number of 32-bit words of the code */
 267                 u32 code_offset;/* Offset of the actual microcode */
 268                 u8 major;       /* The microcode version major */
 269                 u8 minor;       /* The microcode version minor */
 270                 u8 revision;    /* The microcode version revision */
 271                 u8 padding;     /* Reserved, for alignment */
 272                 u8 reserved[4]; /* Reserved, for future expansion */
 273         } __attribute__ ((packed)) microcode[1];
 274         /* All microcode binaries should be located here */
 275         /* CRC32 should be located here, after the microcode binaries */
 276 } __attribute__ ((packed));
 277
 278 struct qe_firmware_info {
 279         char id[64];            /* Firmware name */
 280         u32 vtraps[8];          /* Virtual trap addresses */
 281         u64 extended_modes;     /* Extended modes */
 282 };
 283
 284 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign);
 285 void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data);
 286 uint qe_muram_alloc(uint size, uint align);
 287 void *qe_muram_addr(uint offset);
 288 int qe_get_snum(void);
 289 void qe_put_snum(u8 snum);
 290 void qe_init(uint qe_base);
 291 void qe_reset(void);
 292 void qe_assign_page(uint snum, uint para_ram_base);
 293 int qe_set_brg(uint brg, uint rate);
 294 int qe_set_mii_clk_src(int ucc_num);
 295 int qe_upload_firmware(const struct qe_firmware *firmware);
 296 struct qe_firmware_info *qe_get_firmware_info(void);
 297 void ft_qe_setup(void *blob);
 298
 299 #endif /* __QE_H__ */