2 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include "asm/errno.h"
27 #include "asm/immap_qe.h"
35 /* Default UTBIPAR SMI address */
36 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
37 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
40 static uec_info_t uec_info
[] = {
41 #ifdef CONFIG_UEC_ETH1
42 STD_UEC_INFO(1), /* UEC1 */
44 #ifdef CONFIG_UEC_ETH2
45 STD_UEC_INFO(2), /* UEC2 */
47 #ifdef CONFIG_UEC_ETH3
48 STD_UEC_INFO(3), /* UEC3 */
50 #ifdef CONFIG_UEC_ETH4
51 STD_UEC_INFO(4), /* UEC4 */
53 #ifdef CONFIG_UEC_ETH5
54 STD_UEC_INFO(5), /* UEC5 */
56 #ifdef CONFIG_UEC_ETH6
57 STD_UEC_INFO(6), /* UEC6 */
59 #ifdef CONFIG_UEC_ETH7
60 STD_UEC_INFO(7), /* UEC7 */
62 #ifdef CONFIG_UEC_ETH8
63 STD_UEC_INFO(8), /* UEC8 */
67 #define MAXCONTROLLERS (8)
69 static struct eth_device
*devlist
[MAXCONTROLLERS
];
71 static int uec_mac_enable(uec_private_t
*uec
, comm_dir_e mode
)
77 printf("%s: uec not initial\n", __FUNCTION__
);
80 uec_regs
= uec
->uec_regs
;
82 maccfg1
= in_be32(&uec_regs
->maccfg1
);
84 if (mode
& COMM_DIR_TX
) {
85 maccfg1
|= MACCFG1_ENABLE_TX
;
86 out_be32(&uec_regs
->maccfg1
, maccfg1
);
87 uec
->mac_tx_enabled
= 1;
90 if (mode
& COMM_DIR_RX
) {
91 maccfg1
|= MACCFG1_ENABLE_RX
;
92 out_be32(&uec_regs
->maccfg1
, maccfg1
);
93 uec
->mac_rx_enabled
= 1;
99 static int uec_mac_disable(uec_private_t
*uec
, comm_dir_e mode
)
105 printf("%s: uec not initial\n", __FUNCTION__
);
108 uec_regs
= uec
->uec_regs
;
110 maccfg1
= in_be32(&uec_regs
->maccfg1
);
112 if (mode
& COMM_DIR_TX
) {
113 maccfg1
&= ~MACCFG1_ENABLE_TX
;
114 out_be32(&uec_regs
->maccfg1
, maccfg1
);
115 uec
->mac_tx_enabled
= 0;
118 if (mode
& COMM_DIR_RX
) {
119 maccfg1
&= ~MACCFG1_ENABLE_RX
;
120 out_be32(&uec_regs
->maccfg1
, maccfg1
);
121 uec
->mac_rx_enabled
= 0;
127 static int uec_graceful_stop_tx(uec_private_t
*uec
)
133 if (!uec
|| !uec
->uccf
) {
134 printf("%s: No handle passed.\n", __FUNCTION__
);
138 uf_regs
= uec
->uccf
->uf_regs
;
140 /* Clear the grace stop event */
141 out_be32(&uf_regs
->ucce
, UCCE_GRA
);
143 /* Issue host command */
145 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
146 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
147 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
149 /* Wait for command to complete */
151 ucce
= in_be32(&uf_regs
->ucce
);
152 } while (! (ucce
& UCCE_GRA
));
154 uec
->grace_stopped_tx
= 1;
159 static int uec_graceful_stop_rx(uec_private_t
*uec
)
165 printf("%s: No handle passed.\n", __FUNCTION__
);
169 if (!uec
->p_rx_glbl_pram
) {
170 printf("%s: No init rx global parameter\n", __FUNCTION__
);
174 /* Clear acknowledge bit */
175 ack
= uec
->p_rx_glbl_pram
->rxgstpack
;
176 ack
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
177 uec
->p_rx_glbl_pram
->rxgstpack
= ack
;
179 /* Keep issuing cmd and checking ack bit until it is asserted */
181 /* Issue host command */
183 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
184 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
185 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
186 ack
= uec
->p_rx_glbl_pram
->rxgstpack
;
187 } while (! (ack
& GRACEFUL_STOP_ACKNOWLEDGE_RX
));
189 uec
->grace_stopped_rx
= 1;
194 static int uec_restart_tx(uec_private_t
*uec
)
198 if (!uec
|| !uec
->uec_info
) {
199 printf("%s: No handle passed.\n", __FUNCTION__
);
204 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
205 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
,
206 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
208 uec
->grace_stopped_tx
= 0;
213 static int uec_restart_rx(uec_private_t
*uec
)
217 if (!uec
|| !uec
->uec_info
) {
218 printf("%s: No handle passed.\n", __FUNCTION__
);
223 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
224 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
,
225 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
227 uec
->grace_stopped_rx
= 0;
232 static int uec_open(uec_private_t
*uec
, comm_dir_e mode
)
234 ucc_fast_private_t
*uccf
;
236 if (!uec
|| !uec
->uccf
) {
237 printf("%s: No handle passed.\n", __FUNCTION__
);
242 /* check if the UCC number is in range. */
243 if (uec
->uec_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
244 printf("%s: ucc_num out of range.\n", __FUNCTION__
);
249 uec_mac_enable(uec
, mode
);
251 /* Enable UCC fast */
252 ucc_fast_enable(uccf
, mode
);
254 /* RISC microcode start */
255 if ((mode
& COMM_DIR_TX
) && uec
->grace_stopped_tx
) {
258 if ((mode
& COMM_DIR_RX
) && uec
->grace_stopped_rx
) {
265 static int uec_stop(uec_private_t
*uec
, comm_dir_e mode
)
267 if (!uec
|| !uec
->uccf
) {
268 printf("%s: No handle passed.\n", __FUNCTION__
);
272 /* check if the UCC number is in range. */
273 if (uec
->uec_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
274 printf("%s: ucc_num out of range.\n", __FUNCTION__
);
277 /* Stop any transmissions */
278 if ((mode
& COMM_DIR_TX
) && !uec
->grace_stopped_tx
) {
279 uec_graceful_stop_tx(uec
);
281 /* Stop any receptions */
282 if ((mode
& COMM_DIR_RX
) && !uec
->grace_stopped_rx
) {
283 uec_graceful_stop_rx(uec
);
286 /* Disable the UCC fast */
287 ucc_fast_disable(uec
->uccf
, mode
);
289 /* Disable the MAC */
290 uec_mac_disable(uec
, mode
);
295 static int uec_set_mac_duplex(uec_private_t
*uec
, int duplex
)
301 printf("%s: uec not initial\n", __FUNCTION__
);
304 uec_regs
= uec
->uec_regs
;
306 if (duplex
== DUPLEX_HALF
) {
307 maccfg2
= in_be32(&uec_regs
->maccfg2
);
308 maccfg2
&= ~MACCFG2_FDX
;
309 out_be32(&uec_regs
->maccfg2
, maccfg2
);
312 if (duplex
== DUPLEX_FULL
) {
313 maccfg2
= in_be32(&uec_regs
->maccfg2
);
314 maccfg2
|= MACCFG2_FDX
;
315 out_be32(&uec_regs
->maccfg2
, maccfg2
);
321 static int uec_set_mac_if_mode(uec_private_t
*uec
,
322 phy_interface_t if_mode
, int speed
)
324 phy_interface_t enet_if_mode
;
330 printf("%s: uec not initial\n", __FUNCTION__
);
334 uec_regs
= uec
->uec_regs
;
335 enet_if_mode
= if_mode
;
337 maccfg2
= in_be32(&uec_regs
->maccfg2
);
338 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
340 upsmr
= in_be32(&uec
->uccf
->uf_regs
->upsmr
);
341 upsmr
&= ~(UPSMR_RPM
| UPSMR_TBIM
| UPSMR_R10M
| UPSMR_RMM
);
345 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
346 switch (enet_if_mode
) {
347 case PHY_INTERFACE_MODE_MII
:
349 case PHY_INTERFACE_MODE_RGMII
:
350 upsmr
|= (UPSMR_RPM
| UPSMR_R10M
);
352 case PHY_INTERFACE_MODE_RMII
:
353 upsmr
|= (UPSMR_R10M
| UPSMR_RMM
);
361 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
362 switch (enet_if_mode
) {
363 case PHY_INTERFACE_MODE_MII
:
365 case PHY_INTERFACE_MODE_RGMII
:
368 case PHY_INTERFACE_MODE_RMII
:
377 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
378 switch (enet_if_mode
) {
379 case PHY_INTERFACE_MODE_GMII
:
381 case PHY_INTERFACE_MODE_TBI
:
384 case PHY_INTERFACE_MODE_RTBI
:
385 upsmr
|= (UPSMR_RPM
| UPSMR_TBIM
);
387 case PHY_INTERFACE_MODE_RGMII_RXID
:
388 case PHY_INTERFACE_MODE_RGMII_TXID
:
389 case PHY_INTERFACE_MODE_RGMII_ID
:
390 case PHY_INTERFACE_MODE_RGMII
:
393 case PHY_INTERFACE_MODE_SGMII
:
406 out_be32(&uec_regs
->maccfg2
, maccfg2
);
407 out_be32(&uec
->uccf
->uf_regs
->upsmr
, upsmr
);
412 static int init_mii_management_configuration(uec_mii_t
*uec_mii_regs
)
414 uint timeout
= 0x1000;
417 miimcfg
= in_be32(&uec_mii_regs
->miimcfg
);
418 miimcfg
|= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE
;
419 out_be32(&uec_mii_regs
->miimcfg
, miimcfg
);
421 /* Wait until the bus is free */
422 while ((in_be32(&uec_mii_regs
->miimcfg
) & MIIMIND_BUSY
) && timeout
--);
424 printf("%s: The MII Bus is stuck!", __FUNCTION__
);
431 static int init_phy(struct eth_device
*dev
)
434 uec_mii_t
*umii_regs
;
435 struct uec_mii_info
*mii_info
;
436 struct phy_info
*curphy
;
439 uec
= (uec_private_t
*)dev
->priv
;
440 umii_regs
= uec
->uec_mii_regs
;
446 mii_info
= malloc(sizeof(*mii_info
));
448 printf("%s: Could not allocate mii_info", dev
->name
);
451 memset(mii_info
, 0, sizeof(*mii_info
));
453 if (uec
->uec_info
->uf_info
.eth_type
== GIGA_ETH
) {
454 mii_info
->speed
= SPEED_1000
;
456 mii_info
->speed
= SPEED_100
;
459 mii_info
->duplex
= DUPLEX_FULL
;
463 mii_info
->advertising
= (ADVERTISED_10baseT_Half
|
464 ADVERTISED_10baseT_Full
|
465 ADVERTISED_100baseT_Half
|
466 ADVERTISED_100baseT_Full
|
467 ADVERTISED_1000baseT_Full
);
468 mii_info
->autoneg
= 1;
469 mii_info
->mii_id
= uec
->uec_info
->phy_address
;
472 mii_info
->mdio_read
= &uec_read_phy_reg
;
473 mii_info
->mdio_write
= &uec_write_phy_reg
;
475 uec
->mii_info
= mii_info
;
477 qe_set_mii_clk_src(uec
->uec_info
->uf_info
.ucc_num
);
479 if (init_mii_management_configuration(umii_regs
)) {
480 printf("%s: The MII Bus is stuck!", dev
->name
);
485 /* get info for this PHY */
486 curphy
= uec_get_phy_info(uec
->mii_info
);
488 printf("%s: No PHY found", dev
->name
);
493 mii_info
->phyinfo
= curphy
;
495 /* Run the commands which initialize the PHY */
497 err
= curphy
->init(uec
->mii_info
);
511 static void adjust_link(struct eth_device
*dev
)
513 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
514 struct uec_mii_info
*mii_info
= uec
->mii_info
;
516 extern void change_phy_interface_mode(struct eth_device
*dev
,
517 phy_interface_t mode
, int speed
);
519 if (mii_info
->link
) {
520 /* Now we make sure that we can be in full duplex mode.
521 * If not, we operate in half-duplex mode. */
522 if (mii_info
->duplex
!= uec
->oldduplex
) {
523 if (!(mii_info
->duplex
)) {
524 uec_set_mac_duplex(uec
, DUPLEX_HALF
);
525 printf("%s: Half Duplex\n", dev
->name
);
527 uec_set_mac_duplex(uec
, DUPLEX_FULL
);
528 printf("%s: Full Duplex\n", dev
->name
);
530 uec
->oldduplex
= mii_info
->duplex
;
533 if (mii_info
->speed
!= uec
->oldspeed
) {
534 phy_interface_t mode
=
535 uec
->uec_info
->enet_interface_type
;
536 if (uec
->uec_info
->uf_info
.eth_type
== GIGA_ETH
) {
537 switch (mii_info
->speed
) {
541 printf ("switching to rgmii 100\n");
542 mode
= PHY_INTERFACE_MODE_RGMII
;
545 printf ("switching to rgmii 10\n");
546 mode
= PHY_INTERFACE_MODE_RGMII
;
549 printf("%s: Ack,Speed(%d)is illegal\n",
550 dev
->name
, mii_info
->speed
);
556 change_phy_interface_mode(dev
, mode
, mii_info
->speed
);
557 /* change the MAC interface mode */
558 uec_set_mac_if_mode(uec
, mode
, mii_info
->speed
);
560 printf("%s: Speed %dBT\n", dev
->name
, mii_info
->speed
);
561 uec
->oldspeed
= mii_info
->speed
;
565 printf("%s: Link is up\n", dev
->name
);
569 } else { /* if (mii_info->link) */
571 printf("%s: Link is down\n", dev
->name
);
579 static void phy_change(struct eth_device
*dev
)
581 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
583 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
584 defined(CONFIG_P1021) || defined(CONFIG_P1025)
585 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
587 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
588 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE9
);
589 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
592 /* Update the link, speed, duplex */
593 uec
->mii_info
->phyinfo
->read_status(uec
->mii_info
);
595 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
596 defined(CONFIG_P1021) || defined(CONFIG_P1025)
598 * QE12 is muxed with LBCTL, it needs to be released for enabling
599 * LBCTL signal for LBC usage.
601 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
604 /* Adjust the interface according to speed */
608 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
611 * Find a device index from the devlist by name
614 * The index where the device is located, -1 on error
616 static int uec_miiphy_find_dev_by_name(const char *devname
)
620 for (i
= 0; i
< MAXCONTROLLERS
; i
++) {
621 if (strncmp(devname
, devlist
[i
]->name
, strlen(devname
)) == 0) {
626 /* If device cannot be found, returns -1 */
627 if (i
== MAXCONTROLLERS
) {
628 debug ("%s: device %s not found in devlist\n", __FUNCTION__
, devname
);
636 * Read a MII PHY register.
641 static int uec_miiphy_read(const char *devname
, unsigned char addr
,
642 unsigned char reg
, unsigned short *value
)
646 if (devname
== NULL
|| value
== NULL
) {
647 debug("%s: NULL pointer given\n", __FUNCTION__
);
649 devindex
= uec_miiphy_find_dev_by_name(devname
);
651 *value
= uec_read_phy_reg(devlist
[devindex
], addr
, reg
);
658 * Write a MII PHY register.
663 static int uec_miiphy_write(const char *devname
, unsigned char addr
,
664 unsigned char reg
, unsigned short value
)
668 if (devname
== NULL
) {
669 debug("%s: NULL pointer given\n", __FUNCTION__
);
671 devindex
= uec_miiphy_find_dev_by_name(devname
);
673 uec_write_phy_reg(devlist
[devindex
], addr
, reg
, value
);
680 static int uec_set_mac_address(uec_private_t
*uec
, u8
*mac_addr
)
687 printf("%s: uec not initial\n", __FUNCTION__
);
691 uec_regs
= uec
->uec_regs
;
693 /* if a station address of 0x12345678ABCD, perform a write to
694 MACSTNADDR1 of 0xCDAB7856,
695 MACSTNADDR2 of 0x34120000 */
697 mac_addr1
= (mac_addr
[5] << 24) | (mac_addr
[4] << 16) | \
698 (mac_addr
[3] << 8) | (mac_addr
[2]);
699 out_be32(&uec_regs
->macstnaddr1
, mac_addr1
);
701 mac_addr2
= ((mac_addr
[1] << 24) | (mac_addr
[0] << 16)) & 0xffff0000;
702 out_be32(&uec_regs
->macstnaddr2
, mac_addr2
);
707 static int uec_convert_threads_num(uec_num_of_threads_e threads_num
,
708 int *threads_num_ret
)
710 int num_threads_numerica
;
712 switch (threads_num
) {
713 case UEC_NUM_OF_THREADS_1
:
714 num_threads_numerica
= 1;
716 case UEC_NUM_OF_THREADS_2
:
717 num_threads_numerica
= 2;
719 case UEC_NUM_OF_THREADS_4
:
720 num_threads_numerica
= 4;
722 case UEC_NUM_OF_THREADS_6
:
723 num_threads_numerica
= 6;
725 case UEC_NUM_OF_THREADS_8
:
726 num_threads_numerica
= 8;
729 printf("%s: Bad number of threads value.",
734 *threads_num_ret
= num_threads_numerica
;
739 static void uec_init_tx_parameter(uec_private_t
*uec
, int num_threads_tx
)
741 uec_info_t
*uec_info
;
746 uec_info
= uec
->uec_info
;
748 /* Alloc global Tx parameter RAM page */
749 uec
->tx_glbl_pram_offset
= qe_muram_alloc(
750 sizeof(uec_tx_global_pram_t
),
751 UEC_TX_GLOBAL_PRAM_ALIGNMENT
);
752 uec
->p_tx_glbl_pram
= (uec_tx_global_pram_t
*)
753 qe_muram_addr(uec
->tx_glbl_pram_offset
);
755 /* Zero the global Tx prameter RAM */
756 memset(uec
->p_tx_glbl_pram
, 0, sizeof(uec_tx_global_pram_t
));
758 /* Init global Tx parameter RAM */
760 /* TEMODER, RMON statistics disable, one Tx queue */
761 out_be16(&uec
->p_tx_glbl_pram
->temoder
, TEMODER_INIT_VALUE
);
764 uec
->send_q_mem_reg_offset
= qe_muram_alloc(
765 sizeof(uec_send_queue_qd_t
),
766 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
767 uec
->p_send_q_mem_reg
= (uec_send_queue_mem_region_t
*)
768 qe_muram_addr(uec
->send_q_mem_reg_offset
);
769 out_be32(&uec
->p_tx_glbl_pram
->sqptr
, uec
->send_q_mem_reg_offset
);
771 /* Setup the table with TxBDs ring */
772 end_bd
= (u32
)uec
->p_tx_bd_ring
+ (uec_info
->tx_bd_ring_len
- 1)
774 out_be32(&uec
->p_send_q_mem_reg
->sqqd
[0].bd_ring_base
,
775 (u32
)(uec
->p_tx_bd_ring
));
776 out_be32(&uec
->p_send_q_mem_reg
->sqqd
[0].last_bd_completed_address
,
779 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
780 out_be32(&uec
->p_tx_glbl_pram
->schedulerbasepointer
, 0);
782 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
783 out_be32(&uec
->p_tx_glbl_pram
->txrmonbaseptr
, 0);
785 /* TSTATE, global snooping, big endian, the CSB bus selected */
786 bmrx
= BMR_INIT_VALUE
;
787 out_be32(&uec
->p_tx_glbl_pram
->tstate
, ((u32
)(bmrx
) << BMR_SHIFT
));
790 for (i
= 0; i
< MAX_IPH_OFFSET_ENTRY
; i
++) {
791 out_8(&uec
->p_tx_glbl_pram
->iphoffset
[i
], 0);
795 for (i
= 0; i
< UEC_TX_VTAG_TABLE_ENTRY_MAX
; i
++) {
796 out_be32(&uec
->p_tx_glbl_pram
->vtagtable
[i
], 0);
800 uec
->thread_dat_tx_offset
= qe_muram_alloc(
801 num_threads_tx
* sizeof(uec_thread_data_tx_t
) +
802 32 *(num_threads_tx
== 1), UEC_THREAD_DATA_ALIGNMENT
);
804 uec
->p_thread_data_tx
= (uec_thread_data_tx_t
*)
805 qe_muram_addr(uec
->thread_dat_tx_offset
);
806 out_be32(&uec
->p_tx_glbl_pram
->tqptr
, uec
->thread_dat_tx_offset
);
809 static void uec_init_rx_parameter(uec_private_t
*uec
, int num_threads_rx
)
813 uec_82xx_address_filtering_pram_t
*p_af_pram
;
815 /* Allocate global Rx parameter RAM page */
816 uec
->rx_glbl_pram_offset
= qe_muram_alloc(
817 sizeof(uec_rx_global_pram_t
), UEC_RX_GLOBAL_PRAM_ALIGNMENT
);
818 uec
->p_rx_glbl_pram
= (uec_rx_global_pram_t
*)
819 qe_muram_addr(uec
->rx_glbl_pram_offset
);
821 /* Zero Global Rx parameter RAM */
822 memset(uec
->p_rx_glbl_pram
, 0, sizeof(uec_rx_global_pram_t
));
824 /* Init global Rx parameter RAM */
825 /* REMODER, Extended feature mode disable, VLAN disable,
826 LossLess flow control disable, Receive firmware statisic disable,
827 Extended address parsing mode disable, One Rx queues,
828 Dynamic maximum/minimum frame length disable, IP checksum check
829 disable, IP address alignment disable
831 out_be32(&uec
->p_rx_glbl_pram
->remoder
, REMODER_INIT_VALUE
);
834 uec
->thread_dat_rx_offset
= qe_muram_alloc(
835 num_threads_rx
* sizeof(uec_thread_data_rx_t
),
836 UEC_THREAD_DATA_ALIGNMENT
);
837 uec
->p_thread_data_rx
= (uec_thread_data_rx_t
*)
838 qe_muram_addr(uec
->thread_dat_rx_offset
);
839 out_be32(&uec
->p_rx_glbl_pram
->rqptr
, uec
->thread_dat_rx_offset
);
842 out_be16(&uec
->p_rx_glbl_pram
->typeorlen
, 3072);
844 /* RxRMON base pointer, we don't need it */
845 out_be32(&uec
->p_rx_glbl_pram
->rxrmonbaseptr
, 0);
847 /* IntCoalescingPTR, we don't need it, no interrupt */
848 out_be32(&uec
->p_rx_glbl_pram
->intcoalescingptr
, 0);
850 /* RSTATE, global snooping, big endian, the CSB bus selected */
851 bmrx
= BMR_INIT_VALUE
;
852 out_8(&uec
->p_rx_glbl_pram
->rstate
, bmrx
);
855 out_be16(&uec
->p_rx_glbl_pram
->mrblr
, MAX_RXBUF_LEN
);
858 uec
->rx_bd_qs_tbl_offset
= qe_muram_alloc(
859 sizeof(uec_rx_bd_queues_entry_t
) + \
860 sizeof(uec_rx_prefetched_bds_t
),
861 UEC_RX_BD_QUEUES_ALIGNMENT
);
862 uec
->p_rx_bd_qs_tbl
= (uec_rx_bd_queues_entry_t
*)
863 qe_muram_addr(uec
->rx_bd_qs_tbl_offset
);
866 memset(uec
->p_rx_bd_qs_tbl
, 0, sizeof(uec_rx_bd_queues_entry_t
) + \
867 sizeof(uec_rx_prefetched_bds_t
));
868 out_be32(&uec
->p_rx_glbl_pram
->rbdqptr
, uec
->rx_bd_qs_tbl_offset
);
869 out_be32(&uec
->p_rx_bd_qs_tbl
->externalbdbaseptr
,
870 (u32
)uec
->p_rx_bd_ring
);
873 out_be16(&uec
->p_rx_glbl_pram
->mflr
, MAX_FRAME_LEN
);
875 out_be16(&uec
->p_rx_glbl_pram
->minflr
, MIN_FRAME_LEN
);
877 out_be16(&uec
->p_rx_glbl_pram
->maxd1
, MAX_DMA1_LEN
);
879 out_be16(&uec
->p_rx_glbl_pram
->maxd2
, MAX_DMA2_LEN
);
881 out_be32(&uec
->p_rx_glbl_pram
->ecamptr
, 0);
883 out_be32(&uec
->p_rx_glbl_pram
->l2qt
, 0);
885 for (i
= 0; i
< 8; i
++) {
886 out_be32(&uec
->p_rx_glbl_pram
->l3qt
[i
], 0);
890 out_be16(&uec
->p_rx_glbl_pram
->vlantype
, 0x8100);
892 out_be16(&uec
->p_rx_glbl_pram
->vlantci
, 0);
894 /* Clear PQ2 style address filtering hash table */
895 p_af_pram
= (uec_82xx_address_filtering_pram_t
*) \
896 uec
->p_rx_glbl_pram
->addressfiltering
;
898 p_af_pram
->iaddr_h
= 0;
899 p_af_pram
->iaddr_l
= 0;
900 p_af_pram
->gaddr_h
= 0;
901 p_af_pram
->gaddr_l
= 0;
904 static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec
,
905 int thread_tx
, int thread_rx
)
907 uec_init_cmd_pram_t
*p_init_enet_param
;
908 u32 init_enet_param_offset
;
909 uec_info_t
*uec_info
;
912 u32 init_enet_offset
;
917 uec_info
= uec
->uec_info
;
919 /* Allocate init enet command parameter */
920 uec
->init_enet_param_offset
= qe_muram_alloc(
921 sizeof(uec_init_cmd_pram_t
), 4);
922 init_enet_param_offset
= uec
->init_enet_param_offset
;
923 uec
->p_init_enet_param
= (uec_init_cmd_pram_t
*)
924 qe_muram_addr(uec
->init_enet_param_offset
);
926 /* Zero init enet command struct */
927 memset((void *)uec
->p_init_enet_param
, 0, sizeof(uec_init_cmd_pram_t
));
929 /* Init the command struct */
930 p_init_enet_param
= uec
->p_init_enet_param
;
931 p_init_enet_param
->resinit0
= ENET_INIT_PARAM_MAGIC_RES_INIT0
;
932 p_init_enet_param
->resinit1
= ENET_INIT_PARAM_MAGIC_RES_INIT1
;
933 p_init_enet_param
->resinit2
= ENET_INIT_PARAM_MAGIC_RES_INIT2
;
934 p_init_enet_param
->resinit3
= ENET_INIT_PARAM_MAGIC_RES_INIT3
;
935 p_init_enet_param
->resinit4
= ENET_INIT_PARAM_MAGIC_RES_INIT4
;
936 p_init_enet_param
->largestexternallookupkeysize
= 0;
938 p_init_enet_param
->rgftgfrxglobal
|= ((u32
)uec_info
->num_threads_rx
)
939 << ENET_INIT_PARAM_RGF_SHIFT
;
940 p_init_enet_param
->rgftgfrxglobal
|= ((u32
)uec_info
->num_threads_tx
)
941 << ENET_INIT_PARAM_TGF_SHIFT
;
943 /* Init Rx global parameter pointer */
944 p_init_enet_param
->rgftgfrxglobal
|= uec
->rx_glbl_pram_offset
|
945 (u32
)uec_info
->risc_rx
;
947 /* Init Rx threads */
948 for (i
= 0; i
< (thread_rx
+ 1); i
++) {
949 if ((snum
= qe_get_snum()) < 0) {
950 printf("%s can not get snum\n", __FUNCTION__
);
955 init_enet_offset
= 0;
957 init_enet_offset
= qe_muram_alloc(
958 sizeof(uec_thread_rx_pram_t
),
959 UEC_THREAD_RX_PRAM_ALIGNMENT
);
962 entry_val
= ((u32
)snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) |
963 init_enet_offset
| (u32
)uec_info
->risc_rx
;
964 p_init_enet_param
->rxthread
[i
] = entry_val
;
967 /* Init Tx global parameter pointer */
968 p_init_enet_param
->txglobal
= uec
->tx_glbl_pram_offset
|
969 (u32
)uec_info
->risc_tx
;
971 /* Init Tx threads */
972 for (i
= 0; i
< thread_tx
; i
++) {
973 if ((snum
= qe_get_snum()) < 0) {
974 printf("%s can not get snum\n", __FUNCTION__
);
978 init_enet_offset
= qe_muram_alloc(sizeof(uec_thread_tx_pram_t
),
979 UEC_THREAD_TX_PRAM_ALIGNMENT
);
981 entry_val
= ((u32
)snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) |
982 init_enet_offset
| (u32
)uec_info
->risc_tx
;
983 p_init_enet_param
->txthread
[i
] = entry_val
;
986 __asm__
__volatile__("sync");
988 /* Issue QE command */
989 command
= QE_INIT_TX_RX
;
990 cecr_subblock
= ucc_fast_get_qe_cr_subblock(
991 uec
->uec_info
->uf_info
.ucc_num
);
992 qe_issue_cmd(command
, cecr_subblock
, (u8
) QE_CR_PROTOCOL_ETHERNET
,
993 init_enet_param_offset
);
998 static int uec_startup(uec_private_t
*uec
)
1000 uec_info_t
*uec_info
;
1001 ucc_fast_info_t
*uf_info
;
1002 ucc_fast_private_t
*uccf
;
1003 ucc_fast_t
*uf_regs
;
1014 if (!uec
|| !uec
->uec_info
) {
1015 printf("%s: uec or uec_info not initial\n", __FUNCTION__
);
1019 uec_info
= uec
->uec_info
;
1020 uf_info
= &(uec_info
->uf_info
);
1022 /* Check if Rx BD ring len is illegal */
1023 if ((uec_info
->rx_bd_ring_len
< UEC_RX_BD_RING_SIZE_MIN
) || \
1024 (uec_info
->rx_bd_ring_len
% UEC_RX_BD_RING_SIZE_ALIGNMENT
)) {
1025 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1030 /* Check if Tx BD ring len is illegal */
1031 if (uec_info
->tx_bd_ring_len
< UEC_TX_BD_RING_SIZE_MIN
) {
1032 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1037 /* Check if MRBLR is illegal */
1038 if ((MAX_RXBUF_LEN
== 0) || (MAX_RXBUF_LEN
% UEC_MRBLR_ALIGNMENT
)) {
1039 printf("%s: max rx buffer length must be mutliple of 128.\n",
1044 /* Both Rx and Tx are stopped */
1045 uec
->grace_stopped_rx
= 1;
1046 uec
->grace_stopped_tx
= 1;
1049 if (ucc_fast_init(uf_info
, &uccf
)) {
1050 printf("%s: failed to init ucc fast\n", __FUNCTION__
);
1057 /* Convert the Tx threads number */
1058 if (uec_convert_threads_num(uec_info
->num_threads_tx
,
1063 /* Convert the Rx threads number */
1064 if (uec_convert_threads_num(uec_info
->num_threads_rx
,
1069 uf_regs
= uccf
->uf_regs
;
1071 /* UEC register is following UCC fast registers */
1072 uec_regs
= (uec_t
*)(&uf_regs
->ucc_eth
);
1074 /* Save the UEC register pointer to UEC private struct */
1075 uec
->uec_regs
= uec_regs
;
1077 /* Init UPSMR, enable hardware statistics (UCC) */
1078 out_be32(&uec
->uccf
->uf_regs
->upsmr
, UPSMR_INIT_VALUE
);
1080 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1081 out_be32(&uec_regs
->maccfg1
, MACCFG1_INIT_VALUE
);
1083 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1084 out_be32(&uec_regs
->maccfg2
, MACCFG2_INIT_VALUE
);
1086 /* Setup MAC interface mode */
1087 uec_set_mac_if_mode(uec
, uec_info
->enet_interface_type
, uec_info
->speed
);
1089 /* Setup MII management base */
1090 #ifndef CONFIG_eTSEC_MDIO_BUS
1091 uec
->uec_mii_regs
= (uec_mii_t
*)(&uec_regs
->miimcfg
);
1093 uec
->uec_mii_regs
= (uec_mii_t
*) CONFIG_MIIM_ADDRESS
;
1096 /* Setup MII master clock source */
1097 qe_set_mii_clk_src(uec_info
->uf_info
.ucc_num
);
1100 utbipar
= in_be32(&uec_regs
->utbipar
);
1101 utbipar
&= ~UTBIPAR_PHY_ADDRESS_MASK
;
1103 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1104 * This frees up the remaining SMI addresses for use.
1106 utbipar
|= CONFIG_UTBIPAR_INIT_TBIPA
<< UTBIPAR_PHY_ADDRESS_SHIFT
;
1107 out_be32(&uec_regs
->utbipar
, utbipar
);
1109 /* Configure the TBI for SGMII operation */
1110 if ((uec
->uec_info
->enet_interface_type
== PHY_INTERFACE_MODE_SGMII
) &&
1111 (uec
->uec_info
->speed
== SPEED_1000
)) {
1112 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1113 ENET_TBI_MII_ANA
, TBIANA_SETTINGS
);
1115 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1116 ENET_TBI_MII_TBICON
, TBICON_CLK_SELECT
);
1118 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1119 ENET_TBI_MII_CR
, TBICR_SETTINGS
);
1122 /* Allocate Tx BDs */
1123 length
= ((uec_info
->tx_bd_ring_len
* SIZEOFBD
) /
1124 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
) *
1125 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
1126 if ((uec_info
->tx_bd_ring_len
* SIZEOFBD
) %
1127 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
) {
1128 length
+= UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
1131 align
= UEC_TX_BD_RING_ALIGNMENT
;
1132 uec
->tx_bd_ring_offset
= (u32
)malloc((u32
)(length
+ align
));
1133 if (uec
->tx_bd_ring_offset
!= 0) {
1134 uec
->p_tx_bd_ring
= (u8
*)((uec
->tx_bd_ring_offset
+ align
)
1138 /* Zero all of Tx BDs */
1139 memset((void *)(uec
->tx_bd_ring_offset
), 0, length
+ align
);
1141 /* Allocate Rx BDs */
1142 length
= uec_info
->rx_bd_ring_len
* SIZEOFBD
;
1143 align
= UEC_RX_BD_RING_ALIGNMENT
;
1144 uec
->rx_bd_ring_offset
= (u32
)(malloc((u32
)(length
+ align
)));
1145 if (uec
->rx_bd_ring_offset
!= 0) {
1146 uec
->p_rx_bd_ring
= (u8
*)((uec
->rx_bd_ring_offset
+ align
)
1150 /* Zero all of Rx BDs */
1151 memset((void *)(uec
->rx_bd_ring_offset
), 0, length
+ align
);
1153 /* Allocate Rx buffer */
1154 length
= uec_info
->rx_bd_ring_len
* MAX_RXBUF_LEN
;
1155 align
= UEC_RX_DATA_BUF_ALIGNMENT
;
1156 uec
->rx_buf_offset
= (u32
)malloc(length
+ align
);
1157 if (uec
->rx_buf_offset
!= 0) {
1158 uec
->p_rx_buf
= (u8
*)((uec
->rx_buf_offset
+ align
)
1162 /* Zero all of the Rx buffer */
1163 memset((void *)(uec
->rx_buf_offset
), 0, length
+ align
);
1165 /* Init TxBD ring */
1166 bd
= (qe_bd_t
*)uec
->p_tx_bd_ring
;
1169 for (i
= 0; i
< uec_info
->tx_bd_ring_len
; i
++) {
1171 BD_STATUS_SET(bd
, 0);
1172 BD_LENGTH_SET(bd
, 0);
1175 BD_STATUS_SET((--bd
), TxBD_WRAP
);
1177 /* Init RxBD ring */
1178 bd
= (qe_bd_t
*)uec
->p_rx_bd_ring
;
1180 buf
= uec
->p_rx_buf
;
1181 for (i
= 0; i
< uec_info
->rx_bd_ring_len
; i
++) {
1182 BD_DATA_SET(bd
, buf
);
1183 BD_LENGTH_SET(bd
, 0);
1184 BD_STATUS_SET(bd
, RxBD_EMPTY
);
1185 buf
+= MAX_RXBUF_LEN
;
1188 BD_STATUS_SET((--bd
), RxBD_WRAP
| RxBD_EMPTY
);
1190 /* Init global Tx parameter RAM */
1191 uec_init_tx_parameter(uec
, num_threads_tx
);
1193 /* Init global Rx parameter RAM */
1194 uec_init_rx_parameter(uec
, num_threads_rx
);
1196 /* Init ethernet Tx and Rx parameter command */
1197 if (uec_issue_init_enet_rxtx_cmd(uec
, num_threads_tx
,
1199 printf("%s issue init enet cmd failed\n", __FUNCTION__
);
1206 static int uec_init(struct eth_device
* dev
, bd_t
*bd
)
1210 struct phy_info
*curphy
;
1211 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1212 defined(CONFIG_P1021) || defined(CONFIG_P1025)
1213 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
1216 uec
= (uec_private_t
*)dev
->priv
;
1218 if (uec
->the_first_run
== 0) {
1219 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1220 defined(CONFIG_P1021) || defined(CONFIG_P1025)
1221 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1222 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE9
);
1223 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
1226 err
= init_phy(dev
);
1228 printf("%s: Cannot initialize PHY, aborting.\n",
1233 curphy
= uec
->mii_info
->phyinfo
;
1235 if (curphy
->config_aneg
) {
1236 err
= curphy
->config_aneg(uec
->mii_info
);
1238 printf("%s: Can't negotiate PHY\n", dev
->name
);
1243 /* Give PHYs up to 5 sec to report a link */
1246 err
= curphy
->read_status(uec
->mii_info
);
1247 if (!(((i
-- > 0) && !uec
->mii_info
->link
) || err
))
1252 #if defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
1253 defined(CONFIG_P1021) || defined(CONFIG_P1025)
1254 /* QE12 needs to be released for enabling LBCTL signal*/
1255 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
1259 printf("warning: %s: timeout on PHY link\n", dev
->name
);
1262 uec
->the_first_run
= 1;
1265 /* Set up the MAC address */
1266 if (dev
->enetaddr
[0] & 0x01) {
1267 printf("%s: MacAddress is multcast address\n",
1271 uec_set_mac_address(uec
, dev
->enetaddr
);
1274 err
= uec_open(uec
, COMM_DIR_RX_AND_TX
);
1276 printf("%s: cannot enable UEC device\n", dev
->name
);
1282 return (uec
->mii_info
->link
? 0 : -1);
1285 static void uec_halt(struct eth_device
* dev
)
1287 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
1288 uec_stop(uec
, COMM_DIR_RX_AND_TX
);
1291 static int uec_send(struct eth_device
*dev
, void *buf
, int len
)
1294 ucc_fast_private_t
*uccf
;
1295 volatile qe_bd_t
*bd
;
1300 uec
= (uec_private_t
*)dev
->priv
;
1304 /* Find an empty TxBD */
1305 for (i
= 0; bd
->status
& TxBD_READY
; i
++) {
1307 printf("%s: tx buffer not ready\n", dev
->name
);
1313 BD_DATA_SET(bd
, buf
);
1314 BD_LENGTH_SET(bd
, len
);
1315 status
= bd
->status
;
1317 status
|= (TxBD_READY
| TxBD_LAST
);
1318 BD_STATUS_SET(bd
, status
);
1320 /* Tell UCC to transmit the buffer */
1321 ucc_fast_transmit_on_demand(uccf
);
1323 /* Wait for buffer to be transmitted */
1324 for (i
= 0; bd
->status
& TxBD_READY
; i
++) {
1326 printf("%s: tx error\n", dev
->name
);
1331 /* Ok, the buffer be transimitted */
1332 BD_ADVANCE(bd
, status
, uec
->p_tx_bd_ring
);
1339 static int uec_recv(struct eth_device
* dev
)
1341 uec_private_t
*uec
= dev
->priv
;
1342 volatile qe_bd_t
*bd
;
1348 status
= bd
->status
;
1350 while (!(status
& RxBD_EMPTY
)) {
1351 if (!(status
& RxBD_ERROR
)) {
1353 len
= BD_LENGTH(bd
);
1354 NetReceive(data
, len
);
1356 printf("%s: Rx error\n", dev
->name
);
1359 BD_LENGTH_SET(bd
, 0);
1360 BD_STATUS_SET(bd
, status
| RxBD_EMPTY
);
1361 BD_ADVANCE(bd
, status
, uec
->p_rx_bd_ring
);
1362 status
= bd
->status
;
1369 int uec_initialize(bd_t
*bis
, uec_info_t
*uec_info
)
1371 struct eth_device
*dev
;
1376 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
1379 memset(dev
, 0, sizeof(struct eth_device
));
1381 /* Allocate the UEC private struct */
1382 uec
= (uec_private_t
*)malloc(sizeof(uec_private_t
));
1386 memset(uec
, 0, sizeof(uec_private_t
));
1388 /* Adjust uec_info */
1389 #if (MAX_QE_RISC == 4)
1390 uec_info
->risc_tx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
1391 uec_info
->risc_rx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
1394 devlist
[uec_info
->uf_info
.ucc_num
] = dev
;
1396 uec
->uec_info
= uec_info
;
1399 sprintf(dev
->name
, "UEC%d", uec_info
->uf_info
.ucc_num
);
1401 dev
->priv
= (void *)uec
;
1402 dev
->init
= uec_init
;
1403 dev
->halt
= uec_halt
;
1404 dev
->send
= uec_send
;
1405 dev
->recv
= uec_recv
;
1407 /* Clear the ethnet address */
1408 for (i
= 0; i
< 6; i
++)
1409 dev
->enetaddr
[i
] = 0;
1413 err
= uec_startup(uec
);
1415 printf("%s: Cannot configure net device, aborting.",dev
->name
);
1419 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1420 miiphy_register(dev
->name
, uec_miiphy_read
, uec_miiphy_write
);
1426 int uec_eth_init(bd_t
*bis
, uec_info_t
*uecs
, int num
)
1430 for (i
= 0; i
< num
; i
++)
1431 uec_initialize(bis
, &uecs
[i
]);
1436 int uec_standard_init(bd_t
*bis
)
1438 return uec_eth_init(bis
, uec_info
, ARRAY_SIZE(uec_info
));