2 * Copyright (C) 2006-2011 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include "asm/errno.h"
14 #include "linux/immap_qe.h"
22 /* Default UTBIPAR SMI address */
23 #ifndef CONFIG_UTBIPAR_INIT_TBIPA
24 #define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
27 static uec_info_t uec_info
[] = {
28 #ifdef CONFIG_UEC_ETH1
29 STD_UEC_INFO(1), /* UEC1 */
31 #ifdef CONFIG_UEC_ETH2
32 STD_UEC_INFO(2), /* UEC2 */
34 #ifdef CONFIG_UEC_ETH3
35 STD_UEC_INFO(3), /* UEC3 */
37 #ifdef CONFIG_UEC_ETH4
38 STD_UEC_INFO(4), /* UEC4 */
40 #ifdef CONFIG_UEC_ETH5
41 STD_UEC_INFO(5), /* UEC5 */
43 #ifdef CONFIG_UEC_ETH6
44 STD_UEC_INFO(6), /* UEC6 */
46 #ifdef CONFIG_UEC_ETH7
47 STD_UEC_INFO(7), /* UEC7 */
49 #ifdef CONFIG_UEC_ETH8
50 STD_UEC_INFO(8), /* UEC8 */
54 #define MAXCONTROLLERS (8)
56 static struct eth_device
*devlist
[MAXCONTROLLERS
];
58 static int uec_mac_enable(uec_private_t
*uec
, comm_dir_e mode
)
64 printf("%s: uec not initial\n", __FUNCTION__
);
67 uec_regs
= uec
->uec_regs
;
69 maccfg1
= in_be32(&uec_regs
->maccfg1
);
71 if (mode
& COMM_DIR_TX
) {
72 maccfg1
|= MACCFG1_ENABLE_TX
;
73 out_be32(&uec_regs
->maccfg1
, maccfg1
);
74 uec
->mac_tx_enabled
= 1;
77 if (mode
& COMM_DIR_RX
) {
78 maccfg1
|= MACCFG1_ENABLE_RX
;
79 out_be32(&uec_regs
->maccfg1
, maccfg1
);
80 uec
->mac_rx_enabled
= 1;
86 static int uec_mac_disable(uec_private_t
*uec
, comm_dir_e mode
)
92 printf("%s: uec not initial\n", __FUNCTION__
);
95 uec_regs
= uec
->uec_regs
;
97 maccfg1
= in_be32(&uec_regs
->maccfg1
);
99 if (mode
& COMM_DIR_TX
) {
100 maccfg1
&= ~MACCFG1_ENABLE_TX
;
101 out_be32(&uec_regs
->maccfg1
, maccfg1
);
102 uec
->mac_tx_enabled
= 0;
105 if (mode
& COMM_DIR_RX
) {
106 maccfg1
&= ~MACCFG1_ENABLE_RX
;
107 out_be32(&uec_regs
->maccfg1
, maccfg1
);
108 uec
->mac_rx_enabled
= 0;
114 static int uec_graceful_stop_tx(uec_private_t
*uec
)
120 if (!uec
|| !uec
->uccf
) {
121 printf("%s: No handle passed.\n", __FUNCTION__
);
125 uf_regs
= uec
->uccf
->uf_regs
;
127 /* Clear the grace stop event */
128 out_be32(&uf_regs
->ucce
, UCCE_GRA
);
130 /* Issue host command */
132 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
133 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
134 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
136 /* Wait for command to complete */
138 ucce
= in_be32(&uf_regs
->ucce
);
139 } while (! (ucce
& UCCE_GRA
));
141 uec
->grace_stopped_tx
= 1;
146 static int uec_graceful_stop_rx(uec_private_t
*uec
)
152 printf("%s: No handle passed.\n", __FUNCTION__
);
156 if (!uec
->p_rx_glbl_pram
) {
157 printf("%s: No init rx global parameter\n", __FUNCTION__
);
161 /* Clear acknowledge bit */
162 ack
= uec
->p_rx_glbl_pram
->rxgstpack
;
163 ack
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
164 uec
->p_rx_glbl_pram
->rxgstpack
= ack
;
166 /* Keep issuing cmd and checking ack bit until it is asserted */
168 /* Issue host command */
170 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
171 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
172 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
173 ack
= uec
->p_rx_glbl_pram
->rxgstpack
;
174 } while (! (ack
& GRACEFUL_STOP_ACKNOWLEDGE_RX
));
176 uec
->grace_stopped_rx
= 1;
181 static int uec_restart_tx(uec_private_t
*uec
)
185 if (!uec
|| !uec
->uec_info
) {
186 printf("%s: No handle passed.\n", __FUNCTION__
);
191 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
192 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
,
193 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
195 uec
->grace_stopped_tx
= 0;
200 static int uec_restart_rx(uec_private_t
*uec
)
204 if (!uec
|| !uec
->uec_info
) {
205 printf("%s: No handle passed.\n", __FUNCTION__
);
210 ucc_fast_get_qe_cr_subblock(uec
->uec_info
->uf_info
.ucc_num
);
211 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
,
212 (u8
)QE_CR_PROTOCOL_ETHERNET
, 0);
214 uec
->grace_stopped_rx
= 0;
219 static int uec_open(uec_private_t
*uec
, comm_dir_e mode
)
221 ucc_fast_private_t
*uccf
;
223 if (!uec
|| !uec
->uccf
) {
224 printf("%s: No handle passed.\n", __FUNCTION__
);
229 /* check if the UCC number is in range. */
230 if (uec
->uec_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
231 printf("%s: ucc_num out of range.\n", __FUNCTION__
);
236 uec_mac_enable(uec
, mode
);
238 /* Enable UCC fast */
239 ucc_fast_enable(uccf
, mode
);
241 /* RISC microcode start */
242 if ((mode
& COMM_DIR_TX
) && uec
->grace_stopped_tx
) {
245 if ((mode
& COMM_DIR_RX
) && uec
->grace_stopped_rx
) {
252 static int uec_stop(uec_private_t
*uec
, comm_dir_e mode
)
254 if (!uec
|| !uec
->uccf
) {
255 printf("%s: No handle passed.\n", __FUNCTION__
);
259 /* check if the UCC number is in range. */
260 if (uec
->uec_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
261 printf("%s: ucc_num out of range.\n", __FUNCTION__
);
264 /* Stop any transmissions */
265 if ((mode
& COMM_DIR_TX
) && !uec
->grace_stopped_tx
) {
266 uec_graceful_stop_tx(uec
);
268 /* Stop any receptions */
269 if ((mode
& COMM_DIR_RX
) && !uec
->grace_stopped_rx
) {
270 uec_graceful_stop_rx(uec
);
273 /* Disable the UCC fast */
274 ucc_fast_disable(uec
->uccf
, mode
);
276 /* Disable the MAC */
277 uec_mac_disable(uec
, mode
);
282 static int uec_set_mac_duplex(uec_private_t
*uec
, int duplex
)
288 printf("%s: uec not initial\n", __FUNCTION__
);
291 uec_regs
= uec
->uec_regs
;
293 if (duplex
== DUPLEX_HALF
) {
294 maccfg2
= in_be32(&uec_regs
->maccfg2
);
295 maccfg2
&= ~MACCFG2_FDX
;
296 out_be32(&uec_regs
->maccfg2
, maccfg2
);
299 if (duplex
== DUPLEX_FULL
) {
300 maccfg2
= in_be32(&uec_regs
->maccfg2
);
301 maccfg2
|= MACCFG2_FDX
;
302 out_be32(&uec_regs
->maccfg2
, maccfg2
);
308 static int uec_set_mac_if_mode(uec_private_t
*uec
,
309 phy_interface_t if_mode
, int speed
)
311 phy_interface_t enet_if_mode
;
317 printf("%s: uec not initial\n", __FUNCTION__
);
321 uec_regs
= uec
->uec_regs
;
322 enet_if_mode
= if_mode
;
324 maccfg2
= in_be32(&uec_regs
->maccfg2
);
325 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
327 upsmr
= in_be32(&uec
->uccf
->uf_regs
->upsmr
);
328 upsmr
&= ~(UPSMR_RPM
| UPSMR_TBIM
| UPSMR_R10M
| UPSMR_RMM
);
332 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
333 switch (enet_if_mode
) {
334 case PHY_INTERFACE_MODE_MII
:
336 case PHY_INTERFACE_MODE_RGMII
:
337 upsmr
|= (UPSMR_RPM
| UPSMR_R10M
);
339 case PHY_INTERFACE_MODE_RMII
:
340 upsmr
|= (UPSMR_R10M
| UPSMR_RMM
);
348 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
349 switch (enet_if_mode
) {
350 case PHY_INTERFACE_MODE_MII
:
352 case PHY_INTERFACE_MODE_RGMII
:
355 case PHY_INTERFACE_MODE_RMII
:
364 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
365 switch (enet_if_mode
) {
366 case PHY_INTERFACE_MODE_GMII
:
368 case PHY_INTERFACE_MODE_TBI
:
371 case PHY_INTERFACE_MODE_RTBI
:
372 upsmr
|= (UPSMR_RPM
| UPSMR_TBIM
);
374 case PHY_INTERFACE_MODE_RGMII_RXID
:
375 case PHY_INTERFACE_MODE_RGMII_TXID
:
376 case PHY_INTERFACE_MODE_RGMII_ID
:
377 case PHY_INTERFACE_MODE_RGMII
:
380 case PHY_INTERFACE_MODE_SGMII
:
393 out_be32(&uec_regs
->maccfg2
, maccfg2
);
394 out_be32(&uec
->uccf
->uf_regs
->upsmr
, upsmr
);
399 static int init_mii_management_configuration(uec_mii_t
*uec_mii_regs
)
401 uint timeout
= 0x1000;
404 miimcfg
= in_be32(&uec_mii_regs
->miimcfg
);
405 miimcfg
|= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE
;
406 out_be32(&uec_mii_regs
->miimcfg
, miimcfg
);
408 /* Wait until the bus is free */
409 while ((in_be32(&uec_mii_regs
->miimcfg
) & MIIMIND_BUSY
) && timeout
--);
411 printf("%s: The MII Bus is stuck!", __FUNCTION__
);
418 static int init_phy(struct eth_device
*dev
)
421 uec_mii_t
*umii_regs
;
422 struct uec_mii_info
*mii_info
;
423 struct phy_info
*curphy
;
426 uec
= (uec_private_t
*)dev
->priv
;
427 umii_regs
= uec
->uec_mii_regs
;
433 mii_info
= malloc(sizeof(*mii_info
));
435 printf("%s: Could not allocate mii_info", dev
->name
);
438 memset(mii_info
, 0, sizeof(*mii_info
));
440 if (uec
->uec_info
->uf_info
.eth_type
== GIGA_ETH
) {
441 mii_info
->speed
= SPEED_1000
;
443 mii_info
->speed
= SPEED_100
;
446 mii_info
->duplex
= DUPLEX_FULL
;
450 mii_info
->advertising
= (ADVERTISED_10baseT_Half
|
451 ADVERTISED_10baseT_Full
|
452 ADVERTISED_100baseT_Half
|
453 ADVERTISED_100baseT_Full
|
454 ADVERTISED_1000baseT_Full
);
455 mii_info
->autoneg
= 1;
456 mii_info
->mii_id
= uec
->uec_info
->phy_address
;
459 mii_info
->mdio_read
= &uec_read_phy_reg
;
460 mii_info
->mdio_write
= &uec_write_phy_reg
;
462 uec
->mii_info
= mii_info
;
464 qe_set_mii_clk_src(uec
->uec_info
->uf_info
.ucc_num
);
466 if (init_mii_management_configuration(umii_regs
)) {
467 printf("%s: The MII Bus is stuck!", dev
->name
);
472 /* get info for this PHY */
473 curphy
= uec_get_phy_info(uec
->mii_info
);
475 printf("%s: No PHY found", dev
->name
);
480 mii_info
->phyinfo
= curphy
;
482 /* Run the commands which initialize the PHY */
484 err
= curphy
->init(uec
->mii_info
);
498 static void adjust_link(struct eth_device
*dev
)
500 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
501 struct uec_mii_info
*mii_info
= uec
->mii_info
;
503 extern void change_phy_interface_mode(struct eth_device
*dev
,
504 phy_interface_t mode
, int speed
);
506 if (mii_info
->link
) {
507 /* Now we make sure that we can be in full duplex mode.
508 * If not, we operate in half-duplex mode. */
509 if (mii_info
->duplex
!= uec
->oldduplex
) {
510 if (!(mii_info
->duplex
)) {
511 uec_set_mac_duplex(uec
, DUPLEX_HALF
);
512 printf("%s: Half Duplex\n", dev
->name
);
514 uec_set_mac_duplex(uec
, DUPLEX_FULL
);
515 printf("%s: Full Duplex\n", dev
->name
);
517 uec
->oldduplex
= mii_info
->duplex
;
520 if (mii_info
->speed
!= uec
->oldspeed
) {
521 phy_interface_t mode
=
522 uec
->uec_info
->enet_interface_type
;
523 if (uec
->uec_info
->uf_info
.eth_type
== GIGA_ETH
) {
524 switch (mii_info
->speed
) {
528 printf ("switching to rgmii 100\n");
529 mode
= PHY_INTERFACE_MODE_RGMII
;
532 printf ("switching to rgmii 10\n");
533 mode
= PHY_INTERFACE_MODE_RGMII
;
536 printf("%s: Ack,Speed(%d)is illegal\n",
537 dev
->name
, mii_info
->speed
);
543 change_phy_interface_mode(dev
, mode
, mii_info
->speed
);
544 /* change the MAC interface mode */
545 uec_set_mac_if_mode(uec
, mode
, mii_info
->speed
);
547 printf("%s: Speed %dBT\n", dev
->name
, mii_info
->speed
);
548 uec
->oldspeed
= mii_info
->speed
;
552 printf("%s: Link is up\n", dev
->name
);
556 } else { /* if (mii_info->link) */
558 printf("%s: Link is down\n", dev
->name
);
566 static void phy_change(struct eth_device
*dev
)
568 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
570 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
571 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
573 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
574 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE9
);
575 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
578 /* Update the link, speed, duplex */
579 uec
->mii_info
->phyinfo
->read_status(uec
->mii_info
);
581 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
583 * QE12 is muxed with LBCTL, it needs to be released for enabling
584 * LBCTL signal for LBC usage.
586 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
589 /* Adjust the interface according to speed */
593 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
596 * Find a device index from the devlist by name
599 * The index where the device is located, -1 on error
601 static int uec_miiphy_find_dev_by_name(const char *devname
)
605 for (i
= 0; i
< MAXCONTROLLERS
; i
++) {
606 if (strncmp(devname
, devlist
[i
]->name
, strlen(devname
)) == 0) {
611 /* If device cannot be found, returns -1 */
612 if (i
== MAXCONTROLLERS
) {
613 debug ("%s: device %s not found in devlist\n", __FUNCTION__
, devname
);
621 * Read a MII PHY register.
626 static int uec_miiphy_read(const char *devname
, unsigned char addr
,
627 unsigned char reg
, unsigned short *value
)
631 if (devname
== NULL
|| value
== NULL
) {
632 debug("%s: NULL pointer given\n", __FUNCTION__
);
634 devindex
= uec_miiphy_find_dev_by_name(devname
);
636 *value
= uec_read_phy_reg(devlist
[devindex
], addr
, reg
);
643 * Write a MII PHY register.
648 static int uec_miiphy_write(const char *devname
, unsigned char addr
,
649 unsigned char reg
, unsigned short value
)
653 if (devname
== NULL
) {
654 debug("%s: NULL pointer given\n", __FUNCTION__
);
656 devindex
= uec_miiphy_find_dev_by_name(devname
);
658 uec_write_phy_reg(devlist
[devindex
], addr
, reg
, value
);
665 static int uec_set_mac_address(uec_private_t
*uec
, u8
*mac_addr
)
672 printf("%s: uec not initial\n", __FUNCTION__
);
676 uec_regs
= uec
->uec_regs
;
678 /* if a station address of 0x12345678ABCD, perform a write to
679 MACSTNADDR1 of 0xCDAB7856,
680 MACSTNADDR2 of 0x34120000 */
682 mac_addr1
= (mac_addr
[5] << 24) | (mac_addr
[4] << 16) | \
683 (mac_addr
[3] << 8) | (mac_addr
[2]);
684 out_be32(&uec_regs
->macstnaddr1
, mac_addr1
);
686 mac_addr2
= ((mac_addr
[1] << 24) | (mac_addr
[0] << 16)) & 0xffff0000;
687 out_be32(&uec_regs
->macstnaddr2
, mac_addr2
);
692 static int uec_convert_threads_num(uec_num_of_threads_e threads_num
,
693 int *threads_num_ret
)
695 int num_threads_numerica
;
697 switch (threads_num
) {
698 case UEC_NUM_OF_THREADS_1
:
699 num_threads_numerica
= 1;
701 case UEC_NUM_OF_THREADS_2
:
702 num_threads_numerica
= 2;
704 case UEC_NUM_OF_THREADS_4
:
705 num_threads_numerica
= 4;
707 case UEC_NUM_OF_THREADS_6
:
708 num_threads_numerica
= 6;
710 case UEC_NUM_OF_THREADS_8
:
711 num_threads_numerica
= 8;
714 printf("%s: Bad number of threads value.",
719 *threads_num_ret
= num_threads_numerica
;
724 static void uec_init_tx_parameter(uec_private_t
*uec
, int num_threads_tx
)
726 uec_info_t
*uec_info
;
731 uec_info
= uec
->uec_info
;
733 /* Alloc global Tx parameter RAM page */
734 uec
->tx_glbl_pram_offset
= qe_muram_alloc(
735 sizeof(uec_tx_global_pram_t
),
736 UEC_TX_GLOBAL_PRAM_ALIGNMENT
);
737 uec
->p_tx_glbl_pram
= (uec_tx_global_pram_t
*)
738 qe_muram_addr(uec
->tx_glbl_pram_offset
);
740 /* Zero the global Tx prameter RAM */
741 memset(uec
->p_tx_glbl_pram
, 0, sizeof(uec_tx_global_pram_t
));
743 /* Init global Tx parameter RAM */
745 /* TEMODER, RMON statistics disable, one Tx queue */
746 out_be16(&uec
->p_tx_glbl_pram
->temoder
, TEMODER_INIT_VALUE
);
749 uec
->send_q_mem_reg_offset
= qe_muram_alloc(
750 sizeof(uec_send_queue_qd_t
),
751 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
752 uec
->p_send_q_mem_reg
= (uec_send_queue_mem_region_t
*)
753 qe_muram_addr(uec
->send_q_mem_reg_offset
);
754 out_be32(&uec
->p_tx_glbl_pram
->sqptr
, uec
->send_q_mem_reg_offset
);
756 /* Setup the table with TxBDs ring */
757 end_bd
= (u32
)uec
->p_tx_bd_ring
+ (uec_info
->tx_bd_ring_len
- 1)
759 out_be32(&uec
->p_send_q_mem_reg
->sqqd
[0].bd_ring_base
,
760 (u32
)(uec
->p_tx_bd_ring
));
761 out_be32(&uec
->p_send_q_mem_reg
->sqqd
[0].last_bd_completed_address
,
764 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
765 out_be32(&uec
->p_tx_glbl_pram
->schedulerbasepointer
, 0);
767 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
768 out_be32(&uec
->p_tx_glbl_pram
->txrmonbaseptr
, 0);
770 /* TSTATE, global snooping, big endian, the CSB bus selected */
771 bmrx
= BMR_INIT_VALUE
;
772 out_be32(&uec
->p_tx_glbl_pram
->tstate
, ((u32
)(bmrx
) << BMR_SHIFT
));
775 for (i
= 0; i
< MAX_IPH_OFFSET_ENTRY
; i
++) {
776 out_8(&uec
->p_tx_glbl_pram
->iphoffset
[i
], 0);
780 for (i
= 0; i
< UEC_TX_VTAG_TABLE_ENTRY_MAX
; i
++) {
781 out_be32(&uec
->p_tx_glbl_pram
->vtagtable
[i
], 0);
785 uec
->thread_dat_tx_offset
= qe_muram_alloc(
786 num_threads_tx
* sizeof(uec_thread_data_tx_t
) +
787 32 *(num_threads_tx
== 1), UEC_THREAD_DATA_ALIGNMENT
);
789 uec
->p_thread_data_tx
= (uec_thread_data_tx_t
*)
790 qe_muram_addr(uec
->thread_dat_tx_offset
);
791 out_be32(&uec
->p_tx_glbl_pram
->tqptr
, uec
->thread_dat_tx_offset
);
794 static void uec_init_rx_parameter(uec_private_t
*uec
, int num_threads_rx
)
798 uec_82xx_address_filtering_pram_t
*p_af_pram
;
800 /* Allocate global Rx parameter RAM page */
801 uec
->rx_glbl_pram_offset
= qe_muram_alloc(
802 sizeof(uec_rx_global_pram_t
), UEC_RX_GLOBAL_PRAM_ALIGNMENT
);
803 uec
->p_rx_glbl_pram
= (uec_rx_global_pram_t
*)
804 qe_muram_addr(uec
->rx_glbl_pram_offset
);
806 /* Zero Global Rx parameter RAM */
807 memset(uec
->p_rx_glbl_pram
, 0, sizeof(uec_rx_global_pram_t
));
809 /* Init global Rx parameter RAM */
810 /* REMODER, Extended feature mode disable, VLAN disable,
811 LossLess flow control disable, Receive firmware statisic disable,
812 Extended address parsing mode disable, One Rx queues,
813 Dynamic maximum/minimum frame length disable, IP checksum check
814 disable, IP address alignment disable
816 out_be32(&uec
->p_rx_glbl_pram
->remoder
, REMODER_INIT_VALUE
);
819 uec
->thread_dat_rx_offset
= qe_muram_alloc(
820 num_threads_rx
* sizeof(uec_thread_data_rx_t
),
821 UEC_THREAD_DATA_ALIGNMENT
);
822 uec
->p_thread_data_rx
= (uec_thread_data_rx_t
*)
823 qe_muram_addr(uec
->thread_dat_rx_offset
);
824 out_be32(&uec
->p_rx_glbl_pram
->rqptr
, uec
->thread_dat_rx_offset
);
827 out_be16(&uec
->p_rx_glbl_pram
->typeorlen
, 3072);
829 /* RxRMON base pointer, we don't need it */
830 out_be32(&uec
->p_rx_glbl_pram
->rxrmonbaseptr
, 0);
832 /* IntCoalescingPTR, we don't need it, no interrupt */
833 out_be32(&uec
->p_rx_glbl_pram
->intcoalescingptr
, 0);
835 /* RSTATE, global snooping, big endian, the CSB bus selected */
836 bmrx
= BMR_INIT_VALUE
;
837 out_8(&uec
->p_rx_glbl_pram
->rstate
, bmrx
);
840 out_be16(&uec
->p_rx_glbl_pram
->mrblr
, MAX_RXBUF_LEN
);
843 uec
->rx_bd_qs_tbl_offset
= qe_muram_alloc(
844 sizeof(uec_rx_bd_queues_entry_t
) + \
845 sizeof(uec_rx_prefetched_bds_t
),
846 UEC_RX_BD_QUEUES_ALIGNMENT
);
847 uec
->p_rx_bd_qs_tbl
= (uec_rx_bd_queues_entry_t
*)
848 qe_muram_addr(uec
->rx_bd_qs_tbl_offset
);
851 memset(uec
->p_rx_bd_qs_tbl
, 0, sizeof(uec_rx_bd_queues_entry_t
) + \
852 sizeof(uec_rx_prefetched_bds_t
));
853 out_be32(&uec
->p_rx_glbl_pram
->rbdqptr
, uec
->rx_bd_qs_tbl_offset
);
854 out_be32(&uec
->p_rx_bd_qs_tbl
->externalbdbaseptr
,
855 (u32
)uec
->p_rx_bd_ring
);
858 out_be16(&uec
->p_rx_glbl_pram
->mflr
, MAX_FRAME_LEN
);
860 out_be16(&uec
->p_rx_glbl_pram
->minflr
, MIN_FRAME_LEN
);
862 out_be16(&uec
->p_rx_glbl_pram
->maxd1
, MAX_DMA1_LEN
);
864 out_be16(&uec
->p_rx_glbl_pram
->maxd2
, MAX_DMA2_LEN
);
866 out_be32(&uec
->p_rx_glbl_pram
->ecamptr
, 0);
868 out_be32(&uec
->p_rx_glbl_pram
->l2qt
, 0);
870 for (i
= 0; i
< 8; i
++) {
871 out_be32(&uec
->p_rx_glbl_pram
->l3qt
[i
], 0);
875 out_be16(&uec
->p_rx_glbl_pram
->vlantype
, 0x8100);
877 out_be16(&uec
->p_rx_glbl_pram
->vlantci
, 0);
879 /* Clear PQ2 style address filtering hash table */
880 p_af_pram
= (uec_82xx_address_filtering_pram_t
*) \
881 uec
->p_rx_glbl_pram
->addressfiltering
;
883 p_af_pram
->iaddr_h
= 0;
884 p_af_pram
->iaddr_l
= 0;
885 p_af_pram
->gaddr_h
= 0;
886 p_af_pram
->gaddr_l
= 0;
889 static int uec_issue_init_enet_rxtx_cmd(uec_private_t
*uec
,
890 int thread_tx
, int thread_rx
)
892 uec_init_cmd_pram_t
*p_init_enet_param
;
893 u32 init_enet_param_offset
;
894 uec_info_t
*uec_info
;
897 u32 init_enet_offset
;
902 uec_info
= uec
->uec_info
;
904 /* Allocate init enet command parameter */
905 uec
->init_enet_param_offset
= qe_muram_alloc(
906 sizeof(uec_init_cmd_pram_t
), 4);
907 init_enet_param_offset
= uec
->init_enet_param_offset
;
908 uec
->p_init_enet_param
= (uec_init_cmd_pram_t
*)
909 qe_muram_addr(uec
->init_enet_param_offset
);
911 /* Zero init enet command struct */
912 memset((void *)uec
->p_init_enet_param
, 0, sizeof(uec_init_cmd_pram_t
));
914 /* Init the command struct */
915 p_init_enet_param
= uec
->p_init_enet_param
;
916 p_init_enet_param
->resinit0
= ENET_INIT_PARAM_MAGIC_RES_INIT0
;
917 p_init_enet_param
->resinit1
= ENET_INIT_PARAM_MAGIC_RES_INIT1
;
918 p_init_enet_param
->resinit2
= ENET_INIT_PARAM_MAGIC_RES_INIT2
;
919 p_init_enet_param
->resinit3
= ENET_INIT_PARAM_MAGIC_RES_INIT3
;
920 p_init_enet_param
->resinit4
= ENET_INIT_PARAM_MAGIC_RES_INIT4
;
921 p_init_enet_param
->largestexternallookupkeysize
= 0;
923 p_init_enet_param
->rgftgfrxglobal
|= ((u32
)uec_info
->num_threads_rx
)
924 << ENET_INIT_PARAM_RGF_SHIFT
;
925 p_init_enet_param
->rgftgfrxglobal
|= ((u32
)uec_info
->num_threads_tx
)
926 << ENET_INIT_PARAM_TGF_SHIFT
;
928 /* Init Rx global parameter pointer */
929 p_init_enet_param
->rgftgfrxglobal
|= uec
->rx_glbl_pram_offset
|
930 (u32
)uec_info
->risc_rx
;
932 /* Init Rx threads */
933 for (i
= 0; i
< (thread_rx
+ 1); i
++) {
934 if ((snum
= qe_get_snum()) < 0) {
935 printf("%s can not get snum\n", __FUNCTION__
);
940 init_enet_offset
= 0;
942 init_enet_offset
= qe_muram_alloc(
943 sizeof(uec_thread_rx_pram_t
),
944 UEC_THREAD_RX_PRAM_ALIGNMENT
);
947 entry_val
= ((u32
)snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) |
948 init_enet_offset
| (u32
)uec_info
->risc_rx
;
949 p_init_enet_param
->rxthread
[i
] = entry_val
;
952 /* Init Tx global parameter pointer */
953 p_init_enet_param
->txglobal
= uec
->tx_glbl_pram_offset
|
954 (u32
)uec_info
->risc_tx
;
956 /* Init Tx threads */
957 for (i
= 0; i
< thread_tx
; i
++) {
958 if ((snum
= qe_get_snum()) < 0) {
959 printf("%s can not get snum\n", __FUNCTION__
);
963 init_enet_offset
= qe_muram_alloc(sizeof(uec_thread_tx_pram_t
),
964 UEC_THREAD_TX_PRAM_ALIGNMENT
);
966 entry_val
= ((u32
)snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) |
967 init_enet_offset
| (u32
)uec_info
->risc_tx
;
968 p_init_enet_param
->txthread
[i
] = entry_val
;
971 __asm__
__volatile__("sync");
973 /* Issue QE command */
974 command
= QE_INIT_TX_RX
;
975 cecr_subblock
= ucc_fast_get_qe_cr_subblock(
976 uec
->uec_info
->uf_info
.ucc_num
);
977 qe_issue_cmd(command
, cecr_subblock
, (u8
) QE_CR_PROTOCOL_ETHERNET
,
978 init_enet_param_offset
);
983 static int uec_startup(uec_private_t
*uec
)
985 uec_info_t
*uec_info
;
986 ucc_fast_info_t
*uf_info
;
987 ucc_fast_private_t
*uccf
;
999 if (!uec
|| !uec
->uec_info
) {
1000 printf("%s: uec or uec_info not initial\n", __FUNCTION__
);
1004 uec_info
= uec
->uec_info
;
1005 uf_info
= &(uec_info
->uf_info
);
1007 /* Check if Rx BD ring len is illegal */
1008 if ((uec_info
->rx_bd_ring_len
< UEC_RX_BD_RING_SIZE_MIN
) || \
1009 (uec_info
->rx_bd_ring_len
% UEC_RX_BD_RING_SIZE_ALIGNMENT
)) {
1010 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
1015 /* Check if Tx BD ring len is illegal */
1016 if (uec_info
->tx_bd_ring_len
< UEC_TX_BD_RING_SIZE_MIN
) {
1017 printf("%s: Tx BD ring length must not be smaller than 2.\n",
1022 /* Check if MRBLR is illegal */
1023 if ((MAX_RXBUF_LEN
== 0) || (MAX_RXBUF_LEN
% UEC_MRBLR_ALIGNMENT
)) {
1024 printf("%s: max rx buffer length must be mutliple of 128.\n",
1029 /* Both Rx and Tx are stopped */
1030 uec
->grace_stopped_rx
= 1;
1031 uec
->grace_stopped_tx
= 1;
1034 if (ucc_fast_init(uf_info
, &uccf
)) {
1035 printf("%s: failed to init ucc fast\n", __FUNCTION__
);
1042 /* Convert the Tx threads number */
1043 if (uec_convert_threads_num(uec_info
->num_threads_tx
,
1048 /* Convert the Rx threads number */
1049 if (uec_convert_threads_num(uec_info
->num_threads_rx
,
1054 uf_regs
= uccf
->uf_regs
;
1056 /* UEC register is following UCC fast registers */
1057 uec_regs
= (uec_t
*)(&uf_regs
->ucc_eth
);
1059 /* Save the UEC register pointer to UEC private struct */
1060 uec
->uec_regs
= uec_regs
;
1062 /* Init UPSMR, enable hardware statistics (UCC) */
1063 out_be32(&uec
->uccf
->uf_regs
->upsmr
, UPSMR_INIT_VALUE
);
1065 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1066 out_be32(&uec_regs
->maccfg1
, MACCFG1_INIT_VALUE
);
1068 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1069 out_be32(&uec_regs
->maccfg2
, MACCFG2_INIT_VALUE
);
1071 /* Setup MAC interface mode */
1072 uec_set_mac_if_mode(uec
, uec_info
->enet_interface_type
, uec_info
->speed
);
1074 /* Setup MII management base */
1075 #ifndef CONFIG_eTSEC_MDIO_BUS
1076 uec
->uec_mii_regs
= (uec_mii_t
*)(&uec_regs
->miimcfg
);
1078 uec
->uec_mii_regs
= (uec_mii_t
*) CONFIG_MIIM_ADDRESS
;
1081 /* Setup MII master clock source */
1082 qe_set_mii_clk_src(uec_info
->uf_info
.ucc_num
);
1085 utbipar
= in_be32(&uec_regs
->utbipar
);
1086 utbipar
&= ~UTBIPAR_PHY_ADDRESS_MASK
;
1088 /* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
1089 * This frees up the remaining SMI addresses for use.
1091 utbipar
|= CONFIG_UTBIPAR_INIT_TBIPA
<< UTBIPAR_PHY_ADDRESS_SHIFT
;
1092 out_be32(&uec_regs
->utbipar
, utbipar
);
1094 /* Configure the TBI for SGMII operation */
1095 if ((uec
->uec_info
->enet_interface_type
== PHY_INTERFACE_MODE_SGMII
) &&
1096 (uec
->uec_info
->speed
== SPEED_1000
)) {
1097 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1098 ENET_TBI_MII_ANA
, TBIANA_SETTINGS
);
1100 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1101 ENET_TBI_MII_TBICON
, TBICON_CLK_SELECT
);
1103 uec_write_phy_reg(uec
->dev
, uec_regs
->utbipar
,
1104 ENET_TBI_MII_CR
, TBICR_SETTINGS
);
1107 /* Allocate Tx BDs */
1108 length
= ((uec_info
->tx_bd_ring_len
* SIZEOFBD
) /
1109 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
) *
1110 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
1111 if ((uec_info
->tx_bd_ring_len
* SIZEOFBD
) %
1112 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
) {
1113 length
+= UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
1116 align
= UEC_TX_BD_RING_ALIGNMENT
;
1117 uec
->tx_bd_ring_offset
= (u32
)malloc((u32
)(length
+ align
));
1118 if (uec
->tx_bd_ring_offset
!= 0) {
1119 uec
->p_tx_bd_ring
= (u8
*)((uec
->tx_bd_ring_offset
+ align
)
1123 /* Zero all of Tx BDs */
1124 memset((void *)(uec
->tx_bd_ring_offset
), 0, length
+ align
);
1126 /* Allocate Rx BDs */
1127 length
= uec_info
->rx_bd_ring_len
* SIZEOFBD
;
1128 align
= UEC_RX_BD_RING_ALIGNMENT
;
1129 uec
->rx_bd_ring_offset
= (u32
)(malloc((u32
)(length
+ align
)));
1130 if (uec
->rx_bd_ring_offset
!= 0) {
1131 uec
->p_rx_bd_ring
= (u8
*)((uec
->rx_bd_ring_offset
+ align
)
1135 /* Zero all of Rx BDs */
1136 memset((void *)(uec
->rx_bd_ring_offset
), 0, length
+ align
);
1138 /* Allocate Rx buffer */
1139 length
= uec_info
->rx_bd_ring_len
* MAX_RXBUF_LEN
;
1140 align
= UEC_RX_DATA_BUF_ALIGNMENT
;
1141 uec
->rx_buf_offset
= (u32
)malloc(length
+ align
);
1142 if (uec
->rx_buf_offset
!= 0) {
1143 uec
->p_rx_buf
= (u8
*)((uec
->rx_buf_offset
+ align
)
1147 /* Zero all of the Rx buffer */
1148 memset((void *)(uec
->rx_buf_offset
), 0, length
+ align
);
1150 /* Init TxBD ring */
1151 bd
= (qe_bd_t
*)uec
->p_tx_bd_ring
;
1154 for (i
= 0; i
< uec_info
->tx_bd_ring_len
; i
++) {
1156 BD_STATUS_SET(bd
, 0);
1157 BD_LENGTH_SET(bd
, 0);
1160 BD_STATUS_SET((--bd
), TxBD_WRAP
);
1162 /* Init RxBD ring */
1163 bd
= (qe_bd_t
*)uec
->p_rx_bd_ring
;
1165 buf
= uec
->p_rx_buf
;
1166 for (i
= 0; i
< uec_info
->rx_bd_ring_len
; i
++) {
1167 BD_DATA_SET(bd
, buf
);
1168 BD_LENGTH_SET(bd
, 0);
1169 BD_STATUS_SET(bd
, RxBD_EMPTY
);
1170 buf
+= MAX_RXBUF_LEN
;
1173 BD_STATUS_SET((--bd
), RxBD_WRAP
| RxBD_EMPTY
);
1175 /* Init global Tx parameter RAM */
1176 uec_init_tx_parameter(uec
, num_threads_tx
);
1178 /* Init global Rx parameter RAM */
1179 uec_init_rx_parameter(uec
, num_threads_rx
);
1181 /* Init ethernet Tx and Rx parameter command */
1182 if (uec_issue_init_enet_rxtx_cmd(uec
, num_threads_tx
,
1184 printf("%s issue init enet cmd failed\n", __FUNCTION__
);
1191 static int uec_init(struct eth_device
* dev
, bd_t
*bd
)
1195 struct phy_info
*curphy
;
1196 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
1197 ccsr_gur_t
*gur
= (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR
);
1200 uec
= (uec_private_t
*)dev
->priv
;
1202 if (uec
->the_first_run
== 0) {
1203 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
1204 /* QE9 and QE12 need to be set for enabling QE MII managment signals */
1205 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE9
);
1206 setbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
1209 err
= init_phy(dev
);
1211 printf("%s: Cannot initialize PHY, aborting.\n",
1216 curphy
= uec
->mii_info
->phyinfo
;
1218 if (curphy
->config_aneg
) {
1219 err
= curphy
->config_aneg(uec
->mii_info
);
1221 printf("%s: Can't negotiate PHY\n", dev
->name
);
1226 /* Give PHYs up to 5 sec to report a link */
1229 err
= curphy
->read_status(uec
->mii_info
);
1230 if (!(((i
-- > 0) && !uec
->mii_info
->link
) || err
))
1235 #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
1236 /* QE12 needs to be released for enabling LBCTL signal*/
1237 clrbits_be32(&gur
->pmuxcr
, MPC85xx_PMUXCR_QE12
);
1241 printf("warning: %s: timeout on PHY link\n", dev
->name
);
1244 uec
->the_first_run
= 1;
1247 /* Set up the MAC address */
1248 if (dev
->enetaddr
[0] & 0x01) {
1249 printf("%s: MacAddress is multcast address\n",
1253 uec_set_mac_address(uec
, dev
->enetaddr
);
1256 err
= uec_open(uec
, COMM_DIR_RX_AND_TX
);
1258 printf("%s: cannot enable UEC device\n", dev
->name
);
1264 return (uec
->mii_info
->link
? 0 : -1);
1267 static void uec_halt(struct eth_device
* dev
)
1269 uec_private_t
*uec
= (uec_private_t
*)dev
->priv
;
1270 uec_stop(uec
, COMM_DIR_RX_AND_TX
);
1273 static int uec_send(struct eth_device
*dev
, void *buf
, int len
)
1276 ucc_fast_private_t
*uccf
;
1277 volatile qe_bd_t
*bd
;
1282 uec
= (uec_private_t
*)dev
->priv
;
1286 /* Find an empty TxBD */
1287 for (i
= 0; bd
->status
& TxBD_READY
; i
++) {
1289 printf("%s: tx buffer not ready\n", dev
->name
);
1295 BD_DATA_SET(bd
, buf
);
1296 BD_LENGTH_SET(bd
, len
);
1297 status
= bd
->status
;
1299 status
|= (TxBD_READY
| TxBD_LAST
);
1300 BD_STATUS_SET(bd
, status
);
1302 /* Tell UCC to transmit the buffer */
1303 ucc_fast_transmit_on_demand(uccf
);
1305 /* Wait for buffer to be transmitted */
1306 for (i
= 0; bd
->status
& TxBD_READY
; i
++) {
1308 printf("%s: tx error\n", dev
->name
);
1313 /* Ok, the buffer be transimitted */
1314 BD_ADVANCE(bd
, status
, uec
->p_tx_bd_ring
);
1321 static int uec_recv(struct eth_device
* dev
)
1323 uec_private_t
*uec
= dev
->priv
;
1324 volatile qe_bd_t
*bd
;
1330 status
= bd
->status
;
1332 while (!(status
& RxBD_EMPTY
)) {
1333 if (!(status
& RxBD_ERROR
)) {
1335 len
= BD_LENGTH(bd
);
1336 NetReceive(data
, len
);
1338 printf("%s: Rx error\n", dev
->name
);
1341 BD_LENGTH_SET(bd
, 0);
1342 BD_STATUS_SET(bd
, status
| RxBD_EMPTY
);
1343 BD_ADVANCE(bd
, status
, uec
->p_rx_bd_ring
);
1344 status
= bd
->status
;
1351 int uec_initialize(bd_t
*bis
, uec_info_t
*uec_info
)
1353 struct eth_device
*dev
;
1358 dev
= (struct eth_device
*)malloc(sizeof(struct eth_device
));
1361 memset(dev
, 0, sizeof(struct eth_device
));
1363 /* Allocate the UEC private struct */
1364 uec
= (uec_private_t
*)malloc(sizeof(uec_private_t
));
1368 memset(uec
, 0, sizeof(uec_private_t
));
1370 /* Adjust uec_info */
1371 #if (MAX_QE_RISC == 4)
1372 uec_info
->risc_tx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
1373 uec_info
->risc_rx
= QE_RISC_ALLOCATION_FOUR_RISCS
;
1376 devlist
[uec_info
->uf_info
.ucc_num
] = dev
;
1378 uec
->uec_info
= uec_info
;
1381 sprintf(dev
->name
, "UEC%d", uec_info
->uf_info
.ucc_num
);
1383 dev
->priv
= (void *)uec
;
1384 dev
->init
= uec_init
;
1385 dev
->halt
= uec_halt
;
1386 dev
->send
= uec_send
;
1387 dev
->recv
= uec_recv
;
1389 /* Clear the ethnet address */
1390 for (i
= 0; i
< 6; i
++)
1391 dev
->enetaddr
[i
] = 0;
1395 err
= uec_startup(uec
);
1397 printf("%s: Cannot configure net device, aborting.",dev
->name
);
1401 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1402 miiphy_register(dev
->name
, uec_miiphy_read
, uec_miiphy_write
);
1408 int uec_eth_init(bd_t
*bis
, uec_info_t
*uecs
, int num
)
1412 for (i
= 0; i
< num
; i
++)
1413 uec_initialize(bis
, &uecs
[i
]);
1418 int uec_standard_init(bd_t
*bis
)
1420 return uec_eth_init(bis
, uec_info
, ARRAY_SIZE(uec_info
));