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Merge git://www.denx.de/git/u-boot
[people/ms/u-boot.git] / drivers / qe / uec.c
1 /*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32
33 #if defined(CONFIG_QE)
34
35 #ifdef CONFIG_UEC_ETH1
36 static uec_info_t eth1_uec_info = {
37 .uf_info = {
38 .ucc_num = CFG_UEC1_UCC_NUM,
39 .rx_clock = CFG_UEC1_RX_CLK,
40 .tx_clock = CFG_UEC1_TX_CLK,
41 .eth_type = CFG_UEC1_ETH_TYPE,
42 },
43 .num_threads_tx = UEC_NUM_OF_THREADS_4,
44 .num_threads_rx = UEC_NUM_OF_THREADS_4,
45 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
46 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
47 .tx_bd_ring_len = 16,
48 .rx_bd_ring_len = 16,
49 .phy_address = CFG_UEC1_PHY_ADDR,
50 .enet_interface = CFG_UEC1_INTERFACE_MODE,
51 };
52 #endif
53 #ifdef CONFIG_UEC_ETH2
54 static uec_info_t eth2_uec_info = {
55 .uf_info = {
56 .ucc_num = CFG_UEC2_UCC_NUM,
57 .rx_clock = CFG_UEC2_RX_CLK,
58 .tx_clock = CFG_UEC2_TX_CLK,
59 .eth_type = CFG_UEC2_ETH_TYPE,
60 },
61 .num_threads_tx = UEC_NUM_OF_THREADS_4,
62 .num_threads_rx = UEC_NUM_OF_THREADS_4,
63 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
64 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
65 .tx_bd_ring_len = 16,
66 .rx_bd_ring_len = 16,
67 .phy_address = CFG_UEC2_PHY_ADDR,
68 .enet_interface = CFG_UEC2_INTERFACE_MODE,
69 };
70 #endif
71
72 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
73 {
74 uec_t *uec_regs;
75 u32 maccfg1;
76
77 if (!uec) {
78 printf("%s: uec not initial\n", __FUNCTION__);
79 return -EINVAL;
80 }
81 uec_regs = uec->uec_regs;
82
83 maccfg1 = in_be32(&uec_regs->maccfg1);
84
85 if (mode & COMM_DIR_TX) {
86 maccfg1 |= MACCFG1_ENABLE_TX;
87 out_be32(&uec_regs->maccfg1, maccfg1);
88 uec->mac_tx_enabled = 1;
89 }
90
91 if (mode & COMM_DIR_RX) {
92 maccfg1 |= MACCFG1_ENABLE_RX;
93 out_be32(&uec_regs->maccfg1, maccfg1);
94 uec->mac_rx_enabled = 1;
95 }
96
97 return 0;
98 }
99
100 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
101 {
102 uec_t *uec_regs;
103 u32 maccfg1;
104
105 if (!uec) {
106 printf("%s: uec not initial\n", __FUNCTION__);
107 return -EINVAL;
108 }
109 uec_regs = uec->uec_regs;
110
111 maccfg1 = in_be32(&uec_regs->maccfg1);
112
113 if (mode & COMM_DIR_TX) {
114 maccfg1 &= ~MACCFG1_ENABLE_TX;
115 out_be32(&uec_regs->maccfg1, maccfg1);
116 uec->mac_tx_enabled = 0;
117 }
118
119 if (mode & COMM_DIR_RX) {
120 maccfg1 &= ~MACCFG1_ENABLE_RX;
121 out_be32(&uec_regs->maccfg1, maccfg1);
122 uec->mac_rx_enabled = 0;
123 }
124
125 return 0;
126 }
127
128 static int uec_graceful_stop_tx(uec_private_t *uec)
129 {
130 ucc_fast_t *uf_regs;
131 u32 cecr_subblock;
132 u32 ucce;
133
134 if (!uec || !uec->uccf) {
135 printf("%s: No handle passed.\n", __FUNCTION__);
136 return -EINVAL;
137 }
138
139 uf_regs = uec->uccf->uf_regs;
140
141 /* Clear the grace stop event */
142 out_be32(&uf_regs->ucce, UCCE_GRA);
143
144 /* Issue host command */
145 cecr_subblock =
146 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
147 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
148 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
149
150 /* Wait for command to complete */
151 do {
152 ucce = in_be32(&uf_regs->ucce);
153 } while (! (ucce & UCCE_GRA));
154
155 uec->grace_stopped_tx = 1;
156
157 return 0;
158 }
159
160 static int uec_graceful_stop_rx(uec_private_t *uec)
161 {
162 u32 cecr_subblock;
163 u8 ack;
164
165 if (!uec) {
166 printf("%s: No handle passed.\n", __FUNCTION__);
167 return -EINVAL;
168 }
169
170 if (!uec->p_rx_glbl_pram) {
171 printf("%s: No init rx global parameter\n", __FUNCTION__);
172 return -EINVAL;
173 }
174
175 /* Clear acknowledge bit */
176 ack = uec->p_rx_glbl_pram->rxgstpack;
177 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
178 uec->p_rx_glbl_pram->rxgstpack = ack;
179
180 /* Keep issuing cmd and checking ack bit until it is asserted */
181 do {
182 /* Issue host command */
183 cecr_subblock =
184 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
185 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
186 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
187 ack = uec->p_rx_glbl_pram->rxgstpack;
188 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
189
190 uec->grace_stopped_rx = 1;
191
192 return 0;
193 }
194
195 static int uec_restart_tx(uec_private_t *uec)
196 {
197 u32 cecr_subblock;
198
199 if (!uec || !uec->uec_info) {
200 printf("%s: No handle passed.\n", __FUNCTION__);
201 return -EINVAL;
202 }
203
204 cecr_subblock =
205 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
206 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
207 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
208
209 uec->grace_stopped_tx = 0;
210
211 return 0;
212 }
213
214 static int uec_restart_rx(uec_private_t *uec)
215 {
216 u32 cecr_subblock;
217
218 if (!uec || !uec->uec_info) {
219 printf("%s: No handle passed.\n", __FUNCTION__);
220 return -EINVAL;
221 }
222
223 cecr_subblock =
224 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
225 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
226 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
227
228 uec->grace_stopped_rx = 0;
229
230 return 0;
231 }
232
233 static int uec_open(uec_private_t *uec, comm_dir_e mode)
234 {
235 ucc_fast_private_t *uccf;
236
237 if (!uec || !uec->uccf) {
238 printf("%s: No handle passed.\n", __FUNCTION__);
239 return -EINVAL;
240 }
241 uccf = uec->uccf;
242
243 /* check if the UCC number is in range. */
244 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
245 printf("%s: ucc_num out of range.\n", __FUNCTION__);
246 return -EINVAL;
247 }
248
249 /* Enable MAC */
250 uec_mac_enable(uec, mode);
251
252 /* Enable UCC fast */
253 ucc_fast_enable(uccf, mode);
254
255 /* RISC microcode start */
256 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
257 uec_restart_tx(uec);
258 }
259 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
260 uec_restart_rx(uec);
261 }
262
263 return 0;
264 }
265
266 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
267 {
268 ucc_fast_private_t *uccf;
269
270 if (!uec || !uec->uccf) {
271 printf("%s: No handle passed.\n", __FUNCTION__);
272 return -EINVAL;
273 }
274 uccf = uec->uccf;
275
276 /* check if the UCC number is in range. */
277 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
278 printf("%s: ucc_num out of range.\n", __FUNCTION__);
279 return -EINVAL;
280 }
281 /* Stop any transmissions */
282 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
283 uec_graceful_stop_tx(uec);
284 }
285 /* Stop any receptions */
286 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
287 uec_graceful_stop_rx(uec);
288 }
289
290 /* Disable the UCC fast */
291 ucc_fast_disable(uec->uccf, mode);
292
293 /* Disable the MAC */
294 uec_mac_disable(uec, mode);
295
296 return 0;
297 }
298
299 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
300 {
301 uec_t *uec_regs;
302 u32 maccfg2;
303
304 if (!uec) {
305 printf("%s: uec not initial\n", __FUNCTION__);
306 return -EINVAL;
307 }
308 uec_regs = uec->uec_regs;
309
310 if (duplex == DUPLEX_HALF) {
311 maccfg2 = in_be32(&uec_regs->maccfg2);
312 maccfg2 &= ~MACCFG2_FDX;
313 out_be32(&uec_regs->maccfg2, maccfg2);
314 }
315
316 if (duplex == DUPLEX_FULL) {
317 maccfg2 = in_be32(&uec_regs->maccfg2);
318 maccfg2 |= MACCFG2_FDX;
319 out_be32(&uec_regs->maccfg2, maccfg2);
320 }
321
322 return 0;
323 }
324
325 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
326 {
327 enet_interface_e enet_if_mode;
328 uec_info_t *uec_info;
329 uec_t *uec_regs;
330 u32 upsmr;
331 u32 maccfg2;
332
333 if (!uec) {
334 printf("%s: uec not initial\n", __FUNCTION__);
335 return -EINVAL;
336 }
337
338 uec_info = uec->uec_info;
339 uec_regs = uec->uec_regs;
340 enet_if_mode = if_mode;
341
342 maccfg2 = in_be32(&uec_regs->maccfg2);
343 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
344
345 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
346 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
347
348 switch (enet_if_mode) {
349 case ENET_100_MII:
350 case ENET_10_MII:
351 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
352 break;
353 case ENET_1000_GMII:
354 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
355 break;
356 case ENET_1000_TBI:
357 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
358 upsmr |= UPSMR_TBIM;
359 break;
360 case ENET_1000_RTBI:
361 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
362 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
363 break;
364 case ENET_1000_RGMII:
365 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
366 upsmr |= UPSMR_RPM;
367 break;
368 case ENET_100_RGMII:
369 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
370 upsmr |= UPSMR_RPM;
371 break;
372 case ENET_10_RGMII:
373 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
374 upsmr |= (UPSMR_RPM | UPSMR_R10M);
375 break;
376 case ENET_100_RMII:
377 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
378 upsmr |= UPSMR_RMM;
379 break;
380 case ENET_10_RMII:
381 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
382 upsmr |= (UPSMR_R10M | UPSMR_RMM);
383 break;
384 default:
385 return -EINVAL;
386 break;
387 }
388 out_be32(&uec_regs->maccfg2, maccfg2);
389 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
390
391 return 0;
392 }
393
394 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
395 {
396 uint timeout = 0x1000;
397 u32 miimcfg = 0;
398
399 miimcfg = in_be32(&uec_mii_regs->miimcfg);
400 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
401 out_be32(&uec_mii_regs->miimcfg, miimcfg);
402
403 /* Wait until the bus is free */
404 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
405 if (timeout <= 0) {
406 printf("%s: The MII Bus is stuck!", __FUNCTION__);
407 return -ETIMEDOUT;
408 }
409
410 return 0;
411 }
412
413 static int init_phy(struct eth_device *dev)
414 {
415 uec_private_t *uec;
416 uec_mii_t *umii_regs;
417 struct uec_mii_info *mii_info;
418 struct phy_info *curphy;
419 int err;
420
421 uec = (uec_private_t *)dev->priv;
422 umii_regs = uec->uec_mii_regs;
423
424 uec->oldlink = 0;
425 uec->oldspeed = 0;
426 uec->oldduplex = -1;
427
428 mii_info = malloc(sizeof(*mii_info));
429 if (!mii_info) {
430 printf("%s: Could not allocate mii_info", dev->name);
431 return -ENOMEM;
432 }
433 memset(mii_info, 0, sizeof(*mii_info));
434
435 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
436 mii_info->speed = SPEED_1000;
437 } else {
438 mii_info->speed = SPEED_100;
439 }
440
441 mii_info->duplex = DUPLEX_FULL;
442 mii_info->pause = 0;
443 mii_info->link = 1;
444
445 mii_info->advertising = (ADVERTISED_10baseT_Half |
446 ADVERTISED_10baseT_Full |
447 ADVERTISED_100baseT_Half |
448 ADVERTISED_100baseT_Full |
449 ADVERTISED_1000baseT_Full);
450 mii_info->autoneg = 1;
451 mii_info->mii_id = uec->uec_info->phy_address;
452 mii_info->dev = dev;
453
454 mii_info->mdio_read = &uec_read_phy_reg;
455 mii_info->mdio_write = &uec_write_phy_reg;
456
457 uec->mii_info = mii_info;
458
459 if (init_mii_management_configuration(umii_regs)) {
460 printf("%s: The MII Bus is stuck!", dev->name);
461 err = -1;
462 goto bus_fail;
463 }
464
465 /* get info for this PHY */
466 curphy = uec_get_phy_info(uec->mii_info);
467 if (!curphy) {
468 printf("%s: No PHY found", dev->name);
469 err = -1;
470 goto no_phy;
471 }
472
473 mii_info->phyinfo = curphy;
474
475 /* Run the commands which initialize the PHY */
476 if (curphy->init) {
477 err = curphy->init(uec->mii_info);
478 if (err)
479 goto phy_init_fail;
480 }
481
482 return 0;
483
484 phy_init_fail:
485 no_phy:
486 bus_fail:
487 free(mii_info);
488 return err;
489 }
490
491 static void adjust_link(struct eth_device *dev)
492 {
493 uec_private_t *uec = (uec_private_t *)dev->priv;
494 uec_t *uec_regs;
495 struct uec_mii_info *mii_info = uec->mii_info;
496
497 extern void change_phy_interface_mode(struct eth_device *dev,
498 enet_interface_e mode);
499 uec_regs = uec->uec_regs;
500
501 if (mii_info->link) {
502 /* Now we make sure that we can be in full duplex mode.
503 * If not, we operate in half-duplex mode. */
504 if (mii_info->duplex != uec->oldduplex) {
505 if (!(mii_info->duplex)) {
506 uec_set_mac_duplex(uec, DUPLEX_HALF);
507 printf("%s: Half Duplex\n", dev->name);
508 } else {
509 uec_set_mac_duplex(uec, DUPLEX_FULL);
510 printf("%s: Full Duplex\n", dev->name);
511 }
512 uec->oldduplex = mii_info->duplex;
513 }
514
515 if (mii_info->speed != uec->oldspeed) {
516 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
517 switch (mii_info->speed) {
518 case 1000:
519 break;
520 case 100:
521 printf ("switching to rgmii 100\n");
522 /* change phy to rgmii 100 */
523 change_phy_interface_mode(dev,
524 ENET_100_RGMII);
525 /* change the MAC interface mode */
526 uec_set_mac_if_mode(uec,ENET_100_RGMII);
527 break;
528 case 10:
529 printf ("switching to rgmii 10\n");
530 /* change phy to rgmii 10 */
531 change_phy_interface_mode(dev,
532 ENET_10_RGMII);
533 /* change the MAC interface mode */
534 uec_set_mac_if_mode(uec,ENET_10_RGMII);
535 break;
536 default:
537 printf("%s: Ack,Speed(%d)is illegal\n",
538 dev->name, mii_info->speed);
539 break;
540 }
541 }
542
543 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
544 uec->oldspeed = mii_info->speed;
545 }
546
547 if (!uec->oldlink) {
548 printf("%s: Link is up\n", dev->name);
549 uec->oldlink = 1;
550 }
551
552 } else { /* if (mii_info->link) */
553 if (uec->oldlink) {
554 printf("%s: Link is down\n", dev->name);
555 uec->oldlink = 0;
556 uec->oldspeed = 0;
557 uec->oldduplex = -1;
558 }
559 }
560 }
561
562 static void phy_change(struct eth_device *dev)
563 {
564 uec_private_t *uec = (uec_private_t *)dev->priv;
565 uec_t *uec_regs;
566 int result = 0;
567
568 uec_regs = uec->uec_regs;
569
570 /* Delay 5s to give the PHY a chance to change the register state */
571 udelay(5000000);
572
573 /* Update the link, speed, duplex */
574 result = uec->mii_info->phyinfo->read_status(uec->mii_info);
575
576 /* Adjust the interface according to speed */
577 if ((0 == result) || (uec->mii_info->link == 0)) {
578 adjust_link(dev);
579 }
580 }
581
582 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
583 {
584 uec_t *uec_regs;
585 u32 mac_addr1;
586 u32 mac_addr2;
587
588 if (!uec) {
589 printf("%s: uec not initial\n", __FUNCTION__);
590 return -EINVAL;
591 }
592
593 uec_regs = uec->uec_regs;
594
595 /* if a station address of 0x12345678ABCD, perform a write to
596 MACSTNADDR1 of 0xCDAB7856,
597 MACSTNADDR2 of 0x34120000 */
598
599 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
600 (mac_addr[3] << 8) | (mac_addr[2]);
601 out_be32(&uec_regs->macstnaddr1, mac_addr1);
602
603 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
604 out_be32(&uec_regs->macstnaddr2, mac_addr2);
605
606 return 0;
607 }
608
609 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
610 int *threads_num_ret)
611 {
612 int num_threads_numerica;
613
614 switch (threads_num) {
615 case UEC_NUM_OF_THREADS_1:
616 num_threads_numerica = 1;
617 break;
618 case UEC_NUM_OF_THREADS_2:
619 num_threads_numerica = 2;
620 break;
621 case UEC_NUM_OF_THREADS_4:
622 num_threads_numerica = 4;
623 break;
624 case UEC_NUM_OF_THREADS_6:
625 num_threads_numerica = 6;
626 break;
627 case UEC_NUM_OF_THREADS_8:
628 num_threads_numerica = 8;
629 break;
630 default:
631 printf("%s: Bad number of threads value.",
632 __FUNCTION__);
633 return -EINVAL;
634 }
635
636 *threads_num_ret = num_threads_numerica;
637
638 return 0;
639 }
640
641 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
642 {
643 uec_info_t *uec_info;
644 u32 end_bd;
645 u8 bmrx = 0;
646 int i;
647
648 uec_info = uec->uec_info;
649
650 /* Alloc global Tx parameter RAM page */
651 uec->tx_glbl_pram_offset = qe_muram_alloc(
652 sizeof(uec_tx_global_pram_t),
653 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
654 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
655 qe_muram_addr(uec->tx_glbl_pram_offset);
656
657 /* Zero the global Tx prameter RAM */
658 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
659
660 /* Init global Tx parameter RAM */
661
662 /* TEMODER, RMON statistics disable, one Tx queue */
663 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
664
665 /* SQPTR */
666 uec->send_q_mem_reg_offset = qe_muram_alloc(
667 sizeof(uec_send_queue_qd_t),
668 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
669 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
670 qe_muram_addr(uec->send_q_mem_reg_offset);
671 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
672
673 /* Setup the table with TxBDs ring */
674 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
675 * SIZEOFBD;
676 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
677 (u32)(uec->p_tx_bd_ring));
678 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
679 end_bd);
680
681 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
682 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
683
684 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
685 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
686
687 /* TSTATE, global snooping, big endian, the CSB bus selected */
688 bmrx = BMR_INIT_VALUE;
689 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
690
691 /* IPH_Offset */
692 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
693 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
694 }
695
696 /* VTAG table */
697 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
698 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
699 }
700
701 /* TQPTR */
702 uec->thread_dat_tx_offset = qe_muram_alloc(
703 num_threads_tx * sizeof(uec_thread_data_tx_t) +
704 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
705
706 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
707 qe_muram_addr(uec->thread_dat_tx_offset);
708 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
709 }
710
711 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
712 {
713 u8 bmrx = 0;
714 int i;
715 uec_82xx_address_filtering_pram_t *p_af_pram;
716
717 /* Allocate global Rx parameter RAM page */
718 uec->rx_glbl_pram_offset = qe_muram_alloc(
719 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
720 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
721 qe_muram_addr(uec->rx_glbl_pram_offset);
722
723 /* Zero Global Rx parameter RAM */
724 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
725
726 /* Init global Rx parameter RAM */
727 /* REMODER, Extended feature mode disable, VLAN disable,
728 LossLess flow control disable, Receive firmware statisic disable,
729 Extended address parsing mode disable, One Rx queues,
730 Dynamic maximum/minimum frame length disable, IP checksum check
731 disable, IP address alignment disable
732 */
733 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
734
735 /* RQPTR */
736 uec->thread_dat_rx_offset = qe_muram_alloc(
737 num_threads_rx * sizeof(uec_thread_data_rx_t),
738 UEC_THREAD_DATA_ALIGNMENT);
739 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
740 qe_muram_addr(uec->thread_dat_rx_offset);
741 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
742
743 /* Type_or_Len */
744 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
745
746 /* RxRMON base pointer, we don't need it */
747 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
748
749 /* IntCoalescingPTR, we don't need it, no interrupt */
750 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
751
752 /* RSTATE, global snooping, big endian, the CSB bus selected */
753 bmrx = BMR_INIT_VALUE;
754 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
755
756 /* MRBLR */
757 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
758
759 /* RBDQPTR */
760 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
761 sizeof(uec_rx_bd_queues_entry_t) + \
762 sizeof(uec_rx_prefetched_bds_t),
763 UEC_RX_BD_QUEUES_ALIGNMENT);
764 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
765 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
766
767 /* Zero it */
768 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
769 sizeof(uec_rx_prefetched_bds_t));
770 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
771 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
772 (u32)uec->p_rx_bd_ring);
773
774 /* MFLR */
775 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
776 /* MINFLR */
777 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
778 /* MAXD1 */
779 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
780 /* MAXD2 */
781 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
782 /* ECAM_PTR */
783 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
784 /* L2QT */
785 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
786 /* L3QT */
787 for (i = 0; i < 8; i++) {
788 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
789 }
790
791 /* VLAN_TYPE */
792 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
793 /* TCI */
794 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
795
796 /* Clear PQ2 style address filtering hash table */
797 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
798 uec->p_rx_glbl_pram->addressfiltering;
799
800 p_af_pram->iaddr_h = 0;
801 p_af_pram->iaddr_l = 0;
802 p_af_pram->gaddr_h = 0;
803 p_af_pram->gaddr_l = 0;
804 }
805
806 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
807 int thread_tx, int thread_rx)
808 {
809 uec_init_cmd_pram_t *p_init_enet_param;
810 u32 init_enet_param_offset;
811 uec_info_t *uec_info;
812 int i;
813 int snum;
814 u32 init_enet_offset;
815 u32 entry_val;
816 u32 command;
817 u32 cecr_subblock;
818
819 uec_info = uec->uec_info;
820
821 /* Allocate init enet command parameter */
822 uec->init_enet_param_offset = qe_muram_alloc(
823 sizeof(uec_init_cmd_pram_t), 4);
824 init_enet_param_offset = uec->init_enet_param_offset;
825 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
826 qe_muram_addr(uec->init_enet_param_offset);
827
828 /* Zero init enet command struct */
829 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
830
831 /* Init the command struct */
832 p_init_enet_param = uec->p_init_enet_param;
833 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
834 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
835 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
836 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
837 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
838 p_init_enet_param->largestexternallookupkeysize = 0;
839
840 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
841 << ENET_INIT_PARAM_RGF_SHIFT;
842 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
843 << ENET_INIT_PARAM_TGF_SHIFT;
844
845 /* Init Rx global parameter pointer */
846 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
847 (u32)uec_info->riscRx;
848
849 /* Init Rx threads */
850 for (i = 0; i < (thread_rx + 1); i++) {
851 if ((snum = qe_get_snum()) < 0) {
852 printf("%s can not get snum\n", __FUNCTION__);
853 return -ENOMEM;
854 }
855
856 if (i==0) {
857 init_enet_offset = 0;
858 } else {
859 init_enet_offset = qe_muram_alloc(
860 sizeof(uec_thread_rx_pram_t),
861 UEC_THREAD_RX_PRAM_ALIGNMENT);
862 }
863
864 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
865 init_enet_offset | (u32)uec_info->riscRx;
866 p_init_enet_param->rxthread[i] = entry_val;
867 }
868
869 /* Init Tx global parameter pointer */
870 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
871 (u32)uec_info->riscTx;
872
873 /* Init Tx threads */
874 for (i = 0; i < thread_tx; i++) {
875 if ((snum = qe_get_snum()) < 0) {
876 printf("%s can not get snum\n", __FUNCTION__);
877 return -ENOMEM;
878 }
879
880 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
881 UEC_THREAD_TX_PRAM_ALIGNMENT);
882
883 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
884 init_enet_offset | (u32)uec_info->riscTx;
885 p_init_enet_param->txthread[i] = entry_val;
886 }
887
888 __asm__ __volatile__("sync");
889
890 /* Issue QE command */
891 command = QE_INIT_TX_RX;
892 cecr_subblock = ucc_fast_get_qe_cr_subblock(
893 uec->uec_info->uf_info.ucc_num);
894 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
895 init_enet_param_offset);
896
897 return 0;
898 }
899
900 static int uec_startup(uec_private_t *uec)
901 {
902 uec_info_t *uec_info;
903 ucc_fast_info_t *uf_info;
904 ucc_fast_private_t *uccf;
905 ucc_fast_t *uf_regs;
906 uec_t *uec_regs;
907 int num_threads_tx;
908 int num_threads_rx;
909 u32 utbipar;
910 enet_interface_e enet_interface;
911 u32 length;
912 u32 align;
913 qe_bd_t *bd;
914 u8 *buf;
915 int i;
916
917 if (!uec || !uec->uec_info) {
918 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
919 return -EINVAL;
920 }
921
922 uec_info = uec->uec_info;
923 uf_info = &(uec_info->uf_info);
924
925 /* Check if Rx BD ring len is illegal */
926 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
927 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
928 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
929 __FUNCTION__);
930 return -EINVAL;
931 }
932
933 /* Check if Tx BD ring len is illegal */
934 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
935 printf("%s: Tx BD ring length must not be smaller than 2.\n",
936 __FUNCTION__);
937 return -EINVAL;
938 }
939
940 /* Check if MRBLR is illegal */
941 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
942 printf("%s: max rx buffer length must be mutliple of 128.\n",
943 __FUNCTION__);
944 return -EINVAL;
945 }
946
947 /* Both Rx and Tx are stopped */
948 uec->grace_stopped_rx = 1;
949 uec->grace_stopped_tx = 1;
950
951 /* Init UCC fast */
952 if (ucc_fast_init(uf_info, &uccf)) {
953 printf("%s: failed to init ucc fast\n", __FUNCTION__);
954 return -ENOMEM;
955 }
956
957 /* Save uccf */
958 uec->uccf = uccf;
959
960 /* Convert the Tx threads number */
961 if (uec_convert_threads_num(uec_info->num_threads_tx,
962 &num_threads_tx)) {
963 return -EINVAL;
964 }
965
966 /* Convert the Rx threads number */
967 if (uec_convert_threads_num(uec_info->num_threads_rx,
968 &num_threads_rx)) {
969 return -EINVAL;
970 }
971
972 uf_regs = uccf->uf_regs;
973
974 /* UEC register is following UCC fast registers */
975 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
976
977 /* Save the UEC register pointer to UEC private struct */
978 uec->uec_regs = uec_regs;
979
980 /* Init UPSMR, enable hardware statistics (UCC) */
981 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
982
983 /* Init MACCFG1, flow control disable, disable Tx and Rx */
984 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
985
986 /* Init MACCFG2, length check, MAC PAD and CRC enable */
987 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
988
989 /* Setup MAC interface mode */
990 uec_set_mac_if_mode(uec, uec_info->enet_interface);
991
992 /* Setup MII management base */
993 #ifndef CONFIG_eTSEC_MDIO_BUS
994 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
995 #else
996 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
997 #endif
998
999 /* Setup MII master clock source */
1000 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1001
1002 /* Setup UTBIPAR */
1003 utbipar = in_be32(&uec_regs->utbipar);
1004 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1005 enet_interface = uec->uec_info->enet_interface;
1006 if (enet_interface == ENET_1000_TBI ||
1007 enet_interface == ENET_1000_RTBI) {
1008 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1009 << UTBIPAR_PHY_ADDRESS_SHIFT;
1010 } else {
1011 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1012 << UTBIPAR_PHY_ADDRESS_SHIFT;
1013 }
1014
1015 out_be32(&uec_regs->utbipar, utbipar);
1016
1017 /* Allocate Tx BDs */
1018 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1019 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1020 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1021 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1022 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1023 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1024 }
1025
1026 align = UEC_TX_BD_RING_ALIGNMENT;
1027 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1028 if (uec->tx_bd_ring_offset != 0) {
1029 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1030 & ~(align - 1));
1031 }
1032
1033 /* Zero all of Tx BDs */
1034 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1035
1036 /* Allocate Rx BDs */
1037 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1038 align = UEC_RX_BD_RING_ALIGNMENT;
1039 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1040 if (uec->rx_bd_ring_offset != 0) {
1041 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1042 & ~(align - 1));
1043 }
1044
1045 /* Zero all of Rx BDs */
1046 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1047
1048 /* Allocate Rx buffer */
1049 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1050 align = UEC_RX_DATA_BUF_ALIGNMENT;
1051 uec->rx_buf_offset = (u32)malloc(length + align);
1052 if (uec->rx_buf_offset != 0) {
1053 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1054 & ~(align - 1));
1055 }
1056
1057 /* Zero all of the Rx buffer */
1058 memset((void *)(uec->rx_buf_offset), 0, length + align);
1059
1060 /* Init TxBD ring */
1061 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1062 uec->txBd = bd;
1063
1064 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1065 BD_DATA_CLEAR(bd);
1066 BD_STATUS_SET(bd, 0);
1067 BD_LENGTH_SET(bd, 0);
1068 bd ++;
1069 }
1070 BD_STATUS_SET((--bd), TxBD_WRAP);
1071
1072 /* Init RxBD ring */
1073 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1074 uec->rxBd = bd;
1075 buf = uec->p_rx_buf;
1076 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1077 BD_DATA_SET(bd, buf);
1078 BD_LENGTH_SET(bd, 0);
1079 BD_STATUS_SET(bd, RxBD_EMPTY);
1080 buf += MAX_RXBUF_LEN;
1081 bd ++;
1082 }
1083 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1084
1085 /* Init global Tx parameter RAM */
1086 uec_init_tx_parameter(uec, num_threads_tx);
1087
1088 /* Init global Rx parameter RAM */
1089 uec_init_rx_parameter(uec, num_threads_rx);
1090
1091 /* Init ethernet Tx and Rx parameter command */
1092 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1093 num_threads_rx)) {
1094 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1095 return -ENOMEM;
1096 }
1097
1098 return 0;
1099 }
1100
1101 static int uec_init(struct eth_device* dev, bd_t *bd)
1102 {
1103 uec_private_t *uec;
1104 int err;
1105
1106 uec = (uec_private_t *)dev->priv;
1107
1108 if (uec->the_first_run == 0) {
1109 /* Set up the MAC address */
1110 if (dev->enetaddr[0] & 0x01) {
1111 printf("%s: MacAddress is multcast address\n",
1112 __FUNCTION__);
1113 return 0;
1114 }
1115 uec_set_mac_address(uec, dev->enetaddr);
1116 uec->the_first_run = 1;
1117 }
1118
1119 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1120 if (err) {
1121 printf("%s: cannot enable UEC device\n", dev->name);
1122 return 0;
1123 }
1124
1125 return uec->mii_info->link;
1126 }
1127
1128 static void uec_halt(struct eth_device* dev)
1129 {
1130 uec_private_t *uec = (uec_private_t *)dev->priv;
1131 uec_stop(uec, COMM_DIR_RX_AND_TX);
1132 }
1133
1134 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1135 {
1136 uec_private_t *uec;
1137 ucc_fast_private_t *uccf;
1138 volatile qe_bd_t *bd;
1139 u16 status;
1140 int i;
1141 int result = 0;
1142
1143 uec = (uec_private_t *)dev->priv;
1144 uccf = uec->uccf;
1145 bd = uec->txBd;
1146
1147 /* Find an empty TxBD */
1148 for (i = 0; bd->status & TxBD_READY; i++) {
1149 if (i > 0x100000) {
1150 printf("%s: tx buffer not ready\n", dev->name);
1151 return result;
1152 }
1153 }
1154
1155 /* Init TxBD */
1156 BD_DATA_SET(bd, buf);
1157 BD_LENGTH_SET(bd, len);
1158 status = bd->status;
1159 status &= BD_WRAP;
1160 status |= (TxBD_READY | TxBD_LAST);
1161 BD_STATUS_SET(bd, status);
1162
1163 /* Tell UCC to transmit the buffer */
1164 ucc_fast_transmit_on_demand(uccf);
1165
1166 /* Wait for buffer to be transmitted */
1167 for (i = 0; bd->status & TxBD_READY; i++) {
1168 if (i > 0x100000) {
1169 printf("%s: tx error\n", dev->name);
1170 return result;
1171 }
1172 }
1173
1174 /* Ok, the buffer be transimitted */
1175 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1176 uec->txBd = bd;
1177 result = 1;
1178
1179 return result;
1180 }
1181
1182 static int uec_recv(struct eth_device* dev)
1183 {
1184 uec_private_t *uec = dev->priv;
1185 volatile qe_bd_t *bd;
1186 u16 status;
1187 u16 len;
1188 u8 *data;
1189
1190 bd = uec->rxBd;
1191 status = bd->status;
1192
1193 while (!(status & RxBD_EMPTY)) {
1194 if (!(status & RxBD_ERROR)) {
1195 data = BD_DATA(bd);
1196 len = BD_LENGTH(bd);
1197 NetReceive(data, len);
1198 } else {
1199 printf("%s: Rx error\n", dev->name);
1200 }
1201 status &= BD_CLEAN;
1202 BD_LENGTH_SET(bd, 0);
1203 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1204 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1205 status = bd->status;
1206 }
1207 uec->rxBd = bd;
1208
1209 return 1;
1210 }
1211
1212 int uec_initialize(int index)
1213 {
1214 struct eth_device *dev;
1215 int i;
1216 uec_private_t *uec;
1217 uec_info_t *uec_info;
1218 int err;
1219
1220 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1221 if (!dev)
1222 return 0;
1223 memset(dev, 0, sizeof(struct eth_device));
1224
1225 /* Allocate the UEC private struct */
1226 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1227 if (!uec) {
1228 return -ENOMEM;
1229 }
1230 memset(uec, 0, sizeof(uec_private_t));
1231
1232 /* Init UEC private struct, they come from board.h */
1233 if (index == 0) {
1234 #ifdef CONFIG_UEC_ETH1
1235 uec_info = &eth1_uec_info;
1236 #endif
1237 } else if (index == 1) {
1238 #ifdef CONFIG_UEC_ETH2
1239 uec_info = &eth2_uec_info;
1240 #endif
1241 } else {
1242 printf("%s: index is illegal.\n", __FUNCTION__);
1243 return -EINVAL;
1244 }
1245
1246 uec->uec_info = uec_info;
1247
1248 sprintf(dev->name, "FSL UEC%d", index);
1249 dev->iobase = 0;
1250 dev->priv = (void *)uec;
1251 dev->init = uec_init;
1252 dev->halt = uec_halt;
1253 dev->send = uec_send;
1254 dev->recv = uec_recv;
1255
1256 /* Clear the ethnet address */
1257 for (i = 0; i < 6; i++)
1258 dev->enetaddr[i] = 0;
1259
1260 eth_register(dev);
1261
1262 err = uec_startup(uec);
1263 if (err) {
1264 printf("%s: Cannot configure net device, aborting.",dev->name);
1265 return err;
1266 }
1267
1268 err = init_phy(dev);
1269 if (err) {
1270 printf("%s: Cannot initialize PHY, aborting.\n", dev->name);
1271 return err;
1272 }
1273
1274 phy_change(dev);
1275
1276 return 1;
1277 }
1278 #endif /* CONFIG_QE */
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