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Merge branch 'master' of git://www.denx.de/git/u-boot-fdt
[people/ms/u-boot.git] / drivers / qe / uec.c
1 /*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22 #include "common.h"
23 #include "net.h"
24 #include "malloc.h"
25 #include "asm/errno.h"
26 #include "asm/io.h"
27 #include "asm/immap_qe.h"
28 #include "qe.h"
29 #include "uccf.h"
30 #include "uec.h"
31 #include "uec_phy.h"
32
33 #if defined(CONFIG_QE)
34
35 #ifdef CONFIG_UEC_ETH1
36 static uec_info_t eth1_uec_info = {
37 .uf_info = {
38 .ucc_num = CFG_UEC1_UCC_NUM,
39 .rx_clock = CFG_UEC1_RX_CLK,
40 .tx_clock = CFG_UEC1_TX_CLK,
41 .eth_type = CFG_UEC1_ETH_TYPE,
42 },
43 .num_threads_tx = UEC_NUM_OF_THREADS_4,
44 .num_threads_rx = UEC_NUM_OF_THREADS_4,
45 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
46 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
47 .tx_bd_ring_len = 16,
48 .rx_bd_ring_len = 16,
49 .phy_address = CFG_UEC1_PHY_ADDR,
50 .enet_interface = CFG_UEC1_INTERFACE_MODE,
51 };
52 #endif
53 #ifdef CONFIG_UEC_ETH2
54 static uec_info_t eth2_uec_info = {
55 .uf_info = {
56 .ucc_num = CFG_UEC2_UCC_NUM,
57 .rx_clock = CFG_UEC2_RX_CLK,
58 .tx_clock = CFG_UEC2_TX_CLK,
59 .eth_type = CFG_UEC2_ETH_TYPE,
60 },
61 .num_threads_tx = UEC_NUM_OF_THREADS_4,
62 .num_threads_rx = UEC_NUM_OF_THREADS_4,
63 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
64 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
65 .tx_bd_ring_len = 16,
66 .rx_bd_ring_len = 16,
67 .phy_address = CFG_UEC2_PHY_ADDR,
68 .enet_interface = CFG_UEC2_INTERFACE_MODE,
69 };
70 #endif
71
72 #ifdef CONFIG_UEC_ETH3
73 static uec_info_t eth3_uec_info = {
74 .uf_info = {
75 .ucc_num = CFG_UEC3_UCC_NUM,
76 .rx_clock = CFG_UEC3_RX_CLK,
77 .tx_clock = CFG_UEC3_TX_CLK,
78 .eth_type = CFG_UEC3_ETH_TYPE,
79 },
80 .num_threads_tx = UEC_NUM_OF_THREADS_4,
81 .num_threads_rx = UEC_NUM_OF_THREADS_4,
82 .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
83 .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
84 .tx_bd_ring_len = 16,
85 .rx_bd_ring_len = 16,
86 .phy_address = CFG_UEC3_PHY_ADDR,
87 .enet_interface = CFG_UEC3_INTERFACE_MODE,
88 };
89 #endif
90
91 static int uec_mac_enable(uec_private_t *uec, comm_dir_e mode)
92 {
93 uec_t *uec_regs;
94 u32 maccfg1;
95
96 if (!uec) {
97 printf("%s: uec not initial\n", __FUNCTION__);
98 return -EINVAL;
99 }
100 uec_regs = uec->uec_regs;
101
102 maccfg1 = in_be32(&uec_regs->maccfg1);
103
104 if (mode & COMM_DIR_TX) {
105 maccfg1 |= MACCFG1_ENABLE_TX;
106 out_be32(&uec_regs->maccfg1, maccfg1);
107 uec->mac_tx_enabled = 1;
108 }
109
110 if (mode & COMM_DIR_RX) {
111 maccfg1 |= MACCFG1_ENABLE_RX;
112 out_be32(&uec_regs->maccfg1, maccfg1);
113 uec->mac_rx_enabled = 1;
114 }
115
116 return 0;
117 }
118
119 static int uec_mac_disable(uec_private_t *uec, comm_dir_e mode)
120 {
121 uec_t *uec_regs;
122 u32 maccfg1;
123
124 if (!uec) {
125 printf("%s: uec not initial\n", __FUNCTION__);
126 return -EINVAL;
127 }
128 uec_regs = uec->uec_regs;
129
130 maccfg1 = in_be32(&uec_regs->maccfg1);
131
132 if (mode & COMM_DIR_TX) {
133 maccfg1 &= ~MACCFG1_ENABLE_TX;
134 out_be32(&uec_regs->maccfg1, maccfg1);
135 uec->mac_tx_enabled = 0;
136 }
137
138 if (mode & COMM_DIR_RX) {
139 maccfg1 &= ~MACCFG1_ENABLE_RX;
140 out_be32(&uec_regs->maccfg1, maccfg1);
141 uec->mac_rx_enabled = 0;
142 }
143
144 return 0;
145 }
146
147 static int uec_graceful_stop_tx(uec_private_t *uec)
148 {
149 ucc_fast_t *uf_regs;
150 u32 cecr_subblock;
151 u32 ucce;
152
153 if (!uec || !uec->uccf) {
154 printf("%s: No handle passed.\n", __FUNCTION__);
155 return -EINVAL;
156 }
157
158 uf_regs = uec->uccf->uf_regs;
159
160 /* Clear the grace stop event */
161 out_be32(&uf_regs->ucce, UCCE_GRA);
162
163 /* Issue host command */
164 cecr_subblock =
165 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
166 qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
167 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
168
169 /* Wait for command to complete */
170 do {
171 ucce = in_be32(&uf_regs->ucce);
172 } while (! (ucce & UCCE_GRA));
173
174 uec->grace_stopped_tx = 1;
175
176 return 0;
177 }
178
179 static int uec_graceful_stop_rx(uec_private_t *uec)
180 {
181 u32 cecr_subblock;
182 u8 ack;
183
184 if (!uec) {
185 printf("%s: No handle passed.\n", __FUNCTION__);
186 return -EINVAL;
187 }
188
189 if (!uec->p_rx_glbl_pram) {
190 printf("%s: No init rx global parameter\n", __FUNCTION__);
191 return -EINVAL;
192 }
193
194 /* Clear acknowledge bit */
195 ack = uec->p_rx_glbl_pram->rxgstpack;
196 ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
197 uec->p_rx_glbl_pram->rxgstpack = ack;
198
199 /* Keep issuing cmd and checking ack bit until it is asserted */
200 do {
201 /* Issue host command */
202 cecr_subblock =
203 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
204 qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
205 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
206 ack = uec->p_rx_glbl_pram->rxgstpack;
207 } while (! (ack & GRACEFUL_STOP_ACKNOWLEDGE_RX ));
208
209 uec->grace_stopped_rx = 1;
210
211 return 0;
212 }
213
214 static int uec_restart_tx(uec_private_t *uec)
215 {
216 u32 cecr_subblock;
217
218 if (!uec || !uec->uec_info) {
219 printf("%s: No handle passed.\n", __FUNCTION__);
220 return -EINVAL;
221 }
222
223 cecr_subblock =
224 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
225 qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
226 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
227
228 uec->grace_stopped_tx = 0;
229
230 return 0;
231 }
232
233 static int uec_restart_rx(uec_private_t *uec)
234 {
235 u32 cecr_subblock;
236
237 if (!uec || !uec->uec_info) {
238 printf("%s: No handle passed.\n", __FUNCTION__);
239 return -EINVAL;
240 }
241
242 cecr_subblock =
243 ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
244 qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
245 (u8)QE_CR_PROTOCOL_ETHERNET, 0);
246
247 uec->grace_stopped_rx = 0;
248
249 return 0;
250 }
251
252 static int uec_open(uec_private_t *uec, comm_dir_e mode)
253 {
254 ucc_fast_private_t *uccf;
255
256 if (!uec || !uec->uccf) {
257 printf("%s: No handle passed.\n", __FUNCTION__);
258 return -EINVAL;
259 }
260 uccf = uec->uccf;
261
262 /* check if the UCC number is in range. */
263 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
264 printf("%s: ucc_num out of range.\n", __FUNCTION__);
265 return -EINVAL;
266 }
267
268 /* Enable MAC */
269 uec_mac_enable(uec, mode);
270
271 /* Enable UCC fast */
272 ucc_fast_enable(uccf, mode);
273
274 /* RISC microcode start */
275 if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx) {
276 uec_restart_tx(uec);
277 }
278 if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx) {
279 uec_restart_rx(uec);
280 }
281
282 return 0;
283 }
284
285 static int uec_stop(uec_private_t *uec, comm_dir_e mode)
286 {
287 ucc_fast_private_t *uccf;
288
289 if (!uec || !uec->uccf) {
290 printf("%s: No handle passed.\n", __FUNCTION__);
291 return -EINVAL;
292 }
293 uccf = uec->uccf;
294
295 /* check if the UCC number is in range. */
296 if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
297 printf("%s: ucc_num out of range.\n", __FUNCTION__);
298 return -EINVAL;
299 }
300 /* Stop any transmissions */
301 if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx) {
302 uec_graceful_stop_tx(uec);
303 }
304 /* Stop any receptions */
305 if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx) {
306 uec_graceful_stop_rx(uec);
307 }
308
309 /* Disable the UCC fast */
310 ucc_fast_disable(uec->uccf, mode);
311
312 /* Disable the MAC */
313 uec_mac_disable(uec, mode);
314
315 return 0;
316 }
317
318 static int uec_set_mac_duplex(uec_private_t *uec, int duplex)
319 {
320 uec_t *uec_regs;
321 u32 maccfg2;
322
323 if (!uec) {
324 printf("%s: uec not initial\n", __FUNCTION__);
325 return -EINVAL;
326 }
327 uec_regs = uec->uec_regs;
328
329 if (duplex == DUPLEX_HALF) {
330 maccfg2 = in_be32(&uec_regs->maccfg2);
331 maccfg2 &= ~MACCFG2_FDX;
332 out_be32(&uec_regs->maccfg2, maccfg2);
333 }
334
335 if (duplex == DUPLEX_FULL) {
336 maccfg2 = in_be32(&uec_regs->maccfg2);
337 maccfg2 |= MACCFG2_FDX;
338 out_be32(&uec_regs->maccfg2, maccfg2);
339 }
340
341 return 0;
342 }
343
344 static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
345 {
346 enet_interface_e enet_if_mode;
347 uec_info_t *uec_info;
348 uec_t *uec_regs;
349 u32 upsmr;
350 u32 maccfg2;
351
352 if (!uec) {
353 printf("%s: uec not initial\n", __FUNCTION__);
354 return -EINVAL;
355 }
356
357 uec_info = uec->uec_info;
358 uec_regs = uec->uec_regs;
359 enet_if_mode = if_mode;
360
361 maccfg2 = in_be32(&uec_regs->maccfg2);
362 maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
363
364 upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
365 upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
366
367 switch (enet_if_mode) {
368 case ENET_100_MII:
369 case ENET_10_MII:
370 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
371 break;
372 case ENET_1000_GMII:
373 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
374 break;
375 case ENET_1000_TBI:
376 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
377 upsmr |= UPSMR_TBIM;
378 break;
379 case ENET_1000_RTBI:
380 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
381 upsmr |= (UPSMR_RPM | UPSMR_TBIM);
382 break;
383 case ENET_1000_RGMII:
384 maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
385 upsmr |= UPSMR_RPM;
386 break;
387 case ENET_100_RGMII:
388 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
389 upsmr |= UPSMR_RPM;
390 break;
391 case ENET_10_RGMII:
392 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
393 upsmr |= (UPSMR_RPM | UPSMR_R10M);
394 break;
395 case ENET_100_RMII:
396 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
397 upsmr |= UPSMR_RMM;
398 break;
399 case ENET_10_RMII:
400 maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
401 upsmr |= (UPSMR_R10M | UPSMR_RMM);
402 break;
403 default:
404 return -EINVAL;
405 break;
406 }
407 out_be32(&uec_regs->maccfg2, maccfg2);
408 out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
409
410 return 0;
411 }
412
413 static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
414 {
415 uint timeout = 0x1000;
416 u32 miimcfg = 0;
417
418 miimcfg = in_be32(&uec_mii_regs->miimcfg);
419 miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
420 out_be32(&uec_mii_regs->miimcfg, miimcfg);
421
422 /* Wait until the bus is free */
423 while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
424 if (timeout <= 0) {
425 printf("%s: The MII Bus is stuck!", __FUNCTION__);
426 return -ETIMEDOUT;
427 }
428
429 return 0;
430 }
431
432 static int init_phy(struct eth_device *dev)
433 {
434 uec_private_t *uec;
435 uec_mii_t *umii_regs;
436 struct uec_mii_info *mii_info;
437 struct phy_info *curphy;
438 int err;
439
440 uec = (uec_private_t *)dev->priv;
441 umii_regs = uec->uec_mii_regs;
442
443 uec->oldlink = 0;
444 uec->oldspeed = 0;
445 uec->oldduplex = -1;
446
447 mii_info = malloc(sizeof(*mii_info));
448 if (!mii_info) {
449 printf("%s: Could not allocate mii_info", dev->name);
450 return -ENOMEM;
451 }
452 memset(mii_info, 0, sizeof(*mii_info));
453
454 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
455 mii_info->speed = SPEED_1000;
456 } else {
457 mii_info->speed = SPEED_100;
458 }
459
460 mii_info->duplex = DUPLEX_FULL;
461 mii_info->pause = 0;
462 mii_info->link = 1;
463
464 mii_info->advertising = (ADVERTISED_10baseT_Half |
465 ADVERTISED_10baseT_Full |
466 ADVERTISED_100baseT_Half |
467 ADVERTISED_100baseT_Full |
468 ADVERTISED_1000baseT_Full);
469 mii_info->autoneg = 1;
470 mii_info->mii_id = uec->uec_info->phy_address;
471 mii_info->dev = dev;
472
473 mii_info->mdio_read = &uec_read_phy_reg;
474 mii_info->mdio_write = &uec_write_phy_reg;
475
476 uec->mii_info = mii_info;
477
478 if (init_mii_management_configuration(umii_regs)) {
479 printf("%s: The MII Bus is stuck!", dev->name);
480 err = -1;
481 goto bus_fail;
482 }
483
484 /* get info for this PHY */
485 curphy = uec_get_phy_info(uec->mii_info);
486 if (!curphy) {
487 printf("%s: No PHY found", dev->name);
488 err = -1;
489 goto no_phy;
490 }
491
492 mii_info->phyinfo = curphy;
493
494 /* Run the commands which initialize the PHY */
495 if (curphy->init) {
496 err = curphy->init(uec->mii_info);
497 if (err)
498 goto phy_init_fail;
499 }
500
501 return 0;
502
503 phy_init_fail:
504 no_phy:
505 bus_fail:
506 free(mii_info);
507 return err;
508 }
509
510 static void adjust_link(struct eth_device *dev)
511 {
512 uec_private_t *uec = (uec_private_t *)dev->priv;
513 uec_t *uec_regs;
514 struct uec_mii_info *mii_info = uec->mii_info;
515
516 extern void change_phy_interface_mode(struct eth_device *dev,
517 enet_interface_e mode);
518 uec_regs = uec->uec_regs;
519
520 if (mii_info->link) {
521 /* Now we make sure that we can be in full duplex mode.
522 * If not, we operate in half-duplex mode. */
523 if (mii_info->duplex != uec->oldduplex) {
524 if (!(mii_info->duplex)) {
525 uec_set_mac_duplex(uec, DUPLEX_HALF);
526 printf("%s: Half Duplex\n", dev->name);
527 } else {
528 uec_set_mac_duplex(uec, DUPLEX_FULL);
529 printf("%s: Full Duplex\n", dev->name);
530 }
531 uec->oldduplex = mii_info->duplex;
532 }
533
534 if (mii_info->speed != uec->oldspeed) {
535 if (uec->uec_info->uf_info.eth_type == GIGA_ETH) {
536 switch (mii_info->speed) {
537 case 1000:
538 break;
539 case 100:
540 printf ("switching to rgmii 100\n");
541 /* change phy to rgmii 100 */
542 change_phy_interface_mode(dev,
543 ENET_100_RGMII);
544 /* change the MAC interface mode */
545 uec_set_mac_if_mode(uec,ENET_100_RGMII);
546 break;
547 case 10:
548 printf ("switching to rgmii 10\n");
549 /* change phy to rgmii 10 */
550 change_phy_interface_mode(dev,
551 ENET_10_RGMII);
552 /* change the MAC interface mode */
553 uec_set_mac_if_mode(uec,ENET_10_RGMII);
554 break;
555 default:
556 printf("%s: Ack,Speed(%d)is illegal\n",
557 dev->name, mii_info->speed);
558 break;
559 }
560 }
561
562 printf("%s: Speed %dBT\n", dev->name, mii_info->speed);
563 uec->oldspeed = mii_info->speed;
564 }
565
566 if (!uec->oldlink) {
567 printf("%s: Link is up\n", dev->name);
568 uec->oldlink = 1;
569 }
570
571 } else { /* if (mii_info->link) */
572 if (uec->oldlink) {
573 printf("%s: Link is down\n", dev->name);
574 uec->oldlink = 0;
575 uec->oldspeed = 0;
576 uec->oldduplex = -1;
577 }
578 }
579 }
580
581 static void phy_change(struct eth_device *dev)
582 {
583 uec_private_t *uec = (uec_private_t *)dev->priv;
584 uec_t *uec_regs;
585 int result = 0;
586
587 uec_regs = uec->uec_regs;
588
589 /* Delay 5s to give the PHY a chance to change the register state */
590 udelay(5000000);
591
592 /* Update the link, speed, duplex */
593 result = uec->mii_info->phyinfo->read_status(uec->mii_info);
594
595 /* Adjust the interface according to speed */
596 if ((0 == result) || (uec->mii_info->link == 0)) {
597 adjust_link(dev);
598 }
599 }
600
601 static int uec_set_mac_address(uec_private_t *uec, u8 *mac_addr)
602 {
603 uec_t *uec_regs;
604 u32 mac_addr1;
605 u32 mac_addr2;
606
607 if (!uec) {
608 printf("%s: uec not initial\n", __FUNCTION__);
609 return -EINVAL;
610 }
611
612 uec_regs = uec->uec_regs;
613
614 /* if a station address of 0x12345678ABCD, perform a write to
615 MACSTNADDR1 of 0xCDAB7856,
616 MACSTNADDR2 of 0x34120000 */
617
618 mac_addr1 = (mac_addr[5] << 24) | (mac_addr[4] << 16) | \
619 (mac_addr[3] << 8) | (mac_addr[2]);
620 out_be32(&uec_regs->macstnaddr1, mac_addr1);
621
622 mac_addr2 = ((mac_addr[1] << 24) | (mac_addr[0] << 16)) & 0xffff0000;
623 out_be32(&uec_regs->macstnaddr2, mac_addr2);
624
625 return 0;
626 }
627
628 static int uec_convert_threads_num(uec_num_of_threads_e threads_num,
629 int *threads_num_ret)
630 {
631 int num_threads_numerica;
632
633 switch (threads_num) {
634 case UEC_NUM_OF_THREADS_1:
635 num_threads_numerica = 1;
636 break;
637 case UEC_NUM_OF_THREADS_2:
638 num_threads_numerica = 2;
639 break;
640 case UEC_NUM_OF_THREADS_4:
641 num_threads_numerica = 4;
642 break;
643 case UEC_NUM_OF_THREADS_6:
644 num_threads_numerica = 6;
645 break;
646 case UEC_NUM_OF_THREADS_8:
647 num_threads_numerica = 8;
648 break;
649 default:
650 printf("%s: Bad number of threads value.",
651 __FUNCTION__);
652 return -EINVAL;
653 }
654
655 *threads_num_ret = num_threads_numerica;
656
657 return 0;
658 }
659
660 static void uec_init_tx_parameter(uec_private_t *uec, int num_threads_tx)
661 {
662 uec_info_t *uec_info;
663 u32 end_bd;
664 u8 bmrx = 0;
665 int i;
666
667 uec_info = uec->uec_info;
668
669 /* Alloc global Tx parameter RAM page */
670 uec->tx_glbl_pram_offset = qe_muram_alloc(
671 sizeof(uec_tx_global_pram_t),
672 UEC_TX_GLOBAL_PRAM_ALIGNMENT);
673 uec->p_tx_glbl_pram = (uec_tx_global_pram_t *)
674 qe_muram_addr(uec->tx_glbl_pram_offset);
675
676 /* Zero the global Tx prameter RAM */
677 memset(uec->p_tx_glbl_pram, 0, sizeof(uec_tx_global_pram_t));
678
679 /* Init global Tx parameter RAM */
680
681 /* TEMODER, RMON statistics disable, one Tx queue */
682 out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
683
684 /* SQPTR */
685 uec->send_q_mem_reg_offset = qe_muram_alloc(
686 sizeof(uec_send_queue_qd_t),
687 UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
688 uec->p_send_q_mem_reg = (uec_send_queue_mem_region_t *)
689 qe_muram_addr(uec->send_q_mem_reg_offset);
690 out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
691
692 /* Setup the table with TxBDs ring */
693 end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
694 * SIZEOFBD;
695 out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
696 (u32)(uec->p_tx_bd_ring));
697 out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
698 end_bd);
699
700 /* Scheduler Base Pointer, we have only one Tx queue, no need it */
701 out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
702
703 /* TxRMON Base Pointer, TxRMON disable, we don't need it */
704 out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
705
706 /* TSTATE, global snooping, big endian, the CSB bus selected */
707 bmrx = BMR_INIT_VALUE;
708 out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
709
710 /* IPH_Offset */
711 for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++) {
712 out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
713 }
714
715 /* VTAG table */
716 for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++) {
717 out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
718 }
719
720 /* TQPTR */
721 uec->thread_dat_tx_offset = qe_muram_alloc(
722 num_threads_tx * sizeof(uec_thread_data_tx_t) +
723 32 *(num_threads_tx == 1), UEC_THREAD_DATA_ALIGNMENT);
724
725 uec->p_thread_data_tx = (uec_thread_data_tx_t *)
726 qe_muram_addr(uec->thread_dat_tx_offset);
727 out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
728 }
729
730 static void uec_init_rx_parameter(uec_private_t *uec, int num_threads_rx)
731 {
732 u8 bmrx = 0;
733 int i;
734 uec_82xx_address_filtering_pram_t *p_af_pram;
735
736 /* Allocate global Rx parameter RAM page */
737 uec->rx_glbl_pram_offset = qe_muram_alloc(
738 sizeof(uec_rx_global_pram_t), UEC_RX_GLOBAL_PRAM_ALIGNMENT);
739 uec->p_rx_glbl_pram = (uec_rx_global_pram_t *)
740 qe_muram_addr(uec->rx_glbl_pram_offset);
741
742 /* Zero Global Rx parameter RAM */
743 memset(uec->p_rx_glbl_pram, 0, sizeof(uec_rx_global_pram_t));
744
745 /* Init global Rx parameter RAM */
746 /* REMODER, Extended feature mode disable, VLAN disable,
747 LossLess flow control disable, Receive firmware statisic disable,
748 Extended address parsing mode disable, One Rx queues,
749 Dynamic maximum/minimum frame length disable, IP checksum check
750 disable, IP address alignment disable
751 */
752 out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
753
754 /* RQPTR */
755 uec->thread_dat_rx_offset = qe_muram_alloc(
756 num_threads_rx * sizeof(uec_thread_data_rx_t),
757 UEC_THREAD_DATA_ALIGNMENT);
758 uec->p_thread_data_rx = (uec_thread_data_rx_t *)
759 qe_muram_addr(uec->thread_dat_rx_offset);
760 out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
761
762 /* Type_or_Len */
763 out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
764
765 /* RxRMON base pointer, we don't need it */
766 out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
767
768 /* IntCoalescingPTR, we don't need it, no interrupt */
769 out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
770
771 /* RSTATE, global snooping, big endian, the CSB bus selected */
772 bmrx = BMR_INIT_VALUE;
773 out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
774
775 /* MRBLR */
776 out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
777
778 /* RBDQPTR */
779 uec->rx_bd_qs_tbl_offset = qe_muram_alloc(
780 sizeof(uec_rx_bd_queues_entry_t) + \
781 sizeof(uec_rx_prefetched_bds_t),
782 UEC_RX_BD_QUEUES_ALIGNMENT);
783 uec->p_rx_bd_qs_tbl = (uec_rx_bd_queues_entry_t *)
784 qe_muram_addr(uec->rx_bd_qs_tbl_offset);
785
786 /* Zero it */
787 memset(uec->p_rx_bd_qs_tbl, 0, sizeof(uec_rx_bd_queues_entry_t) + \
788 sizeof(uec_rx_prefetched_bds_t));
789 out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
790 out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
791 (u32)uec->p_rx_bd_ring);
792
793 /* MFLR */
794 out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
795 /* MINFLR */
796 out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
797 /* MAXD1 */
798 out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
799 /* MAXD2 */
800 out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
801 /* ECAM_PTR */
802 out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
803 /* L2QT */
804 out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
805 /* L3QT */
806 for (i = 0; i < 8; i++) {
807 out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
808 }
809
810 /* VLAN_TYPE */
811 out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
812 /* TCI */
813 out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
814
815 /* Clear PQ2 style address filtering hash table */
816 p_af_pram = (uec_82xx_address_filtering_pram_t *) \
817 uec->p_rx_glbl_pram->addressfiltering;
818
819 p_af_pram->iaddr_h = 0;
820 p_af_pram->iaddr_l = 0;
821 p_af_pram->gaddr_h = 0;
822 p_af_pram->gaddr_l = 0;
823 }
824
825 static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
826 int thread_tx, int thread_rx)
827 {
828 uec_init_cmd_pram_t *p_init_enet_param;
829 u32 init_enet_param_offset;
830 uec_info_t *uec_info;
831 int i;
832 int snum;
833 u32 init_enet_offset;
834 u32 entry_val;
835 u32 command;
836 u32 cecr_subblock;
837
838 uec_info = uec->uec_info;
839
840 /* Allocate init enet command parameter */
841 uec->init_enet_param_offset = qe_muram_alloc(
842 sizeof(uec_init_cmd_pram_t), 4);
843 init_enet_param_offset = uec->init_enet_param_offset;
844 uec->p_init_enet_param = (uec_init_cmd_pram_t *)
845 qe_muram_addr(uec->init_enet_param_offset);
846
847 /* Zero init enet command struct */
848 memset((void *)uec->p_init_enet_param, 0, sizeof(uec_init_cmd_pram_t));
849
850 /* Init the command struct */
851 p_init_enet_param = uec->p_init_enet_param;
852 p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
853 p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
854 p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
855 p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
856 p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
857 p_init_enet_param->largestexternallookupkeysize = 0;
858
859 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
860 << ENET_INIT_PARAM_RGF_SHIFT;
861 p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
862 << ENET_INIT_PARAM_TGF_SHIFT;
863
864 /* Init Rx global parameter pointer */
865 p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
866 (u32)uec_info->riscRx;
867
868 /* Init Rx threads */
869 for (i = 0; i < (thread_rx + 1); i++) {
870 if ((snum = qe_get_snum()) < 0) {
871 printf("%s can not get snum\n", __FUNCTION__);
872 return -ENOMEM;
873 }
874
875 if (i==0) {
876 init_enet_offset = 0;
877 } else {
878 init_enet_offset = qe_muram_alloc(
879 sizeof(uec_thread_rx_pram_t),
880 UEC_THREAD_RX_PRAM_ALIGNMENT);
881 }
882
883 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
884 init_enet_offset | (u32)uec_info->riscRx;
885 p_init_enet_param->rxthread[i] = entry_val;
886 }
887
888 /* Init Tx global parameter pointer */
889 p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
890 (u32)uec_info->riscTx;
891
892 /* Init Tx threads */
893 for (i = 0; i < thread_tx; i++) {
894 if ((snum = qe_get_snum()) < 0) {
895 printf("%s can not get snum\n", __FUNCTION__);
896 return -ENOMEM;
897 }
898
899 init_enet_offset = qe_muram_alloc(sizeof(uec_thread_tx_pram_t),
900 UEC_THREAD_TX_PRAM_ALIGNMENT);
901
902 entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
903 init_enet_offset | (u32)uec_info->riscTx;
904 p_init_enet_param->txthread[i] = entry_val;
905 }
906
907 __asm__ __volatile__("sync");
908
909 /* Issue QE command */
910 command = QE_INIT_TX_RX;
911 cecr_subblock = ucc_fast_get_qe_cr_subblock(
912 uec->uec_info->uf_info.ucc_num);
913 qe_issue_cmd(command, cecr_subblock, (u8) QE_CR_PROTOCOL_ETHERNET,
914 init_enet_param_offset);
915
916 return 0;
917 }
918
919 static int uec_startup(uec_private_t *uec)
920 {
921 uec_info_t *uec_info;
922 ucc_fast_info_t *uf_info;
923 ucc_fast_private_t *uccf;
924 ucc_fast_t *uf_regs;
925 uec_t *uec_regs;
926 int num_threads_tx;
927 int num_threads_rx;
928 u32 utbipar;
929 enet_interface_e enet_interface;
930 u32 length;
931 u32 align;
932 qe_bd_t *bd;
933 u8 *buf;
934 int i;
935
936 if (!uec || !uec->uec_info) {
937 printf("%s: uec or uec_info not initial\n", __FUNCTION__);
938 return -EINVAL;
939 }
940
941 uec_info = uec->uec_info;
942 uf_info = &(uec_info->uf_info);
943
944 /* Check if Rx BD ring len is illegal */
945 if ((uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN) || \
946 (uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT)) {
947 printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
948 __FUNCTION__);
949 return -EINVAL;
950 }
951
952 /* Check if Tx BD ring len is illegal */
953 if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
954 printf("%s: Tx BD ring length must not be smaller than 2.\n",
955 __FUNCTION__);
956 return -EINVAL;
957 }
958
959 /* Check if MRBLR is illegal */
960 if ((MAX_RXBUF_LEN == 0) || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
961 printf("%s: max rx buffer length must be mutliple of 128.\n",
962 __FUNCTION__);
963 return -EINVAL;
964 }
965
966 /* Both Rx and Tx are stopped */
967 uec->grace_stopped_rx = 1;
968 uec->grace_stopped_tx = 1;
969
970 /* Init UCC fast */
971 if (ucc_fast_init(uf_info, &uccf)) {
972 printf("%s: failed to init ucc fast\n", __FUNCTION__);
973 return -ENOMEM;
974 }
975
976 /* Save uccf */
977 uec->uccf = uccf;
978
979 /* Convert the Tx threads number */
980 if (uec_convert_threads_num(uec_info->num_threads_tx,
981 &num_threads_tx)) {
982 return -EINVAL;
983 }
984
985 /* Convert the Rx threads number */
986 if (uec_convert_threads_num(uec_info->num_threads_rx,
987 &num_threads_rx)) {
988 return -EINVAL;
989 }
990
991 uf_regs = uccf->uf_regs;
992
993 /* UEC register is following UCC fast registers */
994 uec_regs = (uec_t *)(&uf_regs->ucc_eth);
995
996 /* Save the UEC register pointer to UEC private struct */
997 uec->uec_regs = uec_regs;
998
999 /* Init UPSMR, enable hardware statistics (UCC) */
1000 out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
1001
1002 /* Init MACCFG1, flow control disable, disable Tx and Rx */
1003 out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
1004
1005 /* Init MACCFG2, length check, MAC PAD and CRC enable */
1006 out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
1007
1008 /* Setup MAC interface mode */
1009 uec_set_mac_if_mode(uec, uec_info->enet_interface);
1010
1011 /* Setup MII management base */
1012 #ifndef CONFIG_eTSEC_MDIO_BUS
1013 uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
1014 #else
1015 uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
1016 #endif
1017
1018 /* Setup MII master clock source */
1019 qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
1020
1021 /* Setup UTBIPAR */
1022 utbipar = in_be32(&uec_regs->utbipar);
1023 utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
1024 enet_interface = uec->uec_info->enet_interface;
1025 if (enet_interface == ENET_1000_TBI ||
1026 enet_interface == ENET_1000_RTBI) {
1027 utbipar |= (uec_info->phy_address + uec_info->uf_info.ucc_num)
1028 << UTBIPAR_PHY_ADDRESS_SHIFT;
1029 } else {
1030 utbipar |= (0x10 + uec_info->uf_info.ucc_num)
1031 << UTBIPAR_PHY_ADDRESS_SHIFT;
1032 }
1033
1034 out_be32(&uec_regs->utbipar, utbipar);
1035
1036 /* Allocate Tx BDs */
1037 length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
1038 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
1039 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1040 if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
1041 UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) {
1042 length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
1043 }
1044
1045 align = UEC_TX_BD_RING_ALIGNMENT;
1046 uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
1047 if (uec->tx_bd_ring_offset != 0) {
1048 uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
1049 & ~(align - 1));
1050 }
1051
1052 /* Zero all of Tx BDs */
1053 memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
1054
1055 /* Allocate Rx BDs */
1056 length = uec_info->rx_bd_ring_len * SIZEOFBD;
1057 align = UEC_RX_BD_RING_ALIGNMENT;
1058 uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
1059 if (uec->rx_bd_ring_offset != 0) {
1060 uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
1061 & ~(align - 1));
1062 }
1063
1064 /* Zero all of Rx BDs */
1065 memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
1066
1067 /* Allocate Rx buffer */
1068 length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
1069 align = UEC_RX_DATA_BUF_ALIGNMENT;
1070 uec->rx_buf_offset = (u32)malloc(length + align);
1071 if (uec->rx_buf_offset != 0) {
1072 uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
1073 & ~(align - 1));
1074 }
1075
1076 /* Zero all of the Rx buffer */
1077 memset((void *)(uec->rx_buf_offset), 0, length + align);
1078
1079 /* Init TxBD ring */
1080 bd = (qe_bd_t *)uec->p_tx_bd_ring;
1081 uec->txBd = bd;
1082
1083 for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
1084 BD_DATA_CLEAR(bd);
1085 BD_STATUS_SET(bd, 0);
1086 BD_LENGTH_SET(bd, 0);
1087 bd ++;
1088 }
1089 BD_STATUS_SET((--bd), TxBD_WRAP);
1090
1091 /* Init RxBD ring */
1092 bd = (qe_bd_t *)uec->p_rx_bd_ring;
1093 uec->rxBd = bd;
1094 buf = uec->p_rx_buf;
1095 for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
1096 BD_DATA_SET(bd, buf);
1097 BD_LENGTH_SET(bd, 0);
1098 BD_STATUS_SET(bd, RxBD_EMPTY);
1099 buf += MAX_RXBUF_LEN;
1100 bd ++;
1101 }
1102 BD_STATUS_SET((--bd), RxBD_WRAP | RxBD_EMPTY);
1103
1104 /* Init global Tx parameter RAM */
1105 uec_init_tx_parameter(uec, num_threads_tx);
1106
1107 /* Init global Rx parameter RAM */
1108 uec_init_rx_parameter(uec, num_threads_rx);
1109
1110 /* Init ethernet Tx and Rx parameter command */
1111 if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
1112 num_threads_rx)) {
1113 printf("%s issue init enet cmd failed\n", __FUNCTION__);
1114 return -ENOMEM;
1115 }
1116
1117 return 0;
1118 }
1119
1120 static int uec_init(struct eth_device* dev, bd_t *bd)
1121 {
1122 uec_private_t *uec;
1123 int err;
1124
1125 uec = (uec_private_t *)dev->priv;
1126
1127 if (uec->the_first_run == 0) {
1128 /* Set up the MAC address */
1129 if (dev->enetaddr[0] & 0x01) {
1130 printf("%s: MacAddress is multcast address\n",
1131 __FUNCTION__);
1132 return 0;
1133 }
1134 uec_set_mac_address(uec, dev->enetaddr);
1135 uec->the_first_run = 1;
1136 }
1137
1138 err = uec_open(uec, COMM_DIR_RX_AND_TX);
1139 if (err) {
1140 printf("%s: cannot enable UEC device\n", dev->name);
1141 return 0;
1142 }
1143
1144 return uec->mii_info->link;
1145 }
1146
1147 static void uec_halt(struct eth_device* dev)
1148 {
1149 uec_private_t *uec = (uec_private_t *)dev->priv;
1150 uec_stop(uec, COMM_DIR_RX_AND_TX);
1151 }
1152
1153 static int uec_send(struct eth_device* dev, volatile void *buf, int len)
1154 {
1155 uec_private_t *uec;
1156 ucc_fast_private_t *uccf;
1157 volatile qe_bd_t *bd;
1158 u16 status;
1159 int i;
1160 int result = 0;
1161
1162 uec = (uec_private_t *)dev->priv;
1163 uccf = uec->uccf;
1164 bd = uec->txBd;
1165
1166 /* Find an empty TxBD */
1167 for (i = 0; bd->status & TxBD_READY; i++) {
1168 if (i > 0x100000) {
1169 printf("%s: tx buffer not ready\n", dev->name);
1170 return result;
1171 }
1172 }
1173
1174 /* Init TxBD */
1175 BD_DATA_SET(bd, buf);
1176 BD_LENGTH_SET(bd, len);
1177 status = bd->status;
1178 status &= BD_WRAP;
1179 status |= (TxBD_READY | TxBD_LAST);
1180 BD_STATUS_SET(bd, status);
1181
1182 /* Tell UCC to transmit the buffer */
1183 ucc_fast_transmit_on_demand(uccf);
1184
1185 /* Wait for buffer to be transmitted */
1186 for (i = 0; bd->status & TxBD_READY; i++) {
1187 if (i > 0x100000) {
1188 printf("%s: tx error\n", dev->name);
1189 return result;
1190 }
1191 }
1192
1193 /* Ok, the buffer be transimitted */
1194 BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
1195 uec->txBd = bd;
1196 result = 1;
1197
1198 return result;
1199 }
1200
1201 static int uec_recv(struct eth_device* dev)
1202 {
1203 uec_private_t *uec = dev->priv;
1204 volatile qe_bd_t *bd;
1205 u16 status;
1206 u16 len;
1207 u8 *data;
1208
1209 bd = uec->rxBd;
1210 status = bd->status;
1211
1212 while (!(status & RxBD_EMPTY)) {
1213 if (!(status & RxBD_ERROR)) {
1214 data = BD_DATA(bd);
1215 len = BD_LENGTH(bd);
1216 NetReceive(data, len);
1217 } else {
1218 printf("%s: Rx error\n", dev->name);
1219 }
1220 status &= BD_CLEAN;
1221 BD_LENGTH_SET(bd, 0);
1222 BD_STATUS_SET(bd, status | RxBD_EMPTY);
1223 BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
1224 status = bd->status;
1225 }
1226 uec->rxBd = bd;
1227
1228 return 1;
1229 }
1230
1231 int uec_initialize(int index)
1232 {
1233 struct eth_device *dev;
1234 int i;
1235 uec_private_t *uec;
1236 uec_info_t *uec_info;
1237 int err;
1238
1239 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
1240 if (!dev)
1241 return 0;
1242 memset(dev, 0, sizeof(struct eth_device));
1243
1244 /* Allocate the UEC private struct */
1245 uec = (uec_private_t *)malloc(sizeof(uec_private_t));
1246 if (!uec) {
1247 return -ENOMEM;
1248 }
1249 memset(uec, 0, sizeof(uec_private_t));
1250
1251 /* Init UEC private struct, they come from board.h */
1252 if (index == 0) {
1253 #ifdef CONFIG_UEC_ETH1
1254 uec_info = &eth1_uec_info;
1255 #endif
1256 } else if (index == 1) {
1257 #ifdef CONFIG_UEC_ETH2
1258 uec_info = &eth2_uec_info;
1259 #endif
1260 } else if (index == 2) {
1261 #ifdef CONFIG_UEC_ETH3
1262 uec_info = &eth3_uec_info;
1263 #endif
1264 } else {
1265 printf("%s: index is illegal.\n", __FUNCTION__);
1266 return -EINVAL;
1267 }
1268
1269 uec->uec_info = uec_info;
1270
1271 sprintf(dev->name, "FSL UEC%d", index);
1272 dev->iobase = 0;
1273 dev->priv = (void *)uec;
1274 dev->init = uec_init;
1275 dev->halt = uec_halt;
1276 dev->send = uec_send;
1277 dev->recv = uec_recv;
1278
1279 /* Clear the ethnet address */
1280 for (i = 0; i < 6; i++)
1281 dev->enetaddr[i] = 0;
1282
1283 eth_register(dev);
1284
1285 err = uec_startup(uec);
1286 if (err) {
1287 printf("%s: Cannot configure net device, aborting.",dev->name);
1288 return err;
1289 }
1290
1291 err = init_phy(dev);
1292 if (err) {
1293 printf("%s: Cannot initialize PHY, aborting.\n", dev->name);
1294 return err;
1295 }
1296
1297 phy_change(dev);
1298
1299 return 1;
1300 }
1301 #endif /* CONFIG_QE */
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