2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 * based on source code of Shlomi Gridish
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #define MAX_TX_THREADS 8
30 #define MAX_RX_THREADS 8
31 #define MAX_TX_QUEUES 8
32 #define MAX_RX_QUEUES 8
33 #define MAX_PREFETCHED_BDS 4
34 #define MAX_IPH_OFFSET_ENTRY 8
35 #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
36 #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
38 /* UEC UPSMR (Protocol Specific Mode Register)
40 #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
41 #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
42 #define UPSMR_PRO 0x00400000 /* Promiscuous */
43 #define UPSMR_CAP 0x00200000 /* CAM polarity */
44 #define UPSMR_RSH 0x00100000 /* Receive Short Frames */
45 #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
46 #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
47 #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
48 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
49 #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
50 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */
51 #define UPSMR_BRO 0x00000200 /* Broadcast Address */
52 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
53 #define UPSMR_SGMM 0x00000020 /* SGMII mode */
55 #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
57 /* UEC MACCFG1 (MAC Configuration 1 Register)
59 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
60 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
61 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
62 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
63 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
64 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
66 #define MACCFG1_INIT_VALUE (0)
68 /* UEC MACCFG2 (MAC Configuration 2 Register)
70 #define MACCFG2_PREL 0x00007000
71 #define MACCFG2_PREL_SHIFT (31 - 19)
72 #define MACCFG2_PREL_MASK 0x0000f000
73 #define MACCFG2_SRP 0x00000080
74 #define MACCFG2_STP 0x00000040
75 #define MACCFG2_RESERVED_1 0x00000020 /* must be set */
76 #define MACCFG2_LC 0x00000010 /* Length Check */
77 #define MACCFG2_MPE 0x00000008
78 #define MACCFG2_FDX 0x00000001 /* Full Duplex */
79 #define MACCFG2_FDX_MASK 0x00000001
80 #define MACCFG2_PAD_CRC 0x00000004
81 #define MACCFG2_CRC_EN 0x00000002
82 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
83 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
84 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
85 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
86 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
87 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300
89 #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
90 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
94 #define UCCE_MPD 0x80000000
95 #define UCCE_SCAR 0x40000000
96 #define UCCE_GRA 0x20000000
97 #define UCCE_CBPR 0x10000000
98 #define UCCE_BSY 0x08000000
99 #define UCCE_RXC 0x04000000
100 #define UCCE_TXC 0x02000000
101 #define UCCE_TXE 0x01000000
102 #define UCCE_TXB7 0x00800000
103 #define UCCE_TXB6 0x00400000
104 #define UCCE_TXB5 0x00200000
105 #define UCCE_TXB4 0x00100000
106 #define UCCE_TXB3 0x00080000
107 #define UCCE_TXB2 0x00040000
108 #define UCCE_TXB1 0x00020000
109 #define UCCE_TXB0 0x00010000
110 #define UCCE_RXB7 0x00008000
111 #define UCCE_RXB6 0x00004000
112 #define UCCE_RXB5 0x00002000
113 #define UCCE_RXB4 0x00001000
114 #define UCCE_RXB3 0x00000800
115 #define UCCE_RXB2 0x00000400
116 #define UCCE_RXB1 0x00000200
117 #define UCCE_RXB0 0x00000100
118 #define UCCE_RXF7 0x00000080
119 #define UCCE_RXF6 0x00000040
120 #define UCCE_RXF5 0x00000020
121 #define UCCE_RXF4 0x00000010
122 #define UCCE_RXF3 0x00000008
123 #define UCCE_RXF2 0x00000004
124 #define UCCE_RXF1 0x00000002
125 #define UCCE_RXF0 0x00000001
127 #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
128 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
129 #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
130 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
131 #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
132 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
133 #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
134 UCCE_RXC | UCCE_TXC | UCCE_TXE)
136 /* UEC TEMODR Register
138 #define TEMODER_SCHEDULER_ENABLE 0x2000
139 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400
140 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
141 #define TEMODER_RMON_STATISTICS 0x0100
142 #define TEMODER_NUM_OF_QUEUES_SHIFT (15-15)
144 #define TEMODER_INIT_VALUE 0xc000
146 /* UEC REMODR Register
148 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
149 #define REMODER_RX_EXTENDED_FEATURES 0x80000000
150 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31-9 )
151 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10)
152 #define REMODER_RX_QOS_MODE_SHIFT (31-15)
153 #define REMODER_RMON_STATISTICS 0x00001000
154 #define REMODER_RX_EXTENDED_FILTERING 0x00000800
155 #define REMODER_NUM_OF_QUEUES_SHIFT (31-23)
156 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
157 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
158 #define REMODER_IP_CHECKSUM_CHECK 0x00000002
159 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
161 #define REMODER_INIT_VALUE 0
163 /* BMRx - Bus Mode Register */
165 #define BMR_BO_BE 0x10
166 #define BMR_DTB_SECONDARY_BUS 0x02
167 #define BMR_BDB_SECONDARY_BUS 0x01
170 #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
172 /* UEC UCCS (Ethernet Status Register)
174 #define UCCS_BPR 0x02
175 #define UCCS_PAU 0x02
176 #define UCCS_MPD 0x01
178 /* UEC MIIMCFG (MII Management Configuration Register)
180 #define MIIMCFG_RESET_MANAGEMENT 0x80000000
181 #define MIIMCFG_NO_PREAMBLE 0x00000010
182 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
183 #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
184 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
185 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
186 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
187 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
188 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
189 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
190 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
192 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
193 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
195 /* UEC MIIMCOM (MII Management Command Register)
197 #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
198 #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
200 /* UEC MIIMADD (MII Management Address Register)
202 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
203 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
205 /* UEC MIIMCON (MII Management Control Register)
207 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
208 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
210 /* UEC MIIMIND (MII Management Indicator Register)
212 #define MIIMIND_NOT_VALID 0x00000004
213 #define MIIMIND_SCAN 0x00000002
214 #define MIIMIND_BUSY 0x00000001
216 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
218 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
219 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
221 /* UEC UESCR (Ethernet Statistics Control Register)
223 #define UESCR_AUTOZ 0x8000
224 #define UESCR_CLRCNT 0x4000
225 #define UESCR_MAXCOV_SHIFT (15 - 7)
226 #define UESCR_SCOV_SHIFT (15 - 15)
228 /****** Tx data struct collection ******/
229 /* Tx thread data, each Tx thread has one this struct.
231 typedef struct uec_thread_data_tx
{
233 } __attribute__ ((packed
)) uec_thread_data_tx_t
;
235 /* Tx thread parameter, each Tx thread has one this struct.
237 typedef struct uec_thread_tx_pram
{
239 } __attribute__ ((packed
)) uec_thread_tx_pram_t
;
241 /* Send queue queue-descriptor, each Tx queue has one this QD
243 typedef struct uec_send_queue_qd
{
244 u32 bd_ring_base
; /* pointer to BD ring base address */
246 u32 last_bd_completed_address
; /* last entry in BD ring */
248 } __attribute__ ((packed
)) uec_send_queue_qd_t
;
250 /* Send queue memory region */
251 typedef struct uec_send_queue_mem_region
{
252 uec_send_queue_qd_t sqqd
[MAX_TX_QUEUES
];
253 } __attribute__ ((packed
)) uec_send_queue_mem_region_t
;
257 typedef struct uec_scheduler
{
258 u16 cpucount0
; /* CPU packet counter */
259 u16 cpucount1
; /* CPU packet counter */
260 u16 cecount0
; /* QE packet counter */
261 u16 cecount1
; /* QE packet counter */
262 u16 cpucount2
; /* CPU packet counter */
263 u16 cpucount3
; /* CPU packet counter */
264 u16 cecount2
; /* QE packet counter */
265 u16 cecount3
; /* QE packet counter */
266 u16 cpucount4
; /* CPU packet counter */
267 u16 cpucount5
; /* CPU packet counter */
268 u16 cecount4
; /* QE packet counter */
269 u16 cecount5
; /* QE packet counter */
270 u16 cpucount6
; /* CPU packet counter */
271 u16 cpucount7
; /* CPU packet counter */
272 u16 cecount6
; /* QE packet counter */
273 u16 cecount7
; /* QE packet counter */
274 u32 weightstatus
[MAX_TX_QUEUES
]; /* accumulated weight factor */
275 u32 rtsrshadow
; /* temporary variable handled by QE */
276 u32 time
; /* temporary variable handled by QE */
277 u32 ttl
; /* temporary variable handled by QE */
278 u32 mblinterval
; /* max burst length interval */
279 u16 nortsrbytetime
; /* normalized value of byte time in tsr units */
282 u8 strictpriorityq
; /* Strict Priority Mask register */
283 u8 txasap
; /* Transmit ASAP register */
284 u8 extrabw
; /* Extra BandWidth register */
285 u8 oldwfqmask
; /* temporary variable handled by QE */
286 u8 weightfactor
[MAX_TX_QUEUES
]; /**< weight factor for queues */
287 u32 minw
; /* temporary variable handled by QE */
289 } __attribute__ ((packed
)) uec_scheduler_t
;
291 /* Tx firmware counters
293 typedef struct uec_tx_firmware_statistics_pram
{
294 u32 sicoltx
; /* single collision */
295 u32 mulcoltx
; /* multiple collision */
296 u32 latecoltxfr
; /* late collision */
297 u32 frabortduecol
; /* frames aborted due to tx collision */
298 u32 frlostinmactxer
; /* frames lost due to internal MAC error tx */
299 u32 carriersenseertx
; /* carrier sense error */
300 u32 frtxok
; /* frames transmitted OK */
301 u32 txfrexcessivedefer
;
302 u32 txpkts256
; /* total packets(including bad) 256~511 B */
303 u32 txpkts512
; /* total packets(including bad) 512~1023B */
304 u32 txpkts1024
; /* total packets(including bad) 1024~1518B */
305 u32 txpktsjumbo
; /* total packets(including bad) >1024 */
306 } __attribute__ ((packed
)) uec_tx_firmware_statistics_pram_t
;
308 /* Tx global parameter table
310 typedef struct uec_tx_global_pram
{
314 u32 schedulerbasepointer
;
317 u8 iphoffset
[MAX_IPH_OFFSET_ENTRY
];
321 } __attribute__ ((packed
)) uec_tx_global_pram_t
;
324 /****** Rx data struct collection ******/
325 /* Rx thread data, each Rx thread has one this struct.
327 typedef struct uec_thread_data_rx
{
329 } __attribute__ ((packed
)) uec_thread_data_rx_t
;
331 /* Rx thread parameter, each Rx thread has one this struct.
333 typedef struct uec_thread_rx_pram
{
335 } __attribute__ ((packed
)) uec_thread_rx_pram_t
;
337 /* Rx firmware counters
339 typedef struct uec_rx_firmware_statistics_pram
{
340 u32 frrxfcser
; /* frames with crc error */
341 u32 fraligner
; /* frames with alignment error */
342 u32 inrangelenrxer
; /* in range length error */
343 u32 outrangelenrxer
; /* out of range length error */
344 u32 frtoolong
; /* frame too long */
346 u32 verylongevent
; /* very long event */
347 u32 symbolerror
; /* symbol error */
348 u32 dropbsy
; /* drop because of BD not ready */
350 u32 mismatchdrop
; /* drop because of MAC filtering */
351 u32 underpkts
; /* total frames less than 64 octets */
352 u32 pkts256
; /* total frames(including bad)256~511 B */
353 u32 pkts512
; /* total frames(including bad)512~1023 B */
354 u32 pkts1024
; /* total frames(including bad)1024~1518 B */
355 u32 pktsjumbo
; /* total frames(including bad) >1024 B */
357 u32 pausefr
; /* pause frames */
362 } __attribute__ ((packed
)) uec_rx_firmware_statistics_pram_t
;
364 /* Rx interrupt coalescing entry, each Rx queue has one this entry.
366 typedef struct uec_rx_interrupt_coalescing_entry
{
369 } __attribute__ ((packed
)) uec_rx_interrupt_coalescing_entry_t
;
371 typedef struct uec_rx_interrupt_coalescing_table
{
372 uec_rx_interrupt_coalescing_entry_t entry
[MAX_RX_QUEUES
];
373 } __attribute__ ((packed
)) uec_rx_interrupt_coalescing_table_t
;
375 /* RxBD queue entry, each Rx queue has one this entry.
377 typedef struct uec_rx_bd_queues_entry
{
378 u32 bdbaseptr
; /* BD base pointer */
379 u32 bdptr
; /* BD pointer */
380 u32 externalbdbaseptr
; /* external BD base pointer */
381 u32 externalbdptr
; /* external BD pointer */
382 } __attribute__ ((packed
)) uec_rx_bd_queues_entry_t
;
384 /* Rx global paramter table
386 typedef struct uec_rx_global_pram
{
387 u32 remoder
; /* ethernet mode reg. */
388 u32 rqptr
; /* base pointer to the Rx Queues */
393 u8 rxgstpack
; /* ack on GRACEFUL STOP RX command */
394 u32 rxrmonbaseptr
; /* Rx RMON statistics base */
396 u32 intcoalescingptr
; /* Interrupt coalescing table pointer */
400 u16 mrblr
; /* max receive buffer length reg. */
401 u32 rbdqptr
; /* RxBD parameter table description */
402 u16 mflr
; /* max frame length reg. */
403 u16 minflr
; /* min frame length reg. */
404 u16 maxd1
; /* max dma1 length reg. */
405 u16 maxd2
; /* max dma2 length reg. */
406 u32 ecamptr
; /* external CAM address */
407 u32 l2qt
; /* VLAN priority mapping table. */
408 u32 l3qt
[0x8]; /* IP priority mapping table. */
409 u16 vlantype
; /* vlan type */
410 u16 vlantci
; /* default vlan tci */
411 u8 addressfiltering
[64];/* address filtering data structure */
412 u32 exfGlobalParam
; /* extended filtering global parameters */
413 u8 res6
[0x100-0xC4]; /* Initialize to zero */
414 } __attribute__ ((packed
)) uec_rx_global_pram_t
;
416 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
419 /****** UEC common ******/
420 /* UCC statistics - hardware counters
422 typedef struct uec_hardware_statistics
{
438 } __attribute__ ((packed
)) uec_hardware_statistics_t
;
440 /* InitEnet command parameter
442 typedef struct uec_init_cmd_pram
{
449 u8 largestexternallookupkeysize
;
451 u32 rxthread
[MAX_ENET_INIT_PARAM_ENTRIES_RX
]; /* rx threads */
452 u8 res2
[0x38 - 0x30];
453 u32 txglobal
; /* tx global */
454 u32 txthread
[MAX_ENET_INIT_PARAM_ENTRIES_TX
]; /* tx threads */
456 } __attribute__ ((packed
)) uec_init_cmd_pram_t
;
458 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
459 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
461 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f
462 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
463 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000
464 #define ENET_INIT_PARAM_SNUM_SHIFT 24
466 #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
467 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
468 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
469 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
470 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
472 /* structure representing 82xx Address Filtering Enet Address in PRAM
474 typedef struct uec_82xx_enet_address
{
476 u16 h
; /* address (MSB) */
478 u16 l
; /* address (LSB) */
479 } __attribute__ ((packed
)) uec_82xx_enet_address_t
;
481 /* structure representing 82xx Address Filtering PRAM
483 typedef struct uec_82xx_address_filtering_pram
{
484 u32 iaddr_h
; /* individual address filter, high */
485 u32 iaddr_l
; /* individual address filter, low */
486 u32 gaddr_h
; /* group address filter, high */
487 u32 gaddr_l
; /* group address filter, low */
488 uec_82xx_enet_address_t taddr
;
489 uec_82xx_enet_address_t paddr
[4];
491 } __attribute__ ((packed
)) uec_82xx_address_filtering_pram_t
;
495 typedef struct buffer_descriptor
{
499 } __attribute__ ((packed
)) qe_bd_t
, *p_bd_t
;
501 #define SIZEOFBD sizeof(qe_bd_t)
505 #define BD_WRAP 0x2000
506 #define BD_INT 0x1000
507 #define BD_LAST 0x0800
508 #define BD_CLEAN 0x3000
512 #define TxBD_READY 0x8000
513 #define TxBD_PADCRC 0x4000
514 #define TxBD_WRAP BD_WRAP
515 #define TxBD_INT BD_INT
516 #define TxBD_LAST BD_LAST
517 #define TxBD_TXCRC 0x0400
518 #define TxBD_DEF 0x0200
519 #define TxBD_PP 0x0100
520 #define TxBD_LC 0x0080
521 #define TxBD_RL 0x0040
522 #define TxBD_RC 0x003C
523 #define TxBD_UNDERRUN 0x0002
524 #define TxBD_TRUNC 0x0001
526 #define TxBD_ERROR (TxBD_UNDERRUN | TxBD_TRUNC)
530 #define RxBD_EMPTY 0x8000
531 #define RxBD_OWNER 0x4000
532 #define RxBD_WRAP BD_WRAP
533 #define RxBD_INT BD_INT
534 #define RxBD_LAST BD_LAST
535 #define RxBD_FIRST 0x0400
536 #define RxBD_CMR 0x0200
537 #define RxBD_MISS 0x0100
538 #define RxBD_BCAST 0x0080
539 #define RxBD_MCAST 0x0040
540 #define RxBD_LG 0x0020
541 #define RxBD_NO 0x0010
542 #define RxBD_SHORT 0x0008
543 #define RxBD_CRCERR 0x0004
544 #define RxBD_OVERRUN 0x0002
545 #define RxBD_IPCH 0x0001
547 #define RxBD_ERROR (RxBD_LG | RxBD_NO | RxBD_SHORT | \
548 RxBD_CRCERR | RxBD_OVERRUN)
552 #define BD_STATUS(_bd) (((p_bd_t)(_bd))->status)
553 #define BD_STATUS_SET(_bd, _val) (((p_bd_t)(_bd))->status = _val)
554 #define BD_LENGTH(_bd) (((p_bd_t)(_bd))->len)
555 #define BD_LENGTH_SET(_bd, _val) (((p_bd_t)(_bd))->len = _val)
556 #define BD_DATA_CLEAR(_bd) (((p_bd_t)(_bd))->data = 0)
557 #define BD_IS_DATA(_bd) (((p_bd_t)(_bd))->data)
558 #define BD_DATA(_bd) ((u8 *)(((p_bd_t)(_bd))->data))
559 #define BD_DATA_SET(_bd, _data) (((p_bd_t)(_bd))->data = (u32)(_data))
560 #define BD_ADVANCE(_bd,_status,_base) \
561 (((_status) & BD_WRAP) ? (_bd) = ((p_bd_t)(_base)) : ++(_bd))
565 typedef struct uec_rx_prefetched_bds
{
566 qe_bd_t bd
[MAX_PREFETCHED_BDS
]; /* prefetched bd */
567 } __attribute__ ((packed
)) uec_rx_prefetched_bds_t
;
571 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
572 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
573 #define UEC_THREAD_RX_PRAM_ALIGNMENT 128
574 #define UEC_THREAD_TX_PRAM_ALIGNMENT 64
575 #define UEC_THREAD_DATA_ALIGNMENT 256
576 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
577 #define UEC_SCHEDULER_ALIGNMENT 4
578 #define UEC_TX_STATISTICS_ALIGNMENT 4
579 #define UEC_RX_STATISTICS_ALIGNMENT 4
580 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
581 #define UEC_RX_BD_QUEUES_ALIGNMENT 8
582 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
583 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
584 #define UEC_RX_BD_RING_ALIGNMENT 32
585 #define UEC_TX_BD_RING_ALIGNMENT 32
586 #define UEC_MRBLR_ALIGNMENT 128
587 #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
588 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
589 #define UEC_RX_DATA_BUF_ALIGNMENT 64
591 #define UEC_VLAN_PRIORITY_MAX 8
592 #define UEC_IP_PRIORITY_MAX 64
593 #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
594 #define UEC_RX_BD_RING_SIZE_MIN 8
595 #define UEC_TX_BD_RING_SIZE_MIN 2
599 typedef enum enet_speed
{
600 ENET_SPEED_10BT
, /* 10 Base T */
601 ENET_SPEED_100BT
, /* 100 Base T */
602 ENET_SPEED_1000BT
/* 1000 Base T */
605 /* Ethernet Address Type.
607 typedef enum enet_addr_type
{
608 ENET_ADDR_TYPE_INDIVIDUAL
,
609 ENET_ADDR_TYPE_GROUP
,
610 ENET_ADDR_TYPE_BROADCAST
613 /* TBI / MII Set Register
615 typedef enum enet_tbi_mii_reg
{
616 ENET_TBI_MII_CR
= 0x00,
617 ENET_TBI_MII_SR
= 0x01,
618 ENET_TBI_MII_ANA
= 0x04,
619 ENET_TBI_MII_ANLPBPA
= 0x05,
620 ENET_TBI_MII_ANEX
= 0x06,
621 ENET_TBI_MII_ANNPT
= 0x07,
622 ENET_TBI_MII_ANLPANP
= 0x08,
623 ENET_TBI_MII_EXST
= 0x0F,
624 ENET_TBI_MII_JD
= 0x10,
625 ENET_TBI_MII_TBICON
= 0x11
626 } enet_tbi_mii_reg_e
;
628 /* TBI MDIO register bit fields*/
629 #define TBICON_CLK_SELECT 0x0020
630 #define TBIANA_ASYMMETRIC_PAUSE 0x0100
631 #define TBIANA_SYMMETRIC_PAUSE 0x0080
632 #define TBIANA_HALF_DUPLEX 0x0040
633 #define TBIANA_FULL_DUPLEX 0x0020
634 #define TBICR_PHY_RESET 0x8000
635 #define TBICR_ANEG_ENABLE 0x1000
636 #define TBICR_RESTART_ANEG 0x0200
637 #define TBICR_FULL_DUPLEX 0x0100
638 #define TBICR_SPEED1_SET 0x0040
640 #define TBIANA_SETTINGS ( \
641 TBIANA_ASYMMETRIC_PAUSE \
642 | TBIANA_SYMMETRIC_PAUSE \
643 | TBIANA_FULL_DUPLEX \
646 #define TBICR_SETTINGS ( \
648 | TBICR_ANEG_ENABLE \
649 | TBICR_FULL_DUPLEX \
653 /* UEC number of threads
655 typedef enum uec_num_of_threads
{
656 UEC_NUM_OF_THREADS_1
= 0x1, /* 1 */
657 UEC_NUM_OF_THREADS_2
= 0x2, /* 2 */
658 UEC_NUM_OF_THREADS_4
= 0x0, /* 4 */
659 UEC_NUM_OF_THREADS_6
= 0x3, /* 6 */
660 UEC_NUM_OF_THREADS_8
= 0x4 /* 8 */
661 } uec_num_of_threads_e
;
663 /* UEC ethernet interface type
665 typedef enum enet_interface
{
675 ENET_1000_RGMII_RXID
,
676 ENET_1000_RGMII_TXID
,
682 /* UEC initialization info struct
684 #define STD_UEC_INFO(num) \
687 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
688 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
689 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
690 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
692 .num_threads_tx = UEC_NUM_OF_THREADS_1, \
693 .num_threads_rx = UEC_NUM_OF_THREADS_1, \
694 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
695 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
696 .tx_bd_ring_len = 16, \
697 .rx_bd_ring_len = 16, \
698 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
699 .enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \
702 typedef struct uec_info
{
703 ucc_fast_info_t uf_info
;
704 uec_num_of_threads_e num_threads_tx
;
705 uec_num_of_threads_e num_threads_rx
;
706 unsigned int risc_tx
;
707 unsigned int risc_rx
;
711 enet_interface_e enet_interface
;
714 /* UEC driver initialized info
716 #define MAX_RXBUF_LEN 1536
717 #define MAX_FRAME_LEN 1518
718 #define MIN_FRAME_LEN 64
719 #define MAX_DMA1_LEN 1520
720 #define MAX_DMA2_LEN 1520
722 /* UEC driver private struct
724 typedef struct uec_private
{
725 uec_info_t
*uec_info
;
726 ucc_fast_private_t
*uccf
;
727 struct eth_device
*dev
;
729 uec_mii_t
*uec_mii_regs
;
730 /* enet init command parameter */
731 uec_init_cmd_pram_t
*p_init_enet_param
;
732 u32 init_enet_param_offset
;
733 /* Rx and Tx paramter */
734 uec_rx_global_pram_t
*p_rx_glbl_pram
;
735 u32 rx_glbl_pram_offset
;
736 uec_tx_global_pram_t
*p_tx_glbl_pram
;
737 u32 tx_glbl_pram_offset
;
738 uec_send_queue_mem_region_t
*p_send_q_mem_reg
;
739 u32 send_q_mem_reg_offset
;
740 uec_thread_data_tx_t
*p_thread_data_tx
;
741 u32 thread_dat_tx_offset
;
742 uec_thread_data_rx_t
*p_thread_data_rx
;
743 u32 thread_dat_rx_offset
;
744 uec_rx_bd_queues_entry_t
*p_rx_bd_qs_tbl
;
745 u32 rx_bd_qs_tbl_offset
;
748 u32 tx_bd_ring_offset
;
750 u32 rx_bd_ring_offset
;
753 volatile qe_bd_t
*txBd
;
754 volatile qe_bd_t
*rxBd
;
758 int grace_stopped_tx
;
759 int grace_stopped_rx
;
762 struct uec_mii_info
*mii_info
;
768 int uec_initialize(bd_t
*bis
, uec_info_t
*uec_info
);
769 int uec_eth_init(bd_t
*bis
, uec_info_t
*uecs
, int num
);
770 int uec_standard_init(bd_t
*bis
);
771 #endif /* __UEC_H__ */