drivers/qe/uec_phy.c

   1 /*
   2  * Copyright (C) 2005,2010 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Shlomi Gridish
   5  *
   6  * Description: UCC GETH Driver -- PHY handling
   7  *              Driver for UEC on QE
   8  *              Based on 8260_io/fcc_enet.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "common.h"
  18 #include "net.h"
  19 #include "malloc.h"
  20 #include "asm/errno.h"
  21 #include "asm/immap_qe.h"
  22 #include "asm/io.h"
  23 #include "qe.h"
  24 #include "uccf.h"
  25 #include "uec.h"
  26 #include "uec_phy.h"
  27 #include "miiphy.h"
  28
  29 #define ugphy_printk(format, arg...)  \
  30         printf(format "\n", ## arg)
  31
  32 #define ugphy_dbg(format, arg...)            \
  33         ugphy_printk(format , ## arg)
  34 #define ugphy_err(format, arg...)            \
  35         ugphy_printk(format , ## arg)
  36 #define ugphy_info(format, arg...)           \
  37         ugphy_printk(format , ## arg)
  38 #define ugphy_warn(format, arg...)           \
  39         ugphy_printk(format , ## arg)
  40
  41 #ifdef UEC_VERBOSE_DEBUG
  42 #define ugphy_vdbg ugphy_dbg
  43 #else
  44 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
  45 #endif /* UEC_VERBOSE_DEBUG */
  46
  47 /*--------------------------------------------------------------------+
  48  * Fixed PHY (PHY-less) support for Ethernet Ports.
  49  *
  50  * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
  51  *--------------------------------------------------------------------*/
  52
  53 /*
  54  * Some boards do not have a PHY for each ethernet port. These ports are known
  55  * as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
  56  * CONFIG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
  57  * When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
  58  * and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
  59  * speed and duplex should be for the port.
  60  *
  61  * Example board header configuration file:
  62  *     #define CONFIG_FIXED_PHY   0xFFFFFFFF
  63  *     #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
  64  *
  65  *     #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  66  *     #define CONFIG_SYS_UEC2_PHY_ADDR 0x02
  67  *     #define CONFIG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
  68  *     #define CONFIG_SYS_UEC4_PHY_ADDR 0x04
  69  *
  70  *     #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
  71  *                 {name, speed, duplex},
  72  *
  73  *     #define CONFIG_SYS_FIXED_PHY_PORTS \
  74  *                 CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
  75  *                 CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
  76  */
  77
  78 #ifndef CONFIG_FIXED_PHY
  79 #define CONFIG_FIXED_PHY        0xFFFFFFFF /* Fixed PHY (PHY-less) */
  80 #endif
  81
  82 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
  83 #define CONFIG_SYS_FIXED_PHY_PORTS      /* default is an empty array */
  84 #endif
  85
  86 struct fixed_phy_port {
  87         char name[NAMESIZE];    /* ethernet port name */
  88         unsigned int speed;     /* specified speed 10,100 or 1000 */
  89         unsigned int duplex;    /* specified duplex FULL or HALF */
  90 };
  91
  92 static const struct fixed_phy_port fixed_phy_port[] = {
  93         CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
  94 };
  95
  96 /*--------------------------------------------------------------------+
  97  * BitBang MII support for ethernet ports
  98  *
  99  * Based from MPC8560ADS implementation
 100  *--------------------------------------------------------------------*/
 101 /*
 102  * Example board header file to define bitbang ethernet ports:
 103  *
 104  * #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
 105  * #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
 106 */
 107 #ifndef CONFIG_SYS_BITBANG_PHY_PORTS
 108 #define CONFIG_SYS_BITBANG_PHY_PORTS    /* default is an empty array */
 109 #endif
 110
 111 #if defined(CONFIG_BITBANGMII)
 112 static const char *bitbang_phy_port[] = {
 113         CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
 114 };
 115 #endif /* CONFIG_BITBANGMII */
 116
 117 static void config_genmii_advert (struct uec_mii_info *mii_info);
 118 static void genmii_setup_forced (struct uec_mii_info *mii_info);
 119 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
 120 static int gbit_config_aneg (struct uec_mii_info *mii_info);
 121 static int genmii_config_aneg (struct uec_mii_info *mii_info);
 122 static int genmii_update_link (struct uec_mii_info *mii_info);
 123 static int genmii_read_status (struct uec_mii_info *mii_info);
 124 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
 125 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
 126
 127 /* Write value to the PHY for this device to the register at regnum, */
 128 /* waiting until the write is done before it returns.  All PHY */
 129 /* configuration has to be done through the TSEC1 MIIM regs */
 130 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
 131 {
 132         uec_private_t *ugeth = (uec_private_t *) dev->priv;
 133         uec_mii_t *ug_regs;
 134         enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 135         u32 tmp_reg;
 136
 137
 138 #if defined(CONFIG_BITBANGMII)
 139         u32 i = 0;
 140
 141         for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
 142                 if (strncmp(dev->name, bitbang_phy_port[i],
 143                         sizeof(dev->name)) == 0) {
 144                         (void)bb_miiphy_write(NULL, mii_id, regnum, value);
 145                         return;
 146                 }
 147         }
 148 #endif /* CONFIG_BITBANGMII */
 149
 150         ug_regs = ugeth->uec_mii_regs;
 151
 152         /* Stop the MII management read cycle */
 153         out_be32 (&ug_regs->miimcom, 0);
 154         /* Setting up the MII Mangement Address Register */
 155         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 156         out_be32 (&ug_regs->miimadd, tmp_reg);
 157
 158         /* Setting up the MII Mangement Control Register with the value */
 159         out_be32 (&ug_regs->miimcon, (u32) value);
 160         sync();
 161
 162         /* Wait till MII management write is complete */
 163         while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
 164 }
 165
 166 /* Reads from register regnum in the PHY for device dev, */
 167 /* returning the value.  Clears miimcom first.  All PHY */
 168 /* configuration has to be done through the TSEC1 MIIM regs */
 169 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
 170 {
 171         uec_private_t *ugeth = (uec_private_t *) dev->priv;
 172         uec_mii_t *ug_regs;
 173         enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
 174         u32 tmp_reg;
 175         u16 value;
 176
 177
 178 #if defined(CONFIG_BITBANGMII)
 179         u32 i = 0;
 180
 181         for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
 182                 if (strncmp(dev->name, bitbang_phy_port[i],
 183                         sizeof(dev->name)) == 0) {
 184                         (void)bb_miiphy_read(NULL, mii_id, regnum, &value);
 185                         return (value);
 186                 }
 187         }
 188 #endif /* CONFIG_BITBANGMII */
 189
 190         ug_regs = ugeth->uec_mii_regs;
 191
 192         /* Setting up the MII Mangement Address Register */
 193         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 194         out_be32 (&ug_regs->miimadd, tmp_reg);
 195
 196         /* clear MII management command cycle */
 197         out_be32 (&ug_regs->miimcom, 0);
 198         sync();
 199
 200         /* Perform an MII management read cycle */
 201         out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
 202
 203         /* Wait till MII management write is complete */
 204         while ((in_be32 (&ug_regs->miimind)) &
 205                (MIIMIND_NOT_VALID | MIIMIND_BUSY));
 206
 207         /* Read MII management status  */
 208         value = (u16) in_be32 (&ug_regs->miimstat);
 209         if (value == 0xffff)
 210                 ugphy_vdbg
 211                         ("read wrong value : mii_id %d,mii_reg %d, base %08x",
 212                          mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
 213
 214         return (value);
 215 }
 216
 217 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
 218 {
 219         if (mii_info->phyinfo->ack_interrupt)
 220                 mii_info->phyinfo->ack_interrupt (mii_info);
 221 }
 222
 223 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
 224                                   u32 interrupts)
 225 {
 226         mii_info->interrupts = interrupts;
 227         if (mii_info->phyinfo->config_intr)
 228                 mii_info->phyinfo->config_intr (mii_info);
 229 }
 230
 231 /* Writes MII_ADVERTISE with the appropriate values, after
 232  * sanitizing advertise to make sure only supported features
 233  * are advertised
 234  */
 235 static void config_genmii_advert (struct uec_mii_info *mii_info)
 236 {
 237         u32 advertise;
 238         u16 adv;
 239
 240         /* Only allow advertising what this PHY supports */
 241         mii_info->advertising &= mii_info->phyinfo->features;
 242         advertise = mii_info->advertising;
 243
 244         /* Setup standard advertisement */
 245         adv = phy_read (mii_info, PHY_ANAR);
 246         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 247         if (advertise & ADVERTISED_10baseT_Half)
 248                 adv |= ADVERTISE_10HALF;
 249         if (advertise & ADVERTISED_10baseT_Full)
 250                 adv |= ADVERTISE_10FULL;
 251         if (advertise & ADVERTISED_100baseT_Half)
 252                 adv |= ADVERTISE_100HALF;
 253         if (advertise & ADVERTISED_100baseT_Full)
 254                 adv |= ADVERTISE_100FULL;
 255         phy_write (mii_info, PHY_ANAR, adv);
 256 }
 257
 258 static void genmii_setup_forced (struct uec_mii_info *mii_info)
 259 {
 260         u16 ctrl;
 261         u32 features = mii_info->phyinfo->features;
 262
 263         ctrl = phy_read (mii_info, PHY_BMCR);
 264
 265         ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
 266                   PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
 267         ctrl |= PHY_BMCR_RESET;
 268
 269         switch (mii_info->speed) {
 270         case SPEED_1000:
 271                 if (features & (SUPPORTED_1000baseT_Half
 272                                 | SUPPORTED_1000baseT_Full)) {
 273                         ctrl |= PHY_BMCR_1000_MBPS;
 274                         break;
 275                 }
 276                 mii_info->speed = SPEED_100;
 277         case SPEED_100:
 278                 if (features & (SUPPORTED_100baseT_Half
 279                                 | SUPPORTED_100baseT_Full)) {
 280                         ctrl |= PHY_BMCR_100_MBPS;
 281                         break;
 282                 }
 283                 mii_info->speed = SPEED_10;
 284         case SPEED_10:
 285                 if (features & (SUPPORTED_10baseT_Half
 286                                 | SUPPORTED_10baseT_Full))
 287                         break;
 288         default:                /* Unsupported speed! */
 289                 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
 290                 break;
 291         }
 292
 293         phy_write (mii_info, PHY_BMCR, ctrl);
 294 }
 295
 296 /* Enable and Restart Autonegotiation */
 297 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
 298 {
 299         u16 ctl;
 300
 301         ctl = phy_read (mii_info, PHY_BMCR);
 302         ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 303         phy_write (mii_info, PHY_BMCR, ctl);
 304 }
 305
 306 static int gbit_config_aneg (struct uec_mii_info *mii_info)
 307 {
 308         u16 adv;
 309         u32 advertise;
 310
 311         if (mii_info->autoneg) {
 312                 /* Configure the ADVERTISE register */
 313                 config_genmii_advert (mii_info);
 314                 advertise = mii_info->advertising;
 315
 316                 adv = phy_read (mii_info, MII_1000BASETCONTROL);
 317                 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
 318                          MII_1000BASETCONTROL_HALFDUPLEXCAP);
 319                 if (advertise & SUPPORTED_1000baseT_Half)
 320                         adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
 321                 if (advertise & SUPPORTED_1000baseT_Full)
 322                         adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
 323                 phy_write (mii_info, MII_1000BASETCONTROL, adv);
 324
 325                 /* Start/Restart aneg */
 326                 genmii_restart_aneg (mii_info);
 327         } else
 328                 genmii_setup_forced (mii_info);
 329
 330         return 0;
 331 }
 332
 333 static int marvell_config_aneg (struct uec_mii_info *mii_info)
 334 {
 335         /* The Marvell PHY has an errata which requires
 336          * that certain registers get written in order
 337          * to restart autonegotiation */
 338         phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
 339
 340         phy_write (mii_info, 0x1d, 0x1f);
 341         phy_write (mii_info, 0x1e, 0x200c);
 342         phy_write (mii_info, 0x1d, 0x5);
 343         phy_write (mii_info, 0x1e, 0);
 344         phy_write (mii_info, 0x1e, 0x100);
 345
 346         gbit_config_aneg (mii_info);
 347
 348         return 0;
 349 }
 350
 351 static int genmii_config_aneg (struct uec_mii_info *mii_info)
 352 {
 353         if (mii_info->autoneg) {
 354                 /* Speed up the common case, if link is already up, speed and
 355                    duplex match, skip auto neg as it already matches */
 356                 if (!genmii_read_status(mii_info) && mii_info->link)
 357                         if (mii_info->duplex == DUPLEX_FULL &&
 358                             mii_info->speed == SPEED_100)
 359                                 if (mii_info->advertising &
 360                                     ADVERTISED_100baseT_Full)
 361                                         return 0;
 362
 363                 config_genmii_advert (mii_info);
 364                 genmii_restart_aneg (mii_info);
 365         } else
 366                 genmii_setup_forced (mii_info);
 367
 368         return 0;
 369 }
 370
 371 static int genmii_update_link (struct uec_mii_info *mii_info)
 372 {
 373         u16 status;
 374
 375         /* Status is read once to clear old link state */
 376         phy_read (mii_info, PHY_BMSR);
 377
 378         /*
 379          * Wait if the link is up, and autonegotiation is in progress
 380          * (ie - we're capable and it's not done)
 381          */
 382         status = phy_read(mii_info, PHY_BMSR);
 383         if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
 384             && !(status & PHY_BMSR_AUTN_COMP)) {
 385                 int i = 0;
 386
 387                 while (!(status & PHY_BMSR_AUTN_COMP)) {
 388                         /*
 389                          * Timeout reached ?
 390                          */
 391                         if (i > UGETH_AN_TIMEOUT) {
 392                                 mii_info->link = 0;
 393                                 return 0;
 394                         }
 395
 396                         i++;
 397                         udelay(1000);   /* 1 ms */
 398                         status = phy_read(mii_info, PHY_BMSR);
 399                 }
 400                 mii_info->link = 1;
 401         } else {
 402                 if (status & PHY_BMSR_LS)
 403                         mii_info->link = 1;
 404                 else
 405                         mii_info->link = 0;
 406         }
 407
 408         return 0;
 409 }
 410
 411 static int genmii_read_status (struct uec_mii_info *mii_info)
 412 {
 413         u16 status;
 414         int err;
 415
 416         /* Update the link, but return if there
 417          * was an error */
 418         err = genmii_update_link (mii_info);
 419         if (err)
 420                 return err;
 421
 422         if (mii_info->autoneg) {
 423                 status = phy_read(mii_info, MII_1000BASETSTATUS);
 424
 425                 if (status & (LPA_1000FULL | LPA_1000HALF)) {
 426                         mii_info->speed = SPEED_1000;
 427                         if (status & LPA_1000FULL)
 428                                 mii_info->duplex = DUPLEX_FULL;
 429                         else
 430                                 mii_info->duplex = DUPLEX_HALF;
 431                 } else {
 432                         status = phy_read(mii_info, PHY_ANLPAR);
 433
 434                         if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
 435                                 mii_info->duplex = DUPLEX_FULL;
 436                         else
 437                                 mii_info->duplex = DUPLEX_HALF;
 438                         if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
 439                                 mii_info->speed = SPEED_100;
 440                         else
 441                                 mii_info->speed = SPEED_10;
 442                 }
 443                 mii_info->pause = 0;
 444         }
 445         /* On non-aneg, we assume what we put in BMCR is the speed,
 446          * though magic-aneg shouldn't prevent this case from occurring
 447          */
 448
 449         return 0;
 450 }
 451
 452 static int bcm_init(struct uec_mii_info *mii_info)
 453 {
 454         struct eth_device *edev = mii_info->dev;
 455         uec_private_t *uec = edev->priv;
 456
 457         gbit_config_aneg(mii_info);
 458
 459         if ((uec->uec_info->enet_interface_type == RGMII_RXID) &&
 460            (uec->uec_info->speed == 1000)) {
 461                 u16 val;
 462                 int cnt = 50;
 463
 464                 /* Wait for aneg to complete. */
 465                 do
 466                         val = phy_read(mii_info, PHY_BMSR);
 467                 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
 468
 469                 /* Set RDX clk delay. */
 470                 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
 471
 472                 val = phy_read(mii_info, 0x18);
 473                 /* Set RDX-RXC skew. */
 474                 val |= (1 << 8);
 475                 val |= (7 | (7 << 12));
 476                 /* Write bits 14:0. */
 477                 val |= (1 << 15);
 478                 phy_write(mii_info, 0x18, val);
 479         }
 480
 481          return 0;
 482 }
 483
 484 static int marvell_init(struct uec_mii_info *mii_info)
 485 {
 486         struct eth_device *edev = mii_info->dev;
 487         uec_private_t *uec = edev->priv;
 488         enum fsl_phy_enet_if iface = uec->uec_info->enet_interface_type;
 489         int     speed = uec->uec_info->speed;
 490
 491         if ((speed == 1000) &&
 492            (iface == RGMII_ID ||
 493             iface == RGMII_RXID ||
 494             iface == RGMII_TXID)) {
 495                 int temp;
 496
 497                 temp = phy_read(mii_info, MII_M1111_PHY_EXT_CR);
 498                 if (iface == RGMII_ID) {
 499                         temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
 500                 } else if (iface == RGMII_RXID) {
 501                         temp &= ~MII_M1111_TX_DELAY;
 502                         temp |= MII_M1111_RX_DELAY;
 503                 } else if (iface == RGMII_TXID) {
 504                         temp &= ~MII_M1111_RX_DELAY;
 505                         temp |= MII_M1111_TX_DELAY;
 506                 }
 507                 phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
 508
 509                 temp = phy_read(mii_info, MII_M1111_PHY_EXT_SR);
 510                 temp &= ~MII_M1111_HWCFG_MODE_MASK;
 511                 temp |= MII_M1111_HWCFG_MODE_RGMII;
 512                 phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
 513
 514                 phy_write(mii_info, PHY_BMCR, PHY_BMCR_RESET);
 515         }
 516
 517         return 0;
 518 }
 519
 520 static int marvell_read_status (struct uec_mii_info *mii_info)
 521 {
 522         u16 status;
 523         int err;
 524
 525         /* Update the link, but return if there
 526          * was an error */
 527         err = genmii_update_link (mii_info);
 528         if (err)
 529                 return err;
 530
 531         /* If the link is up, read the speed and duplex */
 532         /* If we aren't autonegotiating, assume speeds
 533          * are as set */
 534         if (mii_info->autoneg && mii_info->link) {
 535                 int speed;
 536
 537                 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
 538
 539                 /* Get the duplexity */
 540                 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
 541                         mii_info->duplex = DUPLEX_FULL;
 542                 else
 543                         mii_info->duplex = DUPLEX_HALF;
 544
 545                 /* Get the speed */
 546                 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
 547                 switch (speed) {
 548                 case MII_M1011_PHY_SPEC_STATUS_1000:
 549                         mii_info->speed = SPEED_1000;
 550                         break;
 551                 case MII_M1011_PHY_SPEC_STATUS_100:
 552                         mii_info->speed = SPEED_100;
 553                         break;
 554                 default:
 555                         mii_info->speed = SPEED_10;
 556                         break;
 557                 }
 558                 mii_info->pause = 0;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
 565 {
 566         /* Clear the interrupts by reading the reg */
 567         phy_read (mii_info, MII_M1011_IEVENT);
 568
 569         return 0;
 570 }
 571
 572 static int marvell_config_intr (struct uec_mii_info *mii_info)
 573 {
 574         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 575                 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 576         else
 577                 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 578
 579         return 0;
 580 }
 581
 582 static int dm9161_init (struct uec_mii_info *mii_info)
 583 {
 584         /* Reset the PHY */
 585         phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
 586                    PHY_BMCR_RESET);
 587         /* PHY and MAC connect */
 588         phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
 589                    ~PHY_BMCR_ISO);
 590
 591         phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
 592
 593         config_genmii_advert (mii_info);
 594         /* Start/restart aneg */
 595         genmii_config_aneg (mii_info);
 596
 597         return 0;
 598 }
 599
 600 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
 601 {
 602         return 0;
 603 }
 604
 605 static int dm9161_read_status (struct uec_mii_info *mii_info)
 606 {
 607         u16 status;
 608         int err;
 609
 610         /* Update the link, but return if there was an error */
 611         err = genmii_update_link (mii_info);
 612         if (err)
 613                 return err;
 614         /* If the link is up, read the speed and duplex
 615            If we aren't autonegotiating assume speeds are as set */
 616         if (mii_info->autoneg && mii_info->link) {
 617                 status = phy_read (mii_info, MII_DM9161_SCSR);
 618                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
 619                         mii_info->speed = SPEED_100;
 620                 else
 621                         mii_info->speed = SPEED_10;
 622
 623                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
 624                         mii_info->duplex = DUPLEX_FULL;
 625                 else
 626                         mii_info->duplex = DUPLEX_HALF;
 627         }
 628
 629         return 0;
 630 }
 631
 632 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
 633 {
 634         /* Clear the interrupt by reading the reg */
 635         phy_read (mii_info, MII_DM9161_INTR);
 636
 637         return 0;
 638 }
 639
 640 static int dm9161_config_intr (struct uec_mii_info *mii_info)
 641 {
 642         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 643                 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
 644         else
 645                 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
 646
 647         return 0;
 648 }
 649
 650 static void dm9161_close (struct uec_mii_info *mii_info)
 651 {
 652 }
 653
 654 static int fixed_phy_aneg (struct uec_mii_info *mii_info)
 655 {
 656         mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
 657         return 0;
 658 }
 659
 660 static int fixed_phy_read_status (struct uec_mii_info *mii_info)
 661 {
 662         int i = 0;
 663
 664         for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
 665                 if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
 666                                 strlen(mii_info->dev->name)) == 0) {
 667                         mii_info->speed = fixed_phy_port[i].speed;
 668                         mii_info->duplex = fixed_phy_port[i].duplex;
 669                         mii_info->link = 1; /* Link is always UP */
 670                         mii_info->pause = 0;
 671                         break;
 672                 }
 673         }
 674         return 0;
 675 }
 676
 677 static int smsc_config_aneg (struct uec_mii_info *mii_info)
 678 {
 679         return 0;
 680 }
 681
 682 static int smsc_read_status (struct uec_mii_info *mii_info)
 683 {
 684         u16 status;
 685         int err;
 686
 687         /* Update the link, but return if there
 688          * was an error */
 689         err = genmii_update_link (mii_info);
 690         if (err)
 691                 return err;
 692
 693         /* If the link is up, read the speed and duplex */
 694         /* If we aren't autonegotiating, assume speeds
 695          * are as set */
 696         if (mii_info->autoneg && mii_info->link) {
 697                 int     val;
 698
 699                 status = phy_read (mii_info, 0x1f);
 700                 val = (status & 0x1c) >> 2;
 701
 702                 switch (val) {
 703                         case 1:
 704                                 mii_info->duplex = DUPLEX_HALF;
 705                                 mii_info->speed = SPEED_10;
 706                                 break;
 707                         case 5:
 708                                 mii_info->duplex = DUPLEX_FULL;
 709                                 mii_info->speed = SPEED_10;
 710                                 break;
 711                         case 2:
 712                                 mii_info->duplex = DUPLEX_HALF;
 713                                 mii_info->speed = SPEED_100;
 714                                 break;
 715                         case 6:
 716                                 mii_info->duplex = DUPLEX_FULL;
 717                                 mii_info->speed = SPEED_100;
 718                                 break;
 719                 }
 720                 mii_info->pause = 0;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static struct phy_info phy_info_dm9161 = {
 727         .phy_id = 0x0181b880,
 728         .phy_id_mask = 0x0ffffff0,
 729         .name = "Davicom DM9161E",
 730         .init = dm9161_init,
 731         .config_aneg = dm9161_config_aneg,
 732         .read_status = dm9161_read_status,
 733         .close = dm9161_close,
 734 };
 735
 736 static struct phy_info phy_info_dm9161a = {
 737         .phy_id = 0x0181b8a0,
 738         .phy_id_mask = 0x0ffffff0,
 739         .name = "Davicom DM9161A",
 740         .features = MII_BASIC_FEATURES,
 741         .init = dm9161_init,
 742         .config_aneg = dm9161_config_aneg,
 743         .read_status = dm9161_read_status,
 744         .ack_interrupt = dm9161_ack_interrupt,
 745         .config_intr = dm9161_config_intr,
 746         .close = dm9161_close,
 747 };
 748
 749 static struct phy_info phy_info_marvell = {
 750         .phy_id = 0x01410c00,
 751         .phy_id_mask = 0xffffff00,
 752         .name = "Marvell 88E11x1",
 753         .features = MII_GBIT_FEATURES,
 754         .init = &marvell_init,
 755         .config_aneg = &marvell_config_aneg,
 756         .read_status = &marvell_read_status,
 757         .ack_interrupt = &marvell_ack_interrupt,
 758         .config_intr = &marvell_config_intr,
 759 };
 760
 761 static struct phy_info phy_info_bcm5481 = {
 762         .phy_id = 0x0143bca0,
 763         .phy_id_mask = 0xffffff0,
 764         .name = "Broadcom 5481",
 765         .features = MII_GBIT_FEATURES,
 766         .read_status = genmii_read_status,
 767         .init = bcm_init,
 768 };
 769
 770 static struct phy_info phy_info_fixedphy = {
 771         .phy_id = CONFIG_FIXED_PHY,
 772         .phy_id_mask = CONFIG_FIXED_PHY,
 773         .name = "Fixed PHY",
 774         .config_aneg = fixed_phy_aneg,
 775         .read_status = fixed_phy_read_status,
 776 };
 777
 778 static struct phy_info phy_info_smsclan8700 = {
 779         .phy_id = 0x0007c0c0,
 780         .phy_id_mask = 0xfffffff0,
 781         .name = "SMSC LAN8700",
 782         .features = MII_BASIC_FEATURES,
 783         .config_aneg = smsc_config_aneg,
 784         .read_status = smsc_read_status,
 785 };
 786
 787 static struct phy_info phy_info_genmii = {
 788         .phy_id = 0x00000000,
 789         .phy_id_mask = 0x00000000,
 790         .name = "Generic MII",
 791         .features = MII_BASIC_FEATURES,
 792         .config_aneg = genmii_config_aneg,
 793         .read_status = genmii_read_status,
 794 };
 795
 796 static struct phy_info *phy_info[] = {
 797         &phy_info_dm9161,
 798         &phy_info_dm9161a,
 799         &phy_info_marvell,
 800         &phy_info_bcm5481,
 801         &phy_info_smsclan8700,
 802         &phy_info_fixedphy,
 803         &phy_info_genmii,
 804         NULL
 805 };
 806
 807 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
 808 {
 809         return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
 810 }
 811
 812 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
 813 {
 814         mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
 815 }
 816
 817 /* Use the PHY ID registers to determine what type of PHY is attached
 818  * to device dev.  return a struct phy_info structure describing that PHY
 819  */
 820 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
 821 {
 822         u16 phy_reg;
 823         u32 phy_ID;
 824         int i;
 825         struct phy_info *theInfo = NULL;
 826
 827         /* Grab the bits from PHYIR1, and put them in the upper half */
 828         phy_reg = phy_read (mii_info, PHY_PHYIDR1);
 829         phy_ID = (phy_reg & 0xffff) << 16;
 830
 831         /* Grab the bits from PHYIR2, and put them in the lower half */
 832         phy_reg = phy_read (mii_info, PHY_PHYIDR2);
 833         phy_ID |= (phy_reg & 0xffff);
 834
 835         /* loop through all the known PHY types, and find one that */
 836         /* matches the ID we read from the PHY. */
 837         for (i = 0; phy_info[i]; i++)
 838                 if (phy_info[i]->phy_id ==
 839                     (phy_ID & phy_info[i]->phy_id_mask)) {
 840                         theInfo = phy_info[i];
 841                         break;
 842                 }
 843
 844         /* This shouldn't happen, as we have generic PHY support */
 845         if (theInfo == NULL) {
 846                 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
 847                 return NULL;
 848         } else {
 849                 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
 850         }
 851
 852         return theInfo;
 853 }
 854
 855 void marvell_phy_interface_mode (struct eth_device *dev,
 856                                  enum fsl_phy_enet_if type,
 857                                  int speed
 858                                 )
 859 {
 860         uec_private_t *uec = (uec_private_t *) dev->priv;
 861         struct uec_mii_info *mii_info;
 862         u16 status;
 863
 864         if (!uec->mii_info) {
 865                 printf ("%s: the PHY not initialized\n", __FUNCTION__);
 866                 return;
 867         }
 868         mii_info = uec->mii_info;
 869
 870         if (type == RGMII) {
 871                 if (speed == 100) {
 872                         phy_write (mii_info, 0x00, 0x9140);
 873                         phy_write (mii_info, 0x1d, 0x001f);
 874                         phy_write (mii_info, 0x1e, 0x200c);
 875                         phy_write (mii_info, 0x1d, 0x0005);
 876                         phy_write (mii_info, 0x1e, 0x0000);
 877                         phy_write (mii_info, 0x1e, 0x0100);
 878                         phy_write (mii_info, 0x09, 0x0e00);
 879                         phy_write (mii_info, 0x04, 0x01e1);
 880                         phy_write (mii_info, 0x00, 0x9140);
 881                         phy_write (mii_info, 0x00, 0x1000);
 882                         udelay (100000);
 883                         phy_write (mii_info, 0x00, 0x2900);
 884                         phy_write (mii_info, 0x14, 0x0cd2);
 885                         phy_write (mii_info, 0x00, 0xa100);
 886                         phy_write (mii_info, 0x09, 0x0000);
 887                         phy_write (mii_info, 0x1b, 0x800b);
 888                         phy_write (mii_info, 0x04, 0x05e1);
 889                         phy_write (mii_info, 0x00, 0xa100);
 890                         phy_write (mii_info, 0x00, 0x2100);
 891                         udelay (1000000);
 892                 } else if (speed == 10) {
 893                         phy_write (mii_info, 0x14, 0x8e40);
 894                         phy_write (mii_info, 0x1b, 0x800b);
 895                         phy_write (mii_info, 0x14, 0x0c82);
 896                         phy_write (mii_info, 0x00, 0x8100);
 897                         udelay (1000000);
 898                 }
 899         }
 900
 901         /* handle 88e1111 rev.B2 erratum 5.6 */
 902         if (mii_info->autoneg) {
 903                 status = phy_read (mii_info, PHY_BMCR);
 904                 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
 905         }
 906         /* now the B2 will correctly report autoneg completion status */
 907 }
 908
 909 void change_phy_interface_mode (struct eth_device *dev,
 910                                 enum fsl_phy_enet_if type, int speed)
 911 {
 912 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
 913         marvell_phy_interface_mode (dev, type, speed);
 914 #endif
 915 }