drivers/qe/uec_phy.c

   1 /*
   2  * Copyright (C) 2005 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Shlomi Gridish
   5  *
   6  * Description: UCC GETH Driver -- PHY handling
   7  *              Driver for UEC on QE
   8  *              Based on 8260_io/fcc_enet.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "common.h"
  18 #include "net.h"
  19 #include "malloc.h"
  20 #include "asm/errno.h"
  21 #include "asm/immap_qe.h"
  22 #include "asm/io.h"
  23 #include "qe.h"
  24 #include "uccf.h"
  25 #include "uec.h"
  26 #include "uec_phy.h"
  27 #include "miiphy.h"
  28
  29 #if defined(CONFIG_QE)
  30
  31 #define ugphy_printk(format, arg...)  \
  32         printf(format "\n", ## arg)
  33
  34 #define ugphy_dbg(format, arg...)            \
  35         ugphy_printk(format , ## arg)
  36 #define ugphy_err(format, arg...)            \
  37         ugphy_printk(format , ## arg)
  38 #define ugphy_info(format, arg...)           \
  39         ugphy_printk(format , ## arg)
  40 #define ugphy_warn(format, arg...)           \
  41         ugphy_printk(format , ## arg)
  42
  43 #ifdef UEC_VERBOSE_DEBUG
  44 #define ugphy_vdbg ugphy_dbg
  45 #else
  46 #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
  47 #endif /* UEC_VERBOSE_DEBUG */
  48
  49 static void config_genmii_advert (struct uec_mii_info *mii_info);
  50 static void genmii_setup_forced (struct uec_mii_info *mii_info);
  51 static void genmii_restart_aneg (struct uec_mii_info *mii_info);
  52 static int gbit_config_aneg (struct uec_mii_info *mii_info);
  53 static int genmii_config_aneg (struct uec_mii_info *mii_info);
  54 static int genmii_update_link (struct uec_mii_info *mii_info);
  55 static int genmii_read_status (struct uec_mii_info *mii_info);
  56 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum);
  57 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val);
  58
  59 /* Write value to the PHY for this device to the register at regnum, */
  60 /* waiting until the write is done before it returns.  All PHY */
  61 /* configuration has to be done through the TSEC1 MIIM regs */
  62 void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
  63 {
  64         uec_private_t *ugeth = (uec_private_t *) dev->priv;
  65         uec_mii_t *ug_regs;
  66         enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
  67         u32 tmp_reg;
  68
  69         ug_regs = ugeth->uec_mii_regs;
  70
  71         /* Stop the MII management read cycle */
  72         out_be32 (&ug_regs->miimcom, 0);
  73         /* Setting up the MII Mangement Address Register */
  74         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
  75         out_be32 (&ug_regs->miimadd, tmp_reg);
  76
  77         /* Setting up the MII Mangement Control Register with the value */
  78         out_be32 (&ug_regs->miimcon, (u32) value);
  79         sync();
  80
  81         /* Wait till MII management write is complete */
  82         while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY);
  83 }
  84
  85 /* Reads from register regnum in the PHY for device dev, */
  86 /* returning the value.  Clears miimcom first.  All PHY */
  87 /* configuration has to be done through the TSEC1 MIIM regs */
  88 int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
  89 {
  90         uec_private_t *ugeth = (uec_private_t *) dev->priv;
  91         uec_mii_t *ug_regs;
  92         enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
  93         u32 tmp_reg;
  94         u16 value;
  95
  96         ug_regs = ugeth->uec_mii_regs;
  97
  98         /* Setting up the MII Mangement Address Register */
  99         tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
 100         out_be32 (&ug_regs->miimadd, tmp_reg);
 101
 102         /* clear MII management command cycle */
 103         out_be32 (&ug_regs->miimcom, 0);
 104         sync();
 105
 106         /* Perform an MII management read cycle */
 107         out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
 108
 109         /* Wait till MII management write is complete */
 110         while ((in_be32 (&ug_regs->miimind)) &
 111                (MIIMIND_NOT_VALID | MIIMIND_BUSY));
 112
 113         /* Read MII management status  */
 114         value = (u16) in_be32 (&ug_regs->miimstat);
 115         if (value == 0xffff)
 116                 ugphy_vdbg
 117                         ("read wrong value : mii_id %d,mii_reg %d, base %08x",
 118                          mii_id, mii_reg, (u32) & (ug_regs->miimcfg));
 119
 120         return (value);
 121 }
 122
 123 void mii_clear_phy_interrupt (struct uec_mii_info *mii_info)
 124 {
 125         if (mii_info->phyinfo->ack_interrupt)
 126                 mii_info->phyinfo->ack_interrupt (mii_info);
 127 }
 128
 129 void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
 130                                   u32 interrupts)
 131 {
 132         mii_info->interrupts = interrupts;
 133         if (mii_info->phyinfo->config_intr)
 134                 mii_info->phyinfo->config_intr (mii_info);
 135 }
 136
 137 /* Writes MII_ADVERTISE with the appropriate values, after
 138  * sanitizing advertise to make sure only supported features
 139  * are advertised
 140  */
 141 static void config_genmii_advert (struct uec_mii_info *mii_info)
 142 {
 143         u32 advertise;
 144         u16 adv;
 145
 146         /* Only allow advertising what this PHY supports */
 147         mii_info->advertising &= mii_info->phyinfo->features;
 148         advertise = mii_info->advertising;
 149
 150         /* Setup standard advertisement */
 151         adv = phy_read (mii_info, PHY_ANAR);
 152         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 153         if (advertise & ADVERTISED_10baseT_Half)
 154                 adv |= ADVERTISE_10HALF;
 155         if (advertise & ADVERTISED_10baseT_Full)
 156                 adv |= ADVERTISE_10FULL;
 157         if (advertise & ADVERTISED_100baseT_Half)
 158                 adv |= ADVERTISE_100HALF;
 159         if (advertise & ADVERTISED_100baseT_Full)
 160                 adv |= ADVERTISE_100FULL;
 161         phy_write (mii_info, PHY_ANAR, adv);
 162 }
 163
 164 static void genmii_setup_forced (struct uec_mii_info *mii_info)
 165 {
 166         u16 ctrl;
 167         u32 features = mii_info->phyinfo->features;
 168
 169         ctrl = phy_read (mii_info, PHY_BMCR);
 170
 171         ctrl &= ~(PHY_BMCR_DPLX | PHY_BMCR_100_MBPS |
 172                   PHY_BMCR_1000_MBPS | PHY_BMCR_AUTON);
 173         ctrl |= PHY_BMCR_RESET;
 174
 175         switch (mii_info->speed) {
 176         case SPEED_1000:
 177                 if (features & (SUPPORTED_1000baseT_Half
 178                                 | SUPPORTED_1000baseT_Full)) {
 179                         ctrl |= PHY_BMCR_1000_MBPS;
 180                         break;
 181                 }
 182                 mii_info->speed = SPEED_100;
 183         case SPEED_100:
 184                 if (features & (SUPPORTED_100baseT_Half
 185                                 | SUPPORTED_100baseT_Full)) {
 186                         ctrl |= PHY_BMCR_100_MBPS;
 187                         break;
 188                 }
 189                 mii_info->speed = SPEED_10;
 190         case SPEED_10:
 191                 if (features & (SUPPORTED_10baseT_Half
 192                                 | SUPPORTED_10baseT_Full))
 193                         break;
 194         default:                /* Unsupported speed! */
 195                 ugphy_err ("%s: Bad speed!", mii_info->dev->name);
 196                 break;
 197         }
 198
 199         phy_write (mii_info, PHY_BMCR, ctrl);
 200 }
 201
 202 /* Enable and Restart Autonegotiation */
 203 static void genmii_restart_aneg (struct uec_mii_info *mii_info)
 204 {
 205         u16 ctl;
 206
 207         ctl = phy_read (mii_info, PHY_BMCR);
 208         ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 209         phy_write (mii_info, PHY_BMCR, ctl);
 210 }
 211
 212 static int gbit_config_aneg (struct uec_mii_info *mii_info)
 213 {
 214         u16 adv;
 215         u32 advertise;
 216
 217         if (mii_info->autoneg) {
 218                 /* Configure the ADVERTISE register */
 219                 config_genmii_advert (mii_info);
 220                 advertise = mii_info->advertising;
 221
 222                 adv = phy_read (mii_info, MII_1000BASETCONTROL);
 223                 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
 224                          MII_1000BASETCONTROL_HALFDUPLEXCAP);
 225                 if (advertise & SUPPORTED_1000baseT_Half)
 226                         adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
 227                 if (advertise & SUPPORTED_1000baseT_Full)
 228                         adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
 229                 phy_write (mii_info, MII_1000BASETCONTROL, adv);
 230
 231                 /* Start/Restart aneg */
 232                 genmii_restart_aneg (mii_info);
 233         } else
 234                 genmii_setup_forced (mii_info);
 235
 236         return 0;
 237 }
 238
 239 static int marvell_config_aneg (struct uec_mii_info *mii_info)
 240 {
 241         /* The Marvell PHY has an errata which requires
 242          * that certain registers get written in order
 243          * to restart autonegotiation */
 244         phy_write (mii_info, PHY_BMCR, PHY_BMCR_RESET);
 245
 246         phy_write (mii_info, 0x1d, 0x1f);
 247         phy_write (mii_info, 0x1e, 0x200c);
 248         phy_write (mii_info, 0x1d, 0x5);
 249         phy_write (mii_info, 0x1e, 0);
 250         phy_write (mii_info, 0x1e, 0x100);
 251
 252         gbit_config_aneg (mii_info);
 253
 254         return 0;
 255 }
 256
 257 static int genmii_config_aneg (struct uec_mii_info *mii_info)
 258 {
 259         if (mii_info->autoneg) {
 260                 config_genmii_advert (mii_info);
 261                 genmii_restart_aneg (mii_info);
 262         } else
 263                 genmii_setup_forced (mii_info);
 264
 265         return 0;
 266 }
 267
 268 static int genmii_update_link (struct uec_mii_info *mii_info)
 269 {
 270         u16 status;
 271
 272         /* Status is read once to clear old link state */
 273         phy_read (mii_info, PHY_BMSR);
 274
 275         /*
 276          * Wait if the link is up, and autonegotiation is in progress
 277          * (ie - we're capable and it's not done)
 278          */
 279         status = phy_read(mii_info, PHY_BMSR);
 280         if ((status & PHY_BMSR_LS) && (status & PHY_BMSR_AUTN_ABLE)
 281             && !(status & PHY_BMSR_AUTN_COMP)) {
 282                 int i = 0;
 283
 284                 while (!(status & PHY_BMSR_AUTN_COMP)) {
 285                         /*
 286                          * Timeout reached ?
 287                          */
 288                         if (i > UGETH_AN_TIMEOUT) {
 289                                 mii_info->link = 0;
 290                                 return 0;
 291                         }
 292
 293                         i++;
 294                         udelay(1000);   /* 1 ms */
 295                         status = phy_read(mii_info, PHY_BMSR);
 296                 }
 297                 mii_info->link = 1;
 298                 udelay(500000); /* another 500 ms (results in faster booting) */
 299         } else {
 300                 if (status & PHY_BMSR_LS)
 301                         mii_info->link = 1;
 302                 else
 303                         mii_info->link = 0;
 304         }
 305
 306         return 0;
 307 }
 308
 309 static int genmii_read_status (struct uec_mii_info *mii_info)
 310 {
 311         u16 status;
 312         int err;
 313
 314         /* Update the link, but return if there
 315          * was an error */
 316         err = genmii_update_link (mii_info);
 317         if (err)
 318                 return err;
 319
 320         if (mii_info->autoneg) {
 321                 status = phy_read(mii_info, MII_1000BASETSTATUS);
 322
 323                 if (status & (LPA_1000FULL | LPA_1000HALF)) {
 324                         mii_info->speed = SPEED_1000;
 325                         if (status & LPA_1000FULL)
 326                                 mii_info->duplex = DUPLEX_FULL;
 327                         else
 328                                 mii_info->duplex = DUPLEX_HALF;
 329                 } else {
 330                         status = phy_read(mii_info, PHY_ANLPAR);
 331
 332                         if (status & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
 333                                 mii_info->duplex = DUPLEX_FULL;
 334                         else
 335                                 mii_info->duplex = DUPLEX_HALF;
 336                         if (status & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX))
 337                                 mii_info->speed = SPEED_100;
 338                         else
 339                                 mii_info->speed = SPEED_10;
 340                 }
 341                 mii_info->pause = 0;
 342         }
 343         /* On non-aneg, we assume what we put in BMCR is the speed,
 344          * though magic-aneg shouldn't prevent this case from occurring
 345          */
 346
 347         return 0;
 348 }
 349
 350 static int bcm_init(struct uec_mii_info *mii_info)
 351 {
 352         struct eth_device *edev = mii_info->dev;
 353         uec_private_t *uec = edev->priv;
 354
 355         gbit_config_aneg(mii_info);
 356
 357         if (uec->uec_info->enet_interface == ENET_1000_RGMII_RXID) {
 358                 u16 val;
 359                 int cnt = 50;
 360
 361                 /* Wait for aneg to complete. */
 362                 do
 363                         val = phy_read(mii_info, PHY_BMSR);
 364                 while (--cnt && !(val & PHY_BMSR_AUTN_COMP));
 365
 366                 /* Set RDX clk delay. */
 367                 phy_write(mii_info, 0x18, 0x7 | (7 << 12));
 368
 369                 val = phy_read(mii_info, 0x18);
 370                 /* Set RDX-RXC skew. */
 371                 val |= (1 << 8);
 372                 val |= (7 | (7 << 12));
 373                 /* Write bits 14:0. */
 374                 val |= (1 << 15);
 375                 phy_write(mii_info, 0x18, val);
 376         }
 377
 378          return 0;
 379 }
 380
 381 static int marvell_read_status (struct uec_mii_info *mii_info)
 382 {
 383         u16 status;
 384         int err;
 385
 386         /* Update the link, but return if there
 387          * was an error */
 388         err = genmii_update_link (mii_info);
 389         if (err)
 390                 return err;
 391
 392         /* If the link is up, read the speed and duplex */
 393         /* If we aren't autonegotiating, assume speeds
 394          * are as set */
 395         if (mii_info->autoneg && mii_info->link) {
 396                 int speed;
 397
 398                 status = phy_read (mii_info, MII_M1011_PHY_SPEC_STATUS);
 399
 400                 /* Get the duplexity */
 401                 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
 402                         mii_info->duplex = DUPLEX_FULL;
 403                 else
 404                         mii_info->duplex = DUPLEX_HALF;
 405
 406                 /* Get the speed */
 407                 speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
 408                 switch (speed) {
 409                 case MII_M1011_PHY_SPEC_STATUS_1000:
 410                         mii_info->speed = SPEED_1000;
 411                         break;
 412                 case MII_M1011_PHY_SPEC_STATUS_100:
 413                         mii_info->speed = SPEED_100;
 414                         break;
 415                 default:
 416                         mii_info->speed = SPEED_10;
 417                         break;
 418                 }
 419                 mii_info->pause = 0;
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int marvell_ack_interrupt (struct uec_mii_info *mii_info)
 426 {
 427         /* Clear the interrupts by reading the reg */
 428         phy_read (mii_info, MII_M1011_IEVENT);
 429
 430         return 0;
 431 }
 432
 433 static int marvell_config_intr (struct uec_mii_info *mii_info)
 434 {
 435         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 436                 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
 437         else
 438                 phy_write (mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
 439
 440         return 0;
 441 }
 442
 443 static int dm9161_init (struct uec_mii_info *mii_info)
 444 {
 445         /* Reset the PHY */
 446         phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) |
 447                    PHY_BMCR_RESET);
 448         /* PHY and MAC connect */
 449         phy_write (mii_info, PHY_BMCR, phy_read (mii_info, PHY_BMCR) &
 450                    ~PHY_BMCR_ISO);
 451
 452         phy_write (mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
 453
 454         config_genmii_advert (mii_info);
 455         /* Start/restart aneg */
 456         genmii_config_aneg (mii_info);
 457
 458         return 0;
 459 }
 460
 461 static int dm9161_config_aneg (struct uec_mii_info *mii_info)
 462 {
 463         return 0;
 464 }
 465
 466 static int dm9161_read_status (struct uec_mii_info *mii_info)
 467 {
 468         u16 status;
 469         int err;
 470
 471         /* Update the link, but return if there was an error */
 472         err = genmii_update_link (mii_info);
 473         if (err)
 474                 return err;
 475         /* If the link is up, read the speed and duplex
 476            If we aren't autonegotiating assume speeds are as set */
 477         if (mii_info->autoneg && mii_info->link) {
 478                 status = phy_read (mii_info, MII_DM9161_SCSR);
 479                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
 480                         mii_info->speed = SPEED_100;
 481                 else
 482                         mii_info->speed = SPEED_10;
 483
 484                 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
 485                         mii_info->duplex = DUPLEX_FULL;
 486                 else
 487                         mii_info->duplex = DUPLEX_HALF;
 488         }
 489
 490         return 0;
 491 }
 492
 493 static int dm9161_ack_interrupt (struct uec_mii_info *mii_info)
 494 {
 495         /* Clear the interrupt by reading the reg */
 496         phy_read (mii_info, MII_DM9161_INTR);
 497
 498         return 0;
 499 }
 500
 501 static int dm9161_config_intr (struct uec_mii_info *mii_info)
 502 {
 503         if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
 504                 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
 505         else
 506                 phy_write (mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
 507
 508         return 0;
 509 }
 510
 511 static void dm9161_close (struct uec_mii_info *mii_info)
 512 {
 513 }
 514
 515 static struct phy_info phy_info_dm9161 = {
 516         .phy_id = 0x0181b880,
 517         .phy_id_mask = 0x0ffffff0,
 518         .name = "Davicom DM9161E",
 519         .init = dm9161_init,
 520         .config_aneg = dm9161_config_aneg,
 521         .read_status = dm9161_read_status,
 522         .close = dm9161_close,
 523 };
 524
 525 static struct phy_info phy_info_dm9161a = {
 526         .phy_id = 0x0181b8a0,
 527         .phy_id_mask = 0x0ffffff0,
 528         .name = "Davicom DM9161A",
 529         .features = MII_BASIC_FEATURES,
 530         .init = dm9161_init,
 531         .config_aneg = dm9161_config_aneg,
 532         .read_status = dm9161_read_status,
 533         .ack_interrupt = dm9161_ack_interrupt,
 534         .config_intr = dm9161_config_intr,
 535         .close = dm9161_close,
 536 };
 537
 538 static struct phy_info phy_info_marvell = {
 539         .phy_id = 0x01410c00,
 540         .phy_id_mask = 0xffffff00,
 541         .name = "Marvell 88E11x1",
 542         .features = MII_GBIT_FEATURES,
 543         .config_aneg = &marvell_config_aneg,
 544         .read_status = &marvell_read_status,
 545         .ack_interrupt = &marvell_ack_interrupt,
 546         .config_intr = &marvell_config_intr,
 547 };
 548
 549 static struct phy_info phy_info_bcm5481 = {
 550         .phy_id = 0x0143bca0,
 551         .phy_id_mask = 0xffffff0,
 552         .name = "Broadcom 5481",
 553         .features = MII_GBIT_FEATURES,
 554         .read_status = genmii_read_status,
 555         .init = bcm_init,
 556 };
 557
 558 static struct phy_info phy_info_genmii = {
 559         .phy_id = 0x00000000,
 560         .phy_id_mask = 0x00000000,
 561         .name = "Generic MII",
 562         .features = MII_BASIC_FEATURES,
 563         .config_aneg = genmii_config_aneg,
 564         .read_status = genmii_read_status,
 565 };
 566
 567 static struct phy_info *phy_info[] = {
 568         &phy_info_dm9161,
 569         &phy_info_dm9161a,
 570         &phy_info_marvell,
 571         &phy_info_bcm5481,
 572         &phy_info_genmii,
 573         NULL
 574 };
 575
 576 u16 phy_read (struct uec_mii_info *mii_info, u16 regnum)
 577 {
 578         return mii_info->mdio_read (mii_info->dev, mii_info->mii_id, regnum);
 579 }
 580
 581 void phy_write (struct uec_mii_info *mii_info, u16 regnum, u16 val)
 582 {
 583         mii_info->mdio_write (mii_info->dev, mii_info->mii_id, regnum, val);
 584 }
 585
 586 /* Use the PHY ID registers to determine what type of PHY is attached
 587  * to device dev.  return a struct phy_info structure describing that PHY
 588  */
 589 struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
 590 {
 591         u16 phy_reg;
 592         u32 phy_ID;
 593         int i;
 594         struct phy_info *theInfo = NULL;
 595
 596         /* Grab the bits from PHYIR1, and put them in the upper half */
 597         phy_reg = phy_read (mii_info, PHY_PHYIDR1);
 598         phy_ID = (phy_reg & 0xffff) << 16;
 599
 600         /* Grab the bits from PHYIR2, and put them in the lower half */
 601         phy_reg = phy_read (mii_info, PHY_PHYIDR2);
 602         phy_ID |= (phy_reg & 0xffff);
 603
 604         /* loop through all the known PHY types, and find one that */
 605         /* matches the ID we read from the PHY. */
 606         for (i = 0; phy_info[i]; i++)
 607                 if (phy_info[i]->phy_id ==
 608                     (phy_ID & phy_info[i]->phy_id_mask)) {
 609                         theInfo = phy_info[i];
 610                         break;
 611                 }
 612
 613         /* This shouldn't happen, as we have generic PHY support */
 614         if (theInfo == NULL) {
 615                 ugphy_info ("UEC: PHY id %x is not supported!", phy_ID);
 616                 return NULL;
 617         } else {
 618                 ugphy_info ("UEC: PHY is %s (%x)", theInfo->name, phy_ID);
 619         }
 620
 621         return theInfo;
 622 }
 623
 624 void marvell_phy_interface_mode (struct eth_device *dev,
 625                                  enet_interface_e mode)
 626 {
 627         uec_private_t *uec = (uec_private_t *) dev->priv;
 628         struct uec_mii_info *mii_info;
 629         u16 status;
 630
 631         if (!uec->mii_info) {
 632                 printf ("%s: the PHY not initialized\n", __FUNCTION__);
 633                 return;
 634         }
 635         mii_info = uec->mii_info;
 636
 637         if (mode == ENET_100_RGMII) {
 638                 phy_write (mii_info, 0x00, 0x9140);
 639                 phy_write (mii_info, 0x1d, 0x001f);
 640                 phy_write (mii_info, 0x1e, 0x200c);
 641                 phy_write (mii_info, 0x1d, 0x0005);
 642                 phy_write (mii_info, 0x1e, 0x0000);
 643                 phy_write (mii_info, 0x1e, 0x0100);
 644                 phy_write (mii_info, 0x09, 0x0e00);
 645                 phy_write (mii_info, 0x04, 0x01e1);
 646                 phy_write (mii_info, 0x00, 0x9140);
 647                 phy_write (mii_info, 0x00, 0x1000);
 648                 udelay (100000);
 649                 phy_write (mii_info, 0x00, 0x2900);
 650                 phy_write (mii_info, 0x14, 0x0cd2);
 651                 phy_write (mii_info, 0x00, 0xa100);
 652                 phy_write (mii_info, 0x09, 0x0000);
 653                 phy_write (mii_info, 0x1b, 0x800b);
 654                 phy_write (mii_info, 0x04, 0x05e1);
 655                 phy_write (mii_info, 0x00, 0xa100);
 656                 phy_write (mii_info, 0x00, 0x2100);
 657                 udelay (1000000);
 658         } else if (mode == ENET_10_RGMII) {
 659                 phy_write (mii_info, 0x14, 0x8e40);
 660                 phy_write (mii_info, 0x1b, 0x800b);
 661                 phy_write (mii_info, 0x14, 0x0c82);
 662                 phy_write (mii_info, 0x00, 0x8100);
 663                 udelay (1000000);
 664         }
 665
 666         /* handle 88e1111 rev.B2 erratum 5.6 */
 667         if (mii_info->autoneg) {
 668                 status = phy_read (mii_info, PHY_BMCR);
 669                 phy_write (mii_info, PHY_BMCR, status | PHY_BMCR_AUTON);
 670         }
 671         /* now the B2 will correctly report autoneg completion status */
 672 }
 673
 674 void change_phy_interface_mode (struct eth_device *dev, enet_interface_e mode)
 675 {
 676 #ifdef CONFIG_PHY_MODE_NEED_CHANGE
 677         marvell_phy_interface_mode (dev, mode);
 678 #endif
 679 }
 680 #endif /* CONFIG_QE */