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[thirdparty/u-boot.git] / drivers / ram / stm32mp1 / stm32mp1_tuning.c
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2019, STMicroelectronics - All Rights Reserved
4 */
5 #include <common.h>
6 #include <console.h>
7 #include <clk.h>
8 #include <ram.h>
9 #include <rand.h>
10 #include <reset.h>
11 #include <asm/io.h>
12 #include <linux/bitops.h>
13 #include <linux/iopoll.h>
14
15 #include "stm32mp1_ddr_regs.h"
16 #include "stm32mp1_ddr.h"
17 #include "stm32mp1_tests.h"
18
19 #define MAX_DQS_PHASE_IDX _144deg
20 #define MAX_DQS_UNIT_IDX 7
21 #define MAX_GSL_IDX 5
22 #define MAX_GPS_IDX 3
23
24 /* Number of bytes used in this SW. ( min 1--> max 4). */
25 #define NUM_BYTES 4
26
27 enum dqs_phase_enum {
28 _36deg = 0,
29 _54deg = 1,
30 _72deg = 2,
31 _90deg = 3,
32 _108deg = 4,
33 _126deg = 5,
34 _144deg = 6
35 };
36
37 /* BIST Result struct */
38 struct BIST_result {
39 /* Overall test result:
40 * 0 Fail (any bit failed) ,
41 * 1 Success (All bits success)
42 */
43 bool test_result;
44 /* 1: true, all fail / 0: False, not all bits fail */
45 bool all_bits_fail;
46 bool bit_i_test_result[8]; /* 0 fail / 1 success */
47 };
48
49 /* a struct that defines tuning parameters of a byte. */
50 struct tuning_position {
51 u8 phase; /* DQS phase */
52 u8 unit; /* DQS unit delay */
53 u32 bits_delay; /* Bits deskew in this byte */
54 };
55
56 /* 36deg, 54deg, 72deg, 90deg, 108deg, 126deg, 144deg */
57 const u8 dx_dll_phase[7] = {3, 2, 1, 0, 14, 13, 12};
58
59 static u8 BIST_error_max = 1;
60 static u32 BIST_seed = 0x1234ABCD;
61
62 static u8 get_nb_bytes(struct stm32mp1_ddrctl *ctl)
63 {
64 u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK;
65 u8 nb_bytes = NUM_BYTES;
66
67 switch (data_bus) {
68 case DDRCTRL_MSTR_DATA_BUS_WIDTH_HALF:
69 nb_bytes /= 2;
70 break;
71 case DDRCTRL_MSTR_DATA_BUS_WIDTH_QUARTER:
72 nb_bytes /= 4;
73 break;
74 default:
75 break;
76 }
77
78 return nb_bytes;
79 }
80
81 static u8 get_nb_bank(struct stm32mp1_ddrctl *ctl)
82 {
83 /* Count bank address bits */
84 u8 bits = 0;
85 u32 reg, val;
86
87 reg = readl(&ctl->addrmap1);
88 /* addrmap1.addrmap_bank_b1 */
89 val = (reg & GENMASK(5, 0)) >> 0;
90 if (val <= 31)
91 bits++;
92 /* addrmap1.addrmap_bank_b2 */
93 val = (reg & GENMASK(13, 8)) >> 8;
94 if (val <= 31)
95 bits++;
96 /* addrmap1.addrmap_bank_b3 */
97 val = (reg & GENMASK(21, 16)) >> 16;
98 if (val <= 31)
99 bits++;
100
101 return bits;
102 }
103
104 static u8 get_nb_col(struct stm32mp1_ddrctl *ctl)
105 {
106 u8 bits;
107 u32 reg, val;
108
109 /* Count column address bits, start at 2 for b0 and b1 (fixed) */
110 bits = 2;
111
112 reg = readl(&ctl->addrmap2);
113 /* addrmap2.addrmap_col_b2 */
114 val = (reg & GENMASK(3, 0)) >> 0;
115 if (val <= 7)
116 bits++;
117 /* addrmap2.addrmap_col_b3 */
118 val = (reg & GENMASK(11, 8)) >> 8;
119 if (val <= 7)
120 bits++;
121 /* addrmap2.addrmap_col_b4 */
122 val = (reg & GENMASK(19, 16)) >> 16;
123 if (val <= 7)
124 bits++;
125 /* addrmap2.addrmap_col_b5 */
126 val = (reg & GENMASK(27, 24)) >> 24;
127 if (val <= 7)
128 bits++;
129
130 reg = readl(&ctl->addrmap3);
131 /* addrmap3.addrmap_col_b6 */
132 val = (reg & GENMASK(3, 0)) >> 0;
133 if (val <= 7)
134 bits++;
135 /* addrmap3.addrmap_col_b7 */
136 val = (reg & GENMASK(11, 8)) >> 8;
137 if (val <= 7)
138 bits++;
139 /* addrmap3.addrmap_col_b8 */
140 val = (reg & GENMASK(19, 16)) >> 16;
141 if (val <= 7)
142 bits++;
143 /* addrmap3.addrmap_col_b9 */
144 val = (reg & GENMASK(27, 24)) >> 24;
145 if (val <= 7)
146 bits++;
147
148 reg = readl(&ctl->addrmap4);
149 /* addrmap4.addrmap_col_b10 */
150 val = (reg & GENMASK(3, 0)) >> 0;
151 if (val <= 7)
152 bits++;
153 /* addrmap4.addrmap_col_b11 */
154 val = (reg & GENMASK(11, 8)) >> 8;
155 if (val <= 7)
156 bits++;
157
158 return bits;
159 }
160
161 static u8 get_nb_row(struct stm32mp1_ddrctl *ctl)
162 {
163 /* Count row address bits */
164 u8 bits = 0;
165 u32 reg, val;
166
167 reg = readl(&ctl->addrmap5);
168 /* addrmap5.addrmap_row_b0 */
169 val = (reg & GENMASK(3, 0)) >> 0;
170 if (val <= 11)
171 bits++;
172 /* addrmap5.addrmap_row_b1 */
173 val = (reg & GENMASK(11, 8)) >> 8;
174 if (val <= 11)
175 bits++;
176 /* addrmap5.addrmap_row_b2_10 */
177 val = (reg & GENMASK(19, 16)) >> 16;
178 if (val <= 11)
179 bits += 9;
180 else
181 printf("warning: addrmap5.addrmap_row_b2_10 not supported\n");
182 /* addrmap5.addrmap_row_b11 */
183 val = (reg & GENMASK(27, 24)) >> 24;
184 if (val <= 11)
185 bits++;
186
187 reg = readl(&ctl->addrmap6);
188 /* addrmap6.addrmap_row_b12 */
189 val = (reg & GENMASK(3, 0)) >> 0;
190 if (val <= 7)
191 bits++;
192 /* addrmap6.addrmap_row_b13 */
193 val = (reg & GENMASK(11, 8)) >> 8;
194 if (val <= 7)
195 bits++;
196 /* addrmap6.addrmap_row_b14 */
197 val = (reg & GENMASK(19, 16)) >> 16;
198 if (val <= 7)
199 bits++;
200 /* addrmap6.addrmap_row_b15 */
201 val = (reg & GENMASK(27, 24)) >> 24;
202 if (val <= 7)
203 bits++;
204
205 return bits;
206 }
207
208 static void itm_soft_reset(struct stm32mp1_ddrphy *phy)
209 {
210 stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
211 }
212
213 /* Read DQ unit delay register and provides the retrieved value for DQS
214 * We are assuming that we have the same delay when clocking
215 * by DQS and when clocking by DQSN
216 */
217 static u8 DQ_unit_index(struct stm32mp1_ddrphy *phy, u8 byte, u8 bit)
218 {
219 u32 index;
220 u32 addr = DXNDQTR(phy, byte);
221
222 /* We are assuming that we have the same delay when clocking by DQS
223 * and when clocking by DQSN : use only the low bits
224 */
225 index = (readl(addr) >> DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit))
226 & DDRPHYC_DXNDQTR_DQDLY_LOW_MASK;
227
228 pr_debug("%s: [%x]: %x => DQ unit index = %x\n",
229 __func__, addr, readl(addr), index);
230
231 return index;
232 }
233
234 /* Sets the DQS phase delay for a byte lane.
235 *phase delay is specified by giving the index of the desired delay
236 * in the dx_dll_phase array.
237 */
238 static void DQS_phase_delay(struct stm32mp1_ddrphy *phy, u8 byte, u8 phase_idx)
239 {
240 u8 sdphase_val = 0;
241
242 /* Write DXNDLLCR.SDPHASE = dx_dll_phase(phase_index); */
243 sdphase_val = dx_dll_phase[phase_idx];
244 clrsetbits_le32(DXNDLLCR(phy, byte),
245 DDRPHYC_DXNDLLCR_SDPHASE_MASK,
246 sdphase_val << DDRPHYC_DXNDLLCR_SDPHASE_SHIFT);
247 }
248
249 /* Sets the DQS unit delay for a byte lane.
250 * unit delay is specified by giving the index of the desired delay
251 * for dgsdly and dqsndly (same value).
252 */
253 static void DQS_unit_delay(struct stm32mp1_ddrphy *phy,
254 u8 byte, u8 unit_dly_idx)
255 {
256 /* Write the same value in DXNDQSTR.DQSDLY and DXNDQSTR.DQSNDLY */
257 clrsetbits_le32(DXNDQSTR(phy, byte),
258 DDRPHYC_DXNDQSTR_DQSDLY_MASK |
259 DDRPHYC_DXNDQSTR_DQSNDLY_MASK,
260 (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSDLY_SHIFT) |
261 (unit_dly_idx << DDRPHYC_DXNDQSTR_DQSNDLY_SHIFT));
262
263 /* After changing this value, an ITM soft reset (PIR.ITMSRST=1,
264 * plus PIR.INIT=1) must be issued.
265 */
266 stm32mp1_ddrphy_init(phy, DDRPHYC_PIR_ITMSRST);
267 }
268
269 /* Sets the DQ unit delay for a bit line in particular byte lane.
270 * unit delay is specified by giving the desired delay
271 */
272 static void set_DQ_unit_delay(struct stm32mp1_ddrphy *phy,
273 u8 byte, u8 bit,
274 u8 dq_delay_index)
275 {
276 u8 dq_bit_delay_val = dq_delay_index | (dq_delay_index << 2);
277
278 /* same value on delay for clock DQ an DQS_b */
279 clrsetbits_le32(DXNDQTR(phy, byte),
280 DDRPHYC_DXNDQTR_DQDLY_MASK
281 << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit),
282 dq_bit_delay_val << DDRPHYC_DXNDQTR_DQDLY_SHIFT(bit));
283 }
284
285 static void set_r0dgsl_delay(struct stm32mp1_ddrphy *phy,
286 u8 byte, u8 r0dgsl_idx)
287 {
288 clrsetbits_le32(DXNDQSTR(phy, byte),
289 DDRPHYC_DXNDQSTR_R0DGSL_MASK,
290 r0dgsl_idx << DDRPHYC_DXNDQSTR_R0DGSL_SHIFT);
291 }
292
293 static void set_r0dgps_delay(struct stm32mp1_ddrphy *phy,
294 u8 byte, u8 r0dgps_idx)
295 {
296 clrsetbits_le32(DXNDQSTR(phy, byte),
297 DDRPHYC_DXNDQSTR_R0DGPS_MASK,
298 r0dgps_idx << DDRPHYC_DXNDQSTR_R0DGPS_SHIFT);
299 }
300
301 /* Basic BIST configuration for data lane tests. */
302 static void config_BIST(struct stm32mp1_ddrctl *ctl,
303 struct stm32mp1_ddrphy *phy)
304 {
305 u8 nb_bank = get_nb_bank(ctl);
306 u8 nb_row = get_nb_row(ctl);
307 u8 nb_col = get_nb_col(ctl);
308
309 /* Selects the SDRAM bank address to be used during BIST. */
310 u32 bbank = 0;
311 /* Selects the SDRAM row address to be used during BIST. */
312 u32 brow = 0;
313 /* Selects the SDRAM column address to be used during BIST. */
314 u32 bcol = 0;
315 /* Selects the value by which the SDRAM address is incremented
316 * for each write/read access.
317 */
318 u32 bainc = 0x00000008;
319 /* Specifies the maximum SDRAM rank to be used during BIST.
320 * The default value is set to maximum ranks minus 1.
321 * must be 0 with single rank
322 */
323 u32 bmrank = 0;
324 /* Selects the SDRAM rank to be used during BIST.
325 * must be 0 with single rank
326 */
327 u32 brank = 0;
328
329 /* Specifies the maximum SDRAM bank address to be used during
330 * BIST before the address & increments to the next rank.
331 */
332 u32 bmbank = (1 << nb_bank) - 1;
333 /* Specifies the maximum SDRAM row address to be used during
334 * BIST before the address & increments to the next bank.
335 */
336 u32 bmrow = (1 << nb_row) - 1;
337 /* Specifies the maximum SDRAM column address to be used during
338 * BIST before the address & increments to the next row.
339 */
340 u32 bmcol = (1 << nb_col) - 1;
341
342 u32 bmode_conf = 0x00000001; /* DRam mode */
343 u32 bdxen_conf = 0x00000001; /* BIST on Data byte */
344 u32 bdpat_conf = 0x00000002; /* Select LFSR pattern */
345
346 /*Setup BIST for DRAM mode, and LFSR-random data pattern.*/
347 /*Write BISTRR.BMODE = 1?b1;*/
348 /*Write BISTRR.BDXEN = 1?b1;*/
349 /*Write BISTRR.BDPAT = 2?b10;*/
350
351 /* reset BIST */
352 writel(0x3, &phy->bistrr);
353
354 writel((bmode_conf << 3) | (bdxen_conf << 14) | (bdpat_conf << 17),
355 &phy->bistrr);
356
357 /*Setup BIST Word Count*/
358 /*Write BISTWCR.BWCNT = 16?b0008;*/
359 writel(0x00000200, &phy->bistwcr); /* A multiple of BL/2 */
360
361 writel(bcol | (brow << 12) | (bbank << 28), &phy->bistar0);
362 writel(brank | (bmrank << 2) | (bainc << 4), &phy->bistar1);
363 writel(bmcol | (bmrow << 12) | (bmbank << 28), &phy->bistar2);
364 }
365
366 /* Select the Byte lane to be tested by BIST. */
367 static void BIST_datx8_sel(struct stm32mp1_ddrphy *phy, u8 datx8)
368 {
369 clrsetbits_le32(&phy->bistrr,
370 DDRPHYC_BISTRR_BDXSEL_MASK,
371 datx8 << DDRPHYC_BISTRR_BDXSEL_SHIFT);
372
373 /*(For example, selecting Byte Lane 3, BISTRR.BDXSEL = 4?b0011)*/
374 /* Write BISTRR.BDXSEL = datx8; */
375 }
376
377 /* Perform BIST Write_Read test on a byte lane and return test result. */
378 static void BIST_test(struct stm32mp1_ddrphy *phy, u8 byte,
379 struct BIST_result *bist)
380 {
381 bool result = true; /* BIST_SUCCESS */
382 u32 cnt = 0;
383 u32 error = 0;
384 u32 val;
385 int ret;
386
387 bist->test_result = true;
388
389 run:
390 itm_soft_reset(phy);
391
392 /*Perform BIST Reset*/
393 /* Write BISTRR.BINST = 3?b011; */
394 clrsetbits_le32(&phy->bistrr,
395 0x00000007,
396 0x00000003);
397
398 /*Re-seed LFSR*/
399 /* Write BISTLSR.SEED = 32'h1234ABCD; */
400 if (BIST_seed)
401 writel(BIST_seed, &phy->bistlsr);
402 else
403 writel(rand(), &phy->bistlsr);
404
405 /* some delay to reset BIST */
406 udelay(10);
407
408 /*Perform BIST Run*/
409 clrsetbits_le32(&phy->bistrr,
410 0x00000007,
411 0x00000001);
412 /* Write BISTRR.BINST = 3?b001; */
413
414 /* poll on BISTGSR.BDONE and wait max 1000 us */
415 ret = readl_poll_timeout(&phy->bistgsr, val,
416 val & DDRPHYC_BISTGSR_BDDONE, 1000);
417
418 if (ret < 0) {
419 printf("warning: BIST timeout\n");
420 result = false; /* BIST_FAIL; */
421 /*Perform BIST Stop */
422 clrsetbits_le32(&phy->bistrr, 0x00000007, 0x00000002);
423 } else {
424 /*Check if received correct number of words*/
425 /* if (Read BISTWCSR.DXWCNT = Read BISTWCR.BWCNT) */
426 if (((readl(&phy->bistwcsr)) >> DDRPHYC_BISTWCSR_DXWCNT_SHIFT)
427 == readl(&phy->bistwcr)) {
428 /*Determine if there is a data comparison error*/
429 /* if (Read BISTGSR.BDXERR = 1?b0) */
430 if (readl(&phy->bistgsr) & DDRPHYC_BISTGSR_BDXERR)
431 result = false; /* BIST_FAIL; */
432 else
433 result = true; /* BIST_SUCCESS; */
434 } else {
435 result = false; /* BIST_FAIL; */
436 }
437 }
438
439 /* loop while success */
440 cnt++;
441 if (result && cnt != 1000)
442 goto run;
443
444 if (!result)
445 error++;
446
447 if (error < BIST_error_max) {
448 if (cnt != 1000)
449 goto run;
450 bist->test_result = true;
451 } else {
452 bist->test_result = false;
453 }
454 }
455
456 /* After running the deskew algo, this function applies the new DQ delays
457 * by reading them from the array "deskew_delay"and writing in PHY registers.
458 * The bits that are not deskewed parfectly (too much skew on them,
459 * or data eye very wide) are marked in the array deskew_non_converge.
460 */
461 static void apply_deskew_results(struct stm32mp1_ddrphy *phy, u8 byte,
462 u8 deskew_delay[NUM_BYTES][8],
463 u8 deskew_non_converge[NUM_BYTES][8])
464 {
465 u8 bit_i;
466 u8 index;
467
468 for (bit_i = 0; bit_i < 8; bit_i++) {
469 set_DQ_unit_delay(phy, byte, bit_i, deskew_delay[byte][bit_i]);
470 index = DQ_unit_index(phy, byte, bit_i);
471 pr_debug("Byte %d ; bit %d : The new DQ delay (%d) index=%d [delta=%d, 3 is the default]",
472 byte, bit_i, deskew_delay[byte][bit_i],
473 index, index - 3);
474 printf("Byte %d, bit %d, DQ delay = %d",
475 byte, bit_i, deskew_delay[byte][bit_i]);
476 if (deskew_non_converge[byte][bit_i] == 1)
477 pr_debug(" - not converged : still more skew");
478 printf("\n");
479 }
480 }
481
482 /* DQ Bit de-skew algorithm.
483 * Deskews data lines as much as possible.
484 * 1. Add delay to DQS line until finding the failure
485 * (normally a hold time violation)
486 * 2. Reduce DQS line by small steps until finding the very first time
487 * we go back to "Pass" condition.
488 * 3. For each DQ line, Reduce DQ delay until finding the very first failure
489 * (normally a hold time fail)
490 * 4. When all bits are at their first failure delay, we can consider them
491 * aligned.
492 * Handle conrer situation (Can't find Pass-fail, or fail-pass transitions
493 * at any step)
494 * TODO Provide a return Status. Improve doc
495 */
496 static enum test_result bit_deskew(struct stm32mp1_ddrctl *ctl,
497 struct stm32mp1_ddrphy *phy, char *string)
498 {
499 /* New DQ delay value (index), set during Deskew algo */
500 u8 deskew_delay[NUM_BYTES][8];
501 /*If there is still skew on a bit, mark this bit. */
502 u8 deskew_non_converge[NUM_BYTES][8];
503 struct BIST_result result;
504 s8 dqs_unit_delay_index = 0;
505 u8 datx8 = 0;
506 u8 bit_i = 0;
507 s8 phase_idx = 0;
508 s8 bit_i_delay_index = 0;
509 u8 success = 0;
510 struct tuning_position last_right_ok;
511 u8 force_stop = 0;
512 u8 fail_found;
513 u8 error = 0;
514 u8 nb_bytes = get_nb_bytes(ctl);
515 /* u8 last_pass_dqs_unit = 0; */
516
517 memset(deskew_delay, 0, sizeof(deskew_delay));
518 memset(deskew_non_converge, 0, sizeof(deskew_non_converge));
519
520 /*Disable DQS Drift Compensation*/
521 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
522 /*Disable all bytes*/
523 /* Disable automatic power down of DLL and IOs when disabling
524 * a byte (To avoid having to add programming and delay
525 * for a DLL re-lock when later re-enabling a disabled Byte Lane)
526 */
527 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
528
529 /* Disable all data bytes */
530 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
531 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
532 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
533 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
534
535 /* Config the BIST block */
536 config_BIST(ctl, phy);
537 pr_debug("BIST Config done.\n");
538
539 /* Train each byte */
540 for (datx8 = 0; datx8 < nb_bytes; datx8++) {
541 if (ctrlc()) {
542 sprintf(string, "interrupted at byte %d/%d, error=%d",
543 datx8 + 1, nb_bytes, error);
544 return TEST_FAILED;
545 }
546 pr_debug("\n======================\n");
547 pr_debug("Start deskew byte %d .\n", datx8);
548 pr_debug("======================\n");
549 /* Enable Byte (DXNGCR, bit DXEN) */
550 setbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
551
552 /* Select the byte lane for comparison of read data */
553 BIST_datx8_sel(phy, datx8);
554
555 /* Set all DQDLYn to maximum value. All bits within the byte
556 * will be delayed with DQSTR = 2 instead of max = 3
557 * to avoid inter bits fail influence
558 */
559 writel(0xAAAAAAAA, DXNDQTR(phy, datx8));
560
561 /* Set the DQS phase delay to 90 DEG (default).
562 * What is defined here is the index of the desired config
563 * in the PHASE array.
564 */
565 phase_idx = _90deg;
566
567 /* Set DQS unit delay to the max value. */
568 dqs_unit_delay_index = MAX_DQS_UNIT_IDX;
569 DQS_unit_delay(phy, datx8, dqs_unit_delay_index);
570 DQS_phase_delay(phy, datx8, phase_idx);
571
572 /* Issue a DLL soft reset */
573 clrbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
574 setbits_le32(DXNDLLCR(phy, datx8), DDRPHYC_DXNDLLCR_DLLSRST);
575
576 /* Test this typical init condition */
577 BIST_test(phy, datx8, &result);
578 success = result.test_result;
579
580 /* If the test pass in this typical condition,
581 * start the algo with it.
582 * Else, look for Pass init condition
583 */
584 if (!success) {
585 pr_debug("Fail at init condtion. Let's look for a good init condition.\n");
586 success = 0; /* init */
587 /* Make sure we start with a PASS condition before
588 * looking for a fail condition.
589 * Find the first PASS PHASE condition
590 */
591
592 /* escape if we find a PASS */
593 pr_debug("increase Phase idx\n");
594 while (!success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
595 DQS_phase_delay(phy, datx8, phase_idx);
596 BIST_test(phy, datx8, &result);
597 success = result.test_result;
598 phase_idx++;
599 }
600 /* if ended with success
601 * ==>> Restore the fist success condition
602 */
603 if (success)
604 phase_idx--; /* because it ended with ++ */
605 }
606 if (ctrlc()) {
607 sprintf(string, "interrupted at byte %d/%d, error=%d",
608 datx8 + 1, nb_bytes, error);
609 return TEST_FAILED;
610 }
611 /* We couldn't find a successful condition, its seems
612 * we have hold violation, lets try reduce DQS_unit Delay
613 */
614 if (!success) {
615 /* We couldn't find a successful condition, its seems
616 * we have hold violation, lets try reduce DQS_unit
617 * Delay
618 */
619 pr_debug("Still fail. Try decrease DQS Unit delay\n");
620
621 phase_idx = 0;
622 dqs_unit_delay_index = 0;
623 DQS_phase_delay(phy, datx8, phase_idx);
624
625 /* escape if we find a PASS */
626 while (!success &&
627 (dqs_unit_delay_index <=
628 MAX_DQS_UNIT_IDX)) {
629 DQS_unit_delay(phy, datx8,
630 dqs_unit_delay_index);
631 BIST_test(phy, datx8, &result);
632 success = result.test_result;
633 dqs_unit_delay_index++;
634 }
635 if (success) {
636 /* Restore the first success condition*/
637 dqs_unit_delay_index--;
638 /* last_pass_dqs_unit = dqs_unit_delay_index;*/
639 DQS_unit_delay(phy, datx8,
640 dqs_unit_delay_index);
641 } else {
642 /* No need to continue,
643 * there is no pass region.
644 */
645 force_stop = 1;
646 }
647 }
648
649 /* There is an initial PASS condition
650 * Look for the first failing condition by PHASE stepping.
651 * This part of the algo can finish without converging.
652 */
653 if (force_stop) {
654 printf("Result: Failed ");
655 printf("[Cannot Deskew lines, ");
656 printf("there is no PASS region]\n");
657 error++;
658 continue;
659 }
660 if (ctrlc()) {
661 sprintf(string, "interrupted at byte %d/%d, error=%d",
662 datx8 + 1, nb_bytes, error);
663 return TEST_FAILED;
664 }
665
666 pr_debug("there is a pass region for phase idx %d\n",
667 phase_idx);
668 pr_debug("Step1: Find the first failing condition\n");
669 /* Look for the first failing condition by PHASE stepping.
670 * This part of the algo can finish without converging.
671 */
672
673 /* escape if we find a fail (hold time violation)
674 * condition at any bit or if out of delay range.
675 */
676 while (success && (phase_idx <= MAX_DQS_PHASE_IDX)) {
677 DQS_phase_delay(phy, datx8, phase_idx);
678 BIST_test(phy, datx8, &result);
679 success = result.test_result;
680 phase_idx++;
681 }
682 if (ctrlc()) {
683 sprintf(string, "interrupted at byte %d/%d, error=%d",
684 datx8 + 1, nb_bytes, error);
685 return TEST_FAILED;
686 }
687
688 /* if the loop ended with a failing condition at any bit,
689 * lets look for the first previous success condition by unit
690 * stepping (minimal delay)
691 */
692 if (!success) {
693 pr_debug("Fail region (PHASE) found phase idx %d\n",
694 phase_idx);
695 pr_debug("Let's look for first success by DQS Unit steps\n");
696 /* This part, the algo always converge */
697 phase_idx--;
698
699 /* escape if we find a success condition
700 * or if out of delay range.
701 */
702 while (!success && dqs_unit_delay_index >= 0) {
703 DQS_unit_delay(phy, datx8,
704 dqs_unit_delay_index);
705 BIST_test(phy, datx8, &result);
706 success = result.test_result;
707 dqs_unit_delay_index--;
708 }
709 /* if the loop ended with a success condition,
710 * the last delay Right OK (before hold violation)
711 * condition is then defined as following:
712 */
713 if (success) {
714 /* Hold the dely parameters of the the last
715 * delay Right OK condition.
716 * -1 to get back to current condition
717 */
718 last_right_ok.phase = phase_idx;
719 /*+1 to get back to current condition */
720 last_right_ok.unit = dqs_unit_delay_index + 1;
721 last_right_ok.bits_delay = 0xFFFFFFFF;
722 pr_debug("Found %d\n", dqs_unit_delay_index);
723 } else {
724 /* the last OK condition is then with the
725 * previous phase_idx.
726 * -2 instead of -1 because at the last
727 * iteration of the while(),
728 * we incremented phase_idx
729 */
730 last_right_ok.phase = phase_idx - 1;
731 /* Nominal+1. Because we want the previous
732 * delay after reducing the phase delay.
733 */
734 last_right_ok.unit = 1;
735 last_right_ok.bits_delay = 0xFFFFFFFF;
736 pr_debug("Not Found : try previous phase %d\n",
737 phase_idx - 1);
738
739 DQS_phase_delay(phy, datx8, phase_idx - 1);
740 dqs_unit_delay_index = 0;
741 success = true;
742 while (success &&
743 (dqs_unit_delay_index <
744 MAX_DQS_UNIT_IDX)) {
745 DQS_unit_delay(phy, datx8,
746 dqs_unit_delay_index);
747 BIST_test(phy, datx8, &result);
748 success = result.test_result;
749 dqs_unit_delay_index++;
750 pr_debug("dqs_unit_delay_index = %d, result = %d\n",
751 dqs_unit_delay_index, success);
752 }
753
754 if (!success) {
755 last_right_ok.unit =
756 dqs_unit_delay_index - 1;
757 } else {
758 last_right_ok.unit = 0;
759 pr_debug("ERROR: failed region not FOUND");
760 }
761 }
762 } else {
763 /* we can't find a failing condition at all bits
764 * ==> Just hold the last test condition
765 * (the max DQS delay)
766 * which is the most likely,
767 * the closest to a hold violation
768 * If we can't find a Fail condition after
769 * the Pass region, stick at this position
770 * In order to have max chances to find a fail
771 * when reducing DQ delays.
772 */
773 last_right_ok.phase = MAX_DQS_PHASE_IDX;
774 last_right_ok.unit = MAX_DQS_UNIT_IDX;
775 last_right_ok.bits_delay = 0xFFFFFFFF;
776 pr_debug("Can't find the a fail condition\n");
777 }
778
779 /* step 2:
780 * if we arrive at this stage, it means that we found the last
781 * Right OK condition (by tweeking the DQS delay). Or we simply
782 * pushed DQS delay to the max
783 * This means that by reducing the delay on some DQ bits,
784 * we should find a failing condition.
785 */
786 printf("Byte %d, DQS unit = %d, phase = %d\n",
787 datx8, last_right_ok.unit, last_right_ok.phase);
788 pr_debug("Step2, unit = %d, phase = %d, bits delay=%x\n",
789 last_right_ok.unit, last_right_ok.phase,
790 last_right_ok.bits_delay);
791
792 /* Restore the last_right_ok condtion. */
793 DQS_unit_delay(phy, datx8, last_right_ok.unit);
794 DQS_phase_delay(phy, datx8, last_right_ok.phase);
795 writel(last_right_ok.bits_delay, DXNDQTR(phy, datx8));
796
797 /* train each bit
798 * reduce delay on each bit, and perform a write/read test
799 * and stop at the very first time it fails.
800 * the goal is the find the first failing condition
801 * for each bit.
802 * When we achieve this condition< for all the bits,
803 * we are sure they are aligned (+/- step resolution)
804 */
805 fail_found = 0;
806 for (bit_i = 0; bit_i < 8; bit_i++) {
807 if (ctrlc()) {
808 sprintf(string,
809 "interrupted at byte %d/%d, error=%d",
810 datx8 + 1, nb_bytes, error);
811 return error;
812 }
813 pr_debug("deskewing bit %d:\n", bit_i);
814 success = 1; /* init */
815 /* Set all DQDLYn to maximum value.
816 * Only bit_i will be down-delayed
817 * ==> if we have a fail, it will be definitely
818 * from bit_i
819 */
820 writel(0xFFFFFFFF, DXNDQTR(phy, datx8));
821 /* Arriving at this stage,
822 * we have a success condition with delay = 3;
823 */
824 bit_i_delay_index = 3;
825
826 /* escape if bit delay is out of range or
827 * if a fatil occurs
828 */
829 while ((bit_i_delay_index >= 0) && success) {
830 set_DQ_unit_delay(phy, datx8,
831 bit_i,
832 bit_i_delay_index);
833 BIST_test(phy, datx8, &result);
834 success = result.test_result;
835 bit_i_delay_index--;
836 }
837
838 /* if escape with a fail condition
839 * ==> save this position for bit_i
840 */
841 if (!success) {
842 /* save the delay position.
843 * Add 1 because the while loop ended with a --,
844 * and that we need to hold the last success
845 * delay
846 */
847 deskew_delay[datx8][bit_i] =
848 bit_i_delay_index + 2;
849 if (deskew_delay[datx8][bit_i] > 3)
850 deskew_delay[datx8][bit_i] = 3;
851
852 /* A flag that states we found at least a fail
853 * at one bit.
854 */
855 fail_found = 1;
856 pr_debug("Fail found on bit %d, for delay = %d => deskew[%d][%d] = %d\n",
857 bit_i, bit_i_delay_index + 1,
858 datx8, bit_i,
859 deskew_delay[datx8][bit_i]);
860 } else {
861 /* if we can find a success condition by
862 * back-delaying this bit, just set the delay
863 * to 0 (the best deskew
864 * possible) and mark the bit.
865 */
866 deskew_delay[datx8][bit_i] = 0;
867 /* set a flag that will be used later
868 * in the report.
869 */
870 deskew_non_converge[datx8][bit_i] = 1;
871 pr_debug("Fail not found on bit %d => deskew[%d][%d] = %d\n",
872 bit_i, datx8, bit_i,
873 deskew_delay[datx8][bit_i]);
874 }
875 }
876 pr_debug("**********byte %d tuning complete************\n",
877 datx8);
878 /* If we can't find any failure by back delaying DQ lines,
879 * hold the default values
880 */
881 if (!fail_found) {
882 for (bit_i = 0; bit_i < 8; bit_i++)
883 deskew_delay[datx8][bit_i] = 0;
884 pr_debug("The Deskew algorithm can't converge, there is too much margin in your design. Good job!\n");
885 }
886
887 apply_deskew_results(phy, datx8, deskew_delay,
888 deskew_non_converge);
889 /* Restore nominal value for DQS delay */
890 DQS_phase_delay(phy, datx8, 3);
891 DQS_unit_delay(phy, datx8, 3);
892 /* disable byte after byte bits deskew */
893 clrbits_le32(DXNGCR(phy, datx8), DDRPHYC_DXNGCR_DXEN);
894 } /* end of byte deskew */
895
896 /* re-enable all data bytes */
897 setbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
898 setbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
899 setbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
900 setbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
901
902 if (error) {
903 sprintf(string, "error = %d", error);
904 return TEST_FAILED;
905 }
906
907 return TEST_PASSED;
908 } /* end function */
909
910 /* Trim DQS timings and set it in the centre of data eye.
911 * Look for a PPPPF region, then look for a FPPP region and finally select
912 * the mid of the FPPPPPF region
913 */
914 static enum test_result eye_training(struct stm32mp1_ddrctl *ctl,
915 struct stm32mp1_ddrphy *phy, char *string)
916 {
917 /*Stores the DQS trim values (PHASE index, unit index) */
918 u8 eye_training_val[NUM_BYTES][2];
919 u8 byte = 0;
920 struct BIST_result result;
921 s8 dqs_unit_delay_index = 0;
922 s8 phase_idx = 0;
923 s8 dqs_unit_delay_index_pass = 0;
924 s8 phase_idx_pass = 0;
925 u8 success = 0;
926 u8 left_phase_bound_found, right_phase_bound_found;
927 u8 left_unit_bound_found, right_unit_bound_found;
928 u8 left_bound_found, right_bound_found;
929 struct tuning_position left_bound, right_bound;
930 u8 error = 0;
931 u8 nb_bytes = get_nb_bytes(ctl);
932
933 /*Disable DQS Drift Compensation*/
934 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
935 /*Disable all bytes*/
936 /* Disable automatic power down of DLL and IOs when disabling a byte
937 * (To avoid having to add programming and delay
938 * for a DLL re-lock when later re-enabling a disabled Byte Lane)
939 */
940 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
941
942 /*Disable all data bytes */
943 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
944 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
945 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
946 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
947
948 /* Config the BIST block */
949 config_BIST(ctl, phy);
950
951 for (byte = 0; byte < nb_bytes; byte++) {
952 if (ctrlc()) {
953 sprintf(string, "interrupted at byte %d/%d, error=%d",
954 byte + 1, nb_bytes, error);
955 return TEST_FAILED;
956 }
957 right_bound.phase = 0;
958 right_bound.unit = 0;
959
960 left_bound.phase = 0;
961 left_bound.unit = 0;
962
963 left_phase_bound_found = 0;
964 right_phase_bound_found = 0;
965
966 left_unit_bound_found = 0;
967 right_unit_bound_found = 0;
968
969 left_bound_found = 0;
970 right_bound_found = 0;
971
972 /* Enable Byte (DXNGCR, bit DXEN) */
973 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
974
975 /* Select the byte lane for comparison of read data */
976 BIST_datx8_sel(phy, byte);
977
978 /* Set DQS phase delay to the nominal value. */
979 phase_idx = _90deg;
980 phase_idx_pass = phase_idx;
981
982 /* Set DQS unit delay to the nominal value. */
983 dqs_unit_delay_index = 3;
984 dqs_unit_delay_index_pass = dqs_unit_delay_index;
985 success = 0;
986
987 pr_debug("STEP0: Find Init delay\n");
988 /* STEP0: Find Init delay: a delay that put the system
989 * in a "Pass" condition then (TODO) update
990 * dqs_unit_delay_index_pass & phase_idx_pass
991 */
992 DQS_unit_delay(phy, byte, dqs_unit_delay_index);
993 DQS_phase_delay(phy, byte, phase_idx);
994 BIST_test(phy, byte, &result);
995 success = result.test_result;
996 /* If we have a fail in the nominal condition */
997 if (!success) {
998 /* Look at the left */
999 while (phase_idx >= 0 && !success) {
1000 phase_idx--;
1001 DQS_phase_delay(phy, byte, phase_idx);
1002 BIST_test(phy, byte, &result);
1003 success = result.test_result;
1004 }
1005 }
1006 if (!success) {
1007 /* if we can't find pass condition,
1008 * then look at the right
1009 */
1010 phase_idx = _90deg;
1011 while (phase_idx <= MAX_DQS_PHASE_IDX &&
1012 !success) {
1013 phase_idx++;
1014 DQS_phase_delay(phy, byte,
1015 phase_idx);
1016 BIST_test(phy, byte, &result);
1017 success = result.test_result;
1018 }
1019 }
1020 /* save the pass condition */
1021 if (success) {
1022 phase_idx_pass = phase_idx;
1023 } else {
1024 printf("Result: Failed ");
1025 printf("[Cannot DQS timings, ");
1026 printf("there is no PASS region]\n");
1027 error++;
1028 continue;
1029 }
1030
1031 if (ctrlc()) {
1032 sprintf(string, "interrupted at byte %d/%d, error=%d",
1033 byte + 1, nb_bytes, error);
1034 return TEST_FAILED;
1035 }
1036 pr_debug("STEP1: Find LEFT PHASE DQS Bound\n");
1037 /* STEP1: Find LEFT PHASE DQS Bound */
1038 while ((phase_idx >= 0) &&
1039 (phase_idx <= MAX_DQS_PHASE_IDX) &&
1040 !left_phase_bound_found) {
1041 DQS_unit_delay(phy, byte,
1042 dqs_unit_delay_index);
1043 DQS_phase_delay(phy, byte,
1044 phase_idx);
1045 BIST_test(phy, byte, &result);
1046 success = result.test_result;
1047
1048 /*TODO: Manage the case were at the beginning
1049 * there is already a fail
1050 */
1051 if (!success) {
1052 /* the last pass condition */
1053 left_bound.phase = ++phase_idx;
1054 left_phase_bound_found = 1;
1055 } else if (success) {
1056 phase_idx--;
1057 }
1058 }
1059 if (!left_phase_bound_found) {
1060 left_bound.phase = 0;
1061 phase_idx = 0;
1062 }
1063 /* If not found, lets take 0 */
1064
1065 if (ctrlc()) {
1066 sprintf(string, "interrupted at byte %d/%d, error=%d",
1067 byte + 1, nb_bytes, error);
1068 return TEST_FAILED;
1069 }
1070 pr_debug("STEP2: Find UNIT left bound\n");
1071 /* STEP2: Find UNIT left bound */
1072 while ((dqs_unit_delay_index >= 0) &&
1073 !left_unit_bound_found) {
1074 DQS_unit_delay(phy, byte,
1075 dqs_unit_delay_index);
1076 DQS_phase_delay(phy, byte, phase_idx);
1077 BIST_test(phy, byte, &result);
1078 success = result.test_result;
1079 if (!success) {
1080 left_bound.unit =
1081 ++dqs_unit_delay_index;
1082 left_unit_bound_found = 1;
1083 left_bound_found = 1;
1084 } else if (success) {
1085 dqs_unit_delay_index--;
1086 }
1087 }
1088
1089 /* If not found, lets take 0 */
1090 if (!left_unit_bound_found)
1091 left_bound.unit = 0;
1092
1093 if (ctrlc()) {
1094 sprintf(string, "interrupted at byte %d/%d, error=%d",
1095 byte + 1, nb_bytes, error);
1096 return TEST_FAILED;
1097 }
1098 pr_debug("STEP3: Find PHase right bound\n");
1099 /* STEP3: Find PHase right bound, start with "pass"
1100 * condition
1101 */
1102
1103 /* Set DQS phase delay to the pass value. */
1104 phase_idx = phase_idx_pass;
1105
1106 /* Set DQS unit delay to the pass value. */
1107 dqs_unit_delay_index = dqs_unit_delay_index_pass;
1108
1109 while ((phase_idx <= MAX_DQS_PHASE_IDX) &&
1110 !right_phase_bound_found) {
1111 DQS_unit_delay(phy, byte,
1112 dqs_unit_delay_index);
1113 DQS_phase_delay(phy, byte, phase_idx);
1114 BIST_test(phy, byte, &result);
1115 success = result.test_result;
1116 if (!success) {
1117 /* the last pass condition */
1118 right_bound.phase = --phase_idx;
1119 right_phase_bound_found = 1;
1120 } else if (success) {
1121 phase_idx++;
1122 }
1123 }
1124
1125 /* If not found, lets take the max value */
1126 if (!right_phase_bound_found) {
1127 right_bound.phase = MAX_DQS_PHASE_IDX;
1128 phase_idx = MAX_DQS_PHASE_IDX;
1129 }
1130
1131 if (ctrlc()) {
1132 sprintf(string, "interrupted at byte %d/%d, error=%d",
1133 byte + 1, nb_bytes, error);
1134 return TEST_FAILED;
1135 }
1136 pr_debug("STEP4: Find UNIT right bound\n");
1137 /* STEP4: Find UNIT right bound */
1138 while ((dqs_unit_delay_index <= MAX_DQS_UNIT_IDX) &&
1139 !right_unit_bound_found) {
1140 DQS_unit_delay(phy, byte,
1141 dqs_unit_delay_index);
1142 DQS_phase_delay(phy, byte, phase_idx);
1143 BIST_test(phy, byte, &result);
1144 success = result.test_result;
1145 if (!success) {
1146 right_bound.unit =
1147 --dqs_unit_delay_index;
1148 right_unit_bound_found = 1;
1149 right_bound_found = 1;
1150 } else if (success) {
1151 dqs_unit_delay_index++;
1152 }
1153 }
1154 /* If not found, lets take the max value */
1155 if (!right_unit_bound_found)
1156 right_bound.unit = MAX_DQS_UNIT_IDX;
1157
1158 /* If we found a regular FAil Pass FAil pattern
1159 * FFPPPPPPFF
1160 * OR PPPPPFF Or FFPPPPP
1161 */
1162
1163 if (left_bound_found || right_bound_found) {
1164 eye_training_val[byte][0] = (right_bound.phase +
1165 left_bound.phase) / 2;
1166 eye_training_val[byte][1] = (right_bound.unit +
1167 left_bound.unit) / 2;
1168
1169 /* If we already lost 1/2PHASE Tuning,
1170 * let's try to recover by ++ on unit
1171 */
1172 if (((right_bound.phase + left_bound.phase) % 2 == 1) &&
1173 eye_training_val[byte][1] != MAX_DQS_UNIT_IDX)
1174 eye_training_val[byte][1]++;
1175 pr_debug("** found phase : %d - %d & unit %d - %d\n",
1176 right_bound.phase, left_bound.phase,
1177 right_bound.unit, left_bound.unit);
1178 pr_debug("** calculating mid region: phase: %d unit: %d (nominal is 3)\n",
1179 eye_training_val[byte][0],
1180 eye_training_val[byte][1]);
1181 } else {
1182 /* PPPPPPPPPP, we're already good.
1183 * Set nominal values.
1184 */
1185 eye_training_val[byte][0] = 3;
1186 eye_training_val[byte][1] = 3;
1187 }
1188 DQS_phase_delay(phy, byte, eye_training_val[byte][0]);
1189 DQS_unit_delay(phy, byte, eye_training_val[byte][1]);
1190
1191 printf("Byte %d, DQS unit = %d, phase = %d\n",
1192 byte,
1193 eye_training_val[byte][1],
1194 eye_training_val[byte][0]);
1195 }
1196
1197 if (error) {
1198 sprintf(string, "error = %d", error);
1199 return TEST_FAILED;
1200 }
1201
1202 return TEST_PASSED;
1203 }
1204
1205 static void display_reg_results(struct stm32mp1_ddrphy *phy, u8 byte)
1206 {
1207 u8 i = 0;
1208
1209 printf("Byte %d Dekew result, bit0 delay, bit1 delay...bit8 delay\n ",
1210 byte);
1211
1212 for (i = 0; i < 8; i++)
1213 printf("%d ", DQ_unit_index(phy, byte, i));
1214 printf("\n");
1215
1216 printf("dxndllcr: [%08x] val:%08x\n",
1217 DXNDLLCR(phy, byte),
1218 readl(DXNDLLCR(phy, byte)));
1219 printf("dxnqdstr: [%08x] val:%08x\n",
1220 DXNDQSTR(phy, byte),
1221 readl(DXNDQSTR(phy, byte)));
1222 printf("dxndqtr: [%08x] val:%08x\n",
1223 DXNDQTR(phy, byte),
1224 readl(DXNDQTR(phy, byte)));
1225 }
1226
1227 /* analyse the dgs gating log table, and determine the midpoint.*/
1228 static u8 set_midpoint_read_dqs_gating(struct stm32mp1_ddrphy *phy, u8 byte,
1229 u8 dqs_gating[NUM_BYTES]
1230 [MAX_GSL_IDX + 1]
1231 [MAX_GPS_IDX + 1])
1232 {
1233 /* stores the dqs gate values (gsl index, gps index) */
1234 u8 dqs_gate_values[NUM_BYTES][2];
1235 u8 gsl_idx, gps_idx = 0;
1236 u8 left_bound_idx[2] = {0, 0};
1237 u8 right_bound_idx[2] = {0, 0};
1238 u8 left_bound_found = 0;
1239 u8 right_bound_found = 0;
1240 u8 intermittent = 0;
1241 u8 value;
1242
1243 for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1244 for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1245 value = dqs_gating[byte][gsl_idx][gps_idx];
1246 if (value == 1 && left_bound_found == 0) {
1247 left_bound_idx[0] = gsl_idx;
1248 left_bound_idx[1] = gps_idx;
1249 left_bound_found = 1;
1250 } else if (value == 0 &&
1251 left_bound_found == 1 &&
1252 !right_bound_found) {
1253 if (gps_idx == 0) {
1254 right_bound_idx[0] = gsl_idx - 1;
1255 right_bound_idx[1] = MAX_GPS_IDX;
1256 } else {
1257 right_bound_idx[0] = gsl_idx;
1258 right_bound_idx[1] = gps_idx - 1;
1259 }
1260 right_bound_found = 1;
1261 } else if (value == 1 &&
1262 right_bound_found == 1) {
1263 intermittent = 1;
1264 }
1265 }
1266 }
1267
1268 /* if only ppppppp is found, there is no mid region. */
1269 if (left_bound_idx[0] == 0 && left_bound_idx[1] == 0 &&
1270 right_bound_idx[0] == 0 && right_bound_idx[1] == 0)
1271 intermittent = 1;
1272
1273 /*if we found a regular fail pass fail pattern ffppppppff
1274 * or pppppff or ffppppp
1275 */
1276 if (!intermittent) {
1277 /*if we found a regular fail pass fail pattern ffppppppff
1278 * or pppppff or ffppppp
1279 */
1280 if (left_bound_found || right_bound_found) {
1281 pr_debug("idx0(%d): %d %d idx1(%d) : %d %d\n",
1282 left_bound_found,
1283 right_bound_idx[0], left_bound_idx[0],
1284 right_bound_found,
1285 right_bound_idx[1], left_bound_idx[1]);
1286 dqs_gate_values[byte][0] =
1287 (right_bound_idx[0] + left_bound_idx[0]) / 2;
1288 dqs_gate_values[byte][1] =
1289 (right_bound_idx[1] + left_bound_idx[1]) / 2;
1290 /* if we already lost 1/2gsl tuning,
1291 * let's try to recover by ++ on gps
1292 */
1293 if (((right_bound_idx[0] +
1294 left_bound_idx[0]) % 2 == 1) &&
1295 dqs_gate_values[byte][1] != MAX_GPS_IDX)
1296 dqs_gate_values[byte][1]++;
1297 /* if we already lost 1/2gsl tuning and gps is on max*/
1298 else if (((right_bound_idx[0] +
1299 left_bound_idx[0]) % 2 == 1) &&
1300 dqs_gate_values[byte][1] == MAX_GPS_IDX) {
1301 dqs_gate_values[byte][1] = 0;
1302 dqs_gate_values[byte][0]++;
1303 }
1304 /* if we have gsl left and write limit too close
1305 * (difference=1)
1306 */
1307 if (((right_bound_idx[0] - left_bound_idx[0]) == 1)) {
1308 dqs_gate_values[byte][1] = (left_bound_idx[1] +
1309 right_bound_idx[1] +
1310 4) / 2;
1311 if (dqs_gate_values[byte][1] >= 4) {
1312 dqs_gate_values[byte][0] =
1313 right_bound_idx[0];
1314 dqs_gate_values[byte][1] -= 4;
1315 } else {
1316 dqs_gate_values[byte][0] =
1317 left_bound_idx[0];
1318 }
1319 }
1320 pr_debug("*******calculating mid region: system latency: %d phase: %d********\n",
1321 dqs_gate_values[byte][0],
1322 dqs_gate_values[byte][1]);
1323 pr_debug("*******the nominal values were system latency: 0 phase: 2*******\n");
1324 }
1325 } else {
1326 /* if intermitant, restore defaut values */
1327 pr_debug("dqs gating:no regular fail/pass/fail found. defaults values restored.\n");
1328 dqs_gate_values[byte][0] = 0;
1329 dqs_gate_values[byte][1] = 2;
1330 }
1331 set_r0dgsl_delay(phy, byte, dqs_gate_values[byte][0]);
1332 set_r0dgps_delay(phy, byte, dqs_gate_values[byte][1]);
1333 printf("Byte %d, R0DGSL = %d, R0DGPS = %d\n",
1334 byte, dqs_gate_values[byte][0], dqs_gate_values[byte][1]);
1335
1336 /* return 0 if intermittent or if both left_bound
1337 * and right_bound are not found
1338 */
1339 return !(intermittent || (left_bound_found && right_bound_found));
1340 }
1341
1342 static enum test_result read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1343 struct stm32mp1_ddrphy *phy,
1344 char *string)
1345 {
1346 /* stores the log of pass/fail */
1347 u8 dqs_gating[NUM_BYTES][MAX_GSL_IDX + 1][MAX_GPS_IDX + 1];
1348 u8 byte, gsl_idx, gps_idx = 0;
1349 struct BIST_result result;
1350 u8 success = 0;
1351 u8 nb_bytes = get_nb_bytes(ctl);
1352
1353 memset(dqs_gating, 0x0, sizeof(dqs_gating));
1354
1355 /*disable dqs drift compensation*/
1356 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP);
1357 /*disable all bytes*/
1358 /* disable automatic power down of dll and ios when disabling a byte
1359 * (to avoid having to add programming and delay
1360 * for a dll re-lock when later re-enabling a disabled byte lane)
1361 */
1362 clrbits_le32(&phy->pgcr, DDRPHYC_PGCR_PDDISDX);
1363
1364 /* disable all data bytes */
1365 clrbits_le32(&phy->dx0gcr, DDRPHYC_DXNGCR_DXEN);
1366 clrbits_le32(&phy->dx1gcr, DDRPHYC_DXNGCR_DXEN);
1367 clrbits_le32(&phy->dx2gcr, DDRPHYC_DXNGCR_DXEN);
1368 clrbits_le32(&phy->dx3gcr, DDRPHYC_DXNGCR_DXEN);
1369
1370 /* config the bist block */
1371 config_BIST(ctl, phy);
1372
1373 for (byte = 0; byte < nb_bytes; byte++) {
1374 if (ctrlc()) {
1375 sprintf(string, "interrupted at byte %d/%d",
1376 byte + 1, nb_bytes);
1377 return TEST_FAILED;
1378 }
1379 /* enable byte x (dxngcr, bit dxen) */
1380 setbits_le32(DXNGCR(phy, byte), DDRPHYC_DXNGCR_DXEN);
1381
1382 /* select the byte lane for comparison of read data */
1383 BIST_datx8_sel(phy, byte);
1384 for (gsl_idx = 0; gsl_idx <= MAX_GSL_IDX; gsl_idx++) {
1385 for (gps_idx = 0; gps_idx <= MAX_GPS_IDX; gps_idx++) {
1386 if (ctrlc()) {
1387 sprintf(string,
1388 "interrupted at byte %d/%d",
1389 byte + 1, nb_bytes);
1390 return TEST_FAILED;
1391 }
1392 /* write cfg to dxndqstr */
1393 set_r0dgsl_delay(phy, byte, gsl_idx);
1394 set_r0dgps_delay(phy, byte, gps_idx);
1395
1396 BIST_test(phy, byte, &result);
1397 success = result.test_result;
1398 if (success)
1399 dqs_gating[byte][gsl_idx][gps_idx] = 1;
1400 itm_soft_reset(phy);
1401 }
1402 }
1403 set_midpoint_read_dqs_gating(phy, byte, dqs_gating);
1404 /* dummy reads */
1405 readl(0xc0000000);
1406 readl(0xc0000000);
1407 }
1408
1409 /* re-enable drift compensation */
1410 /* setbits_le32(&phy->pgcr, DDRPHYC_PGCR_DFTCMP); */
1411 return TEST_PASSED;
1412 }
1413
1414 /****************************************************************
1415 * TEST
1416 ****************************************************************
1417 */
1418 static enum test_result do_read_dqs_gating(struct stm32mp1_ddrctl *ctl,
1419 struct stm32mp1_ddrphy *phy,
1420 char *string, int argc,
1421 char *argv[])
1422 {
1423 u32 rfshctl3 = readl(&ctl->rfshctl3);
1424 u32 pwrctl = readl(&ctl->pwrctl);
1425 u32 derateen = readl(&ctl->derateen);
1426 enum test_result res;
1427
1428 writel(0x0, &ctl->derateen);
1429 stm32mp1_refresh_disable(ctl);
1430
1431 res = read_dqs_gating(ctl, phy, string);
1432
1433 stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1434 writel(derateen, &ctl->derateen);
1435
1436 return res;
1437 }
1438
1439 static enum test_result do_bit_deskew(struct stm32mp1_ddrctl *ctl,
1440 struct stm32mp1_ddrphy *phy,
1441 char *string, int argc, char *argv[])
1442 {
1443 u32 rfshctl3 = readl(&ctl->rfshctl3);
1444 u32 pwrctl = readl(&ctl->pwrctl);
1445 u32 derateen = readl(&ctl->derateen);
1446 enum test_result res;
1447
1448 writel(0x0, &ctl->derateen);
1449 stm32mp1_refresh_disable(ctl);
1450
1451 res = bit_deskew(ctl, phy, string);
1452
1453 stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1454 writel(derateen, &ctl->derateen);
1455
1456 return res;
1457 }
1458
1459 static enum test_result do_eye_training(struct stm32mp1_ddrctl *ctl,
1460 struct stm32mp1_ddrphy *phy,
1461 char *string, int argc, char *argv[])
1462 {
1463 u32 rfshctl3 = readl(&ctl->rfshctl3);
1464 u32 pwrctl = readl(&ctl->pwrctl);
1465 u32 derateen = readl(&ctl->derateen);
1466 enum test_result res;
1467
1468 writel(0x0, &ctl->derateen);
1469 stm32mp1_refresh_disable(ctl);
1470
1471 res = eye_training(ctl, phy, string);
1472
1473 stm32mp1_refresh_restore(ctl, rfshctl3, pwrctl);
1474 writel(derateen, &ctl->derateen);
1475
1476 return res;
1477 }
1478
1479 static enum test_result do_display(struct stm32mp1_ddrctl *ctl,
1480 struct stm32mp1_ddrphy *phy,
1481 char *string, int argc, char *argv[])
1482 {
1483 int byte;
1484 u8 nb_bytes = get_nb_bytes(ctl);
1485
1486 for (byte = 0; byte < nb_bytes; byte++)
1487 display_reg_results(phy, byte);
1488
1489 return TEST_PASSED;
1490 }
1491
1492 static enum test_result do_bist_config(struct stm32mp1_ddrctl *ctl,
1493 struct stm32mp1_ddrphy *phy,
1494 char *string, int argc, char *argv[])
1495 {
1496 unsigned long value;
1497
1498 if (argc > 0) {
1499 if (strict_strtoul(argv[0], 0, &value) < 0) {
1500 sprintf(string, "invalid nbErr %s", argv[0]);
1501 return TEST_FAILED;
1502 }
1503 BIST_error_max = value;
1504 }
1505 if (argc > 1) {
1506 if (strict_strtoul(argv[1], 0, &value) < 0) {
1507 sprintf(string, "invalid Seed %s", argv[1]);
1508 return TEST_FAILED;
1509 }
1510 BIST_seed = value;
1511 }
1512 printf("Bist.nbErr = %d\n", BIST_error_max);
1513 if (BIST_seed)
1514 printf("Bist.Seed = 0x%x\n", BIST_seed);
1515 else
1516 printf("Bist.Seed = random\n");
1517
1518 return TEST_PASSED;
1519 }
1520
1521 /****************************************************************
1522 * TEST Description
1523 ****************************************************************
1524 */
1525
1526 const struct test_desc tuning[] = {
1527 {do_read_dqs_gating, "Read DQS gating",
1528 "software read DQS Gating", "", 0 },
1529 {do_bit_deskew, "Bit de-skew", "", "", 0 },
1530 {do_eye_training, "Eye Training", "or DQS training", "", 0 },
1531 {do_display, "Display registers", "", "", 0 },
1532 {do_bist_config, "Bist config", "[nbErr] [seed]",
1533 "configure Bist test", 2},
1534 };
1535
1536 const int tuning_nb = ARRAY_SIZE(tuning);
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