drivers/reset/Kconfig

   1 menu "Reset Controller Support"
   2
   3 config DM_RESET
   4         bool "Enable reset controllers using Driver Model"
   5         depends on DM && OF_CONTROL
   6         help
   7           Enable support for the reset controller driver class. Many hardware
   8           modules are equipped with a reset signal, typically driven by some
   9           reset controller hardware module within the chip. In U-Boot, reset
  10           controller drivers allow control over these reset signals. In some
  11           cases this API is applicable to chips outside the CPU as well,
  12           although driving such reset isgnals using GPIOs may be more
  13           appropriate in this case.
  14
  15 config SANDBOX_RESET
  16         bool "Enable the sandbox reset test driver"
  17         depends on DM_MAILBOX && SANDBOX
  18         help
  19           Enable support for a test reset controller implementation, which
  20           simply accepts requests to reset various HW modules without actually
  21           doing anything beyond a little error checking.
  22
  23 config TEGRA_CAR_RESET
  24         bool "Enable Tegra CAR-based reset driver"
  25         depends on TEGRA_CAR
  26         help
  27           Enable support for manipulating Tegra's on-SoC reset signals via
  28           direct register access to the Tegra CAR (Clock And Reset controller).
  29
  30 config TEGRA186_RESET
  31         bool "Enable Tegra186 BPMP-based reset driver"
  32         depends on TEGRA186_BPMP
  33         help
  34           Enable support for manipulating Tegra's on-SoC reset signals via IPC
  35           requests to the BPMP (Boot and Power Management Processor).
  36
  37 config RESET_UNIPHIER
  38         bool "Reset controller driver for UniPhier SoCs"
  39         depends on ARCH_UNIPHIER
  40         default y
  41         help
  42           Support for reset controllers on UniPhier SoCs.
  43           Say Y if you want to control reset signals provided by System Control
  44           block, Media I/O block, Peripheral Block.
  45
  46 endmenu